1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Socionext Inc.
3*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/bitops.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/errno.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/sizes.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "pll.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* PLL type: SSC */
17*4882a593Smuzhiyun #define SC_PLLCTRL_SSC_DK_MASK GENMASK(14, 0)
18*4882a593Smuzhiyun #define SC_PLLCTRL_SSC_EN BIT(31)
19*4882a593Smuzhiyun #define SC_PLLCTRL2_NRSTDS BIT(28)
20*4882a593Smuzhiyun #define SC_PLLCTRL2_SSC_JK_MASK GENMASK(26, 0)
21*4882a593Smuzhiyun #define SC_PLLCTRL3_REGI_SHIFT 16
22*4882a593Smuzhiyun #define SC_PLLCTRL3_REGI_MASK GENMASK(19, 16)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* PLL type: VPLL27 */
25*4882a593Smuzhiyun #define SC_VPLL27CTRL_WP BIT(0)
26*4882a593Smuzhiyun #define SC_VPLL27CTRL3_K_LD BIT(28)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* PLL type: DSPLL */
29*4882a593Smuzhiyun #define SC_DSPLLCTRL2_K_LD BIT(28)
30*4882a593Smuzhiyun
uniphier_ld20_sscpll_init(unsigned long reg_base,unsigned int freq,unsigned int ssc_rate,unsigned int divn)31*4882a593Smuzhiyun int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
32*4882a593Smuzhiyun unsigned int ssc_rate, unsigned int divn)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun void __iomem *base;
35*4882a593Smuzhiyun u32 tmp;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun base = ioremap(reg_base, SZ_16);
38*4882a593Smuzhiyun if (!base)
39*4882a593Smuzhiyun return -ENOMEM;
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun if (freq != UNIPHIER_PLL_FREQ_DEFAULT) {
42*4882a593Smuzhiyun tmp = readl(base); /* SSCPLLCTRL */
43*4882a593Smuzhiyun tmp &= ~SC_PLLCTRL_SSC_DK_MASK;
44*4882a593Smuzhiyun tmp |= (487 * freq * ssc_rate / divn / 512) &
45*4882a593Smuzhiyun SC_PLLCTRL_SSC_DK_MASK;
46*4882a593Smuzhiyun writel(tmp, base);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun tmp = readl(base + 4);
49*4882a593Smuzhiyun tmp &= ~SC_PLLCTRL2_SSC_JK_MASK;
50*4882a593Smuzhiyun tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun udelay(50);
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun tmp = readl(base + 4); /* SSCPLLCTRL2 */
56*4882a593Smuzhiyun tmp |= SC_PLLCTRL2_NRSTDS;
57*4882a593Smuzhiyun writel(tmp, base + 4);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun iounmap(base);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)64*4882a593Smuzhiyun int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun void __iomem *base;
67*4882a593Smuzhiyun u32 tmp;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun base = ioremap(reg_base, SZ_16);
70*4882a593Smuzhiyun if (!base)
71*4882a593Smuzhiyun return -ENOMEM;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun tmp = readl(base); /* SSCPLLCTRL */
74*4882a593Smuzhiyun tmp |= SC_PLLCTRL_SSC_EN;
75*4882a593Smuzhiyun writel(tmp, base);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun iounmap(base);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
uniphier_ld20_sscpll_set_regi(unsigned long reg_base,unsigned regi)82*4882a593Smuzhiyun int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun void __iomem *base;
85*4882a593Smuzhiyun u32 tmp;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun base = ioremap(reg_base, SZ_16);
88*4882a593Smuzhiyun if (!base)
89*4882a593Smuzhiyun return -ENOMEM;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun tmp = readl(base + 8); /* SSCPLLCTRL3 */
92*4882a593Smuzhiyun tmp &= ~SC_PLLCTRL3_REGI_MASK;
93*4882a593Smuzhiyun tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
94*4882a593Smuzhiyun writel(tmp, base + 8);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun iounmap(base);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return 0;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
uniphier_ld20_vpll27_init(unsigned long reg_base)101*4882a593Smuzhiyun int uniphier_ld20_vpll27_init(unsigned long reg_base)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun void __iomem *base;
104*4882a593Smuzhiyun u32 tmp;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun base = ioremap(reg_base, SZ_16);
107*4882a593Smuzhiyun if (!base)
108*4882a593Smuzhiyun return -ENOMEM;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun tmp = readl(base); /* VPLL27CTRL */
111*4882a593Smuzhiyun tmp |= SC_VPLL27CTRL_WP; /* write protect off */
112*4882a593Smuzhiyun writel(tmp, base);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun tmp = readl(base + 8); /* VPLL27CTRL3 */
115*4882a593Smuzhiyun tmp |= SC_VPLL27CTRL3_K_LD;
116*4882a593Smuzhiyun writel(tmp, base + 8);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun tmp = readl(base); /* VPLL27CTRL */
119*4882a593Smuzhiyun tmp &= ~SC_VPLL27CTRL_WP; /* write protect on */
120*4882a593Smuzhiyun writel(tmp, base);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun iounmap(base);
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return 0;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
uniphier_ld20_dspll_init(unsigned long reg_base)127*4882a593Smuzhiyun int uniphier_ld20_dspll_init(unsigned long reg_base)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun void __iomem *base;
130*4882a593Smuzhiyun u32 tmp;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun base = ioremap(reg_base, SZ_16);
133*4882a593Smuzhiyun if (!base)
134*4882a593Smuzhiyun return -ENOMEM;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun tmp = readl(base + 4); /* DSPLLCTRL2 */
137*4882a593Smuzhiyun tmp |= SC_DSPLLCTRL2_K_LD;
138*4882a593Smuzhiyun writel(tmp, base + 4);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun iounmap(base);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144