1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2016 Socionext Inc. 3*4882a593Smuzhiyun * Author: Masahiro Yamada <yamada.masahiro@socionext.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef MACH_PLL_H 9*4882a593Smuzhiyun #define MACH_PLL_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define UNIPHIER_PLL_FREQ_DEFAULT (0) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun void uniphier_ld4_dpll_ssc_en(void); 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, 16*4882a593Smuzhiyun unsigned int ssc_rate, unsigned int divn); 17*4882a593Smuzhiyun int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base); 18*4882a593Smuzhiyun int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi); 19*4882a593Smuzhiyun int uniphier_ld20_vpll27_init(unsigned long reg_base); 20*4882a593Smuzhiyun int uniphier_ld20_dspll_init(unsigned long reg_base); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #endif /* MACH_PLL_H */ 23