Searched refs:crlapb_base (Results 1 – 5 of 5) sorted by relevance
98 tmp = readl(&crlapb_base->rst_lpd_top); in set_r5_reset()105 writel(tmp, &crlapb_base->rst_lpd_top); in set_r5_reset()112 tmp = readl(&crlapb_base->rst_lpd_top); in release_r5_reset()119 writel(tmp, &crlapb_base->rst_lpd_top); in release_r5_reset()126 tmp = readl(&crlapb_base->cpu_r5_ctrl); in enable_clock_r5()128 writel(tmp, &crlapb_base->cpu_r5_ctrl); in enable_clock_r5()159 u32 val = readl(&crlapb_base->rst_lpd_top); in cpu_status()
41 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()45 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()73 &crlapb_base->boot_mode); in spl_boot_device()76 reg = readl(&crlapb_base->boot_mode); in spl_boot_device()
40 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()44 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()72 &crlapb_base->boot_mode); in spl_boot_device()75 reg = readl(&crlapb_base->boot_mode); in spl_boot_device()
192 val = readl(&crlapb_base->timestamp_ref_ctrl); in board_early_init_r()196 val = readl(&crlapb_base->timestamp_ref_ctrl); in board_early_init_r()198 writel(val, &crlapb_base->timestamp_ref_ctrl); in board_early_init_r()266 reg = readl(&crlapb_base->boot_mode); in board_late_init()
48 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) macro