Searched refs:PLLE_AUX (Results 1 – 6 of 6) sorted by relevance
| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra210/ |
| H A D | clock.c | 1144 #define PLLE_AUX 0x48c macro
1167 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
1169 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
1245 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
1250 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
1256 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
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| /OK3568_Linux_fs/kernel/drivers/clk/tegra/ |
| H A D | clk-tegra30.c | 81 #define PLLE_AUX 0x48c macro
882 clk_base + PLLE_AUX, 2, 1, 0, NULL); in tegra30_pll_init()
1050 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
1055 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra30_periph_clk_init()
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| H A D | clk-tegra124.c | 62 #define PLLE_AUX 0x48c macro
479 .aux_reg = PLLE_AUX,
1058 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
1064 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra124_periph_clk_init()
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| H A D | clk-tegra114.c | 93 #define PLLE_AUX 0x48c macro
563 .aux_reg = PLLE_AUX,
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| H A D | clk-tegra210.c | 92 #define PLLE_AUX 0x48c macro
1922 .aux_reg = PLLE_AUX,
3093 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
3099 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX, in tegra210_periph_clk_init()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 958 #define PLLE_AUX 0x48c macro
971 value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
974 writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX); in tegra_plle_enable()
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