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Searched refs:PCLK_PIPEPHY0 (Results 1 – 6 of 6) sorted by relevance

/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/
H A Dphy-rockchip-naneng-combphy.txt29 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
/OK3568_Linux_fs/u-boot/include/dt-bindings/clock/
H A Drk3568-cru.h443 #define PCLK_PIPEPHY0 380 macro
/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Drk3568-cru.h443 #define PCLK_PIPEPHY0 380 macro
/OK3568_Linux_fs/kernel/drivers/clk/rockchip/
H A Dclk-rk3568.c1466 GATE(PCLK_PIPEPHY0, "pclk_pipephy0", "pclk_top", 0,
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3568.dtsi2636 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>;
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3568.dtsi3468 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,