1ROCKCHIP COMBO PHY WITH NANENG IP BLOCK 2 3Required properties (phy (parent) node): 4 - compatible : should be one of the listed compatibles: 5 * "rockchip,rk3568-naneng-combphy" 6 - reg : the address offset of grf for combo-phy configuration. 7 - rockchip,pipe-grf : phandle to the syscon managing the "pipe general register files" 8 - rockchip,pipe-phy-grf: phandle to the syscon managing the "phy general register files" 9 - clocks : phandle + phy specifier pair, for the input clocks of phy. 10 - clock-names : input clocks name of phy. 11 - resets : phandle + reset specifier pairs. 12 - reset-names : reset names of phy. 13 - #clock-cells : should be 1. 14 15Optional properties: 16 - assigned-clocks : phandle of refclk. 17 - assigned-clock-parents : parent of clk_xxx_osc or clk_xxx_div. 18 Refer to clk/clock-bindings.txt for generic clock 19 consumer properties. 20 - rockchip,dis-u3otg0-port: when set, disable the u3 root port of otg0 host. 21 - rockchip,dis-u3otg1-port: when set, disable the u3 root port of otg1 host. 22 23Example: 24 25combphy0: phy@fe820000 { 26 compatible = "rockchip,rk3568-naneng-combphy"; 27 reg = <0x0 0xfe820000 0x0 0x100>; 28 #phy-cells = <1>; 29 clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>; 30 clock-names = "refclk", "apbclk"; 31 resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>; 32 reset-names = "combphy-apb", "combphy"; 33 rockchip,pipe-grf = <&pipegrf>; 34 rockchip,pipe-phy-grf = <&pipe_phy_grf0>; 35 status = "disabled"; 36}; 37