Searched refs:MAX_CS (Results 1 – 18 of 18) sorted by relevance
18 static u32 xor_regs_base_backup[MAX_CS];19 static u32 xor_regs_mask_backup[MAX_CS];29 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()31 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()51 for (ui = 0; ui < MAX_CS; ui++) { in mv_sys_xor_init()90 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_finish()92 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_finish()
192 extern u16 odt_static[ODT_OPT][MAX_CS];193 extern u16 odt_dynamic[ODT_OPT][MAX_CS];647 if (cs_num > MAX_CS) {649 MAX_CS, 1);662 for (cs = 0; cs < MAX_CS; cs += 2) {684 MAX_CS, 1);897 for (cs = 0; cs < MAX_CS; cs++) {921 for (cs = 0; cs < MAX_CS; cs++) {937 for (cs = 0; cs < MAX_CS; cs++) {1014 for (cs = 0; cs < MAX_CS; cs++) {[all …]
53 extern u16 odt_static[ODT_OPT][MAX_CS];54 extern u16 odt_dynamic[ODT_OPT][MAX_CS];107 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw()229 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()431 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_wl_supplement()530 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()619 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_hw_reg_dimm()661 u32 res[MAX_CS]; in ddr3_write_leveling_sw()679 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_write_leveling_sw()719 memset(dram_info->wl_val, 0, sizeof(u32) * MAX_CS * MAX_PUP_NUM * 7); in ddr3_write_leveling_sw()[all …]
44 extern u16 odt_dynamic[ODT_OPT][MAX_CS];48 extern u16 odt_static[ODT_OPT][MAX_CS];196 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()442 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()468 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()676 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_high_2_low()1005 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()1137 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()1163 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()1436 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dfs_low_2_high()
42 u16 odt_static[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */61 u16 odt_dynamic[ODT_OPT][MAX_CS] = { /* NearEnd/FarEnd */
169 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()185 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()232 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_save_and_set_training_windows()1077 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_get_cs_num_from_reg()
17 #define MAX_CS 4 macro439 #define MAX_CS 4 macro
260 u32 wl_val[MAX_CS][MAX_PUP_NUM][7];261 u32 rl_val[MAX_CS][MAX_PUP_NUM][7];
151 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_rx()233 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_dqs_centralization_tx()1335 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_load_dqs_patterns()
716 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_save_training()1028 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_get_min_max_read_sample_delay()
98 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_read_leveling_hw()
1560 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_load_pbs_patterns()
25 static u32 ui_xor_regs_base_backup[MAX_CS];26 static u32 ui_xor_regs_mask_backup[MAX_CS];33 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()36 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_init()91 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_finish()94 for (ui = 0; ui < MAX_CS; ui++) in mv_sys_xor_finish()
200 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_restore_and_set_final_windows()245 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_save_and_set_training_windows()523 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_get_cs_num_from_reg()593 for (cs = 0; cs < MAX_CS; cs++) { in ddr3_fast_path_dynamic_cs_size_config()
14 #define MAX_CS 4 macro437 #define MAX_CS 4 macro
23 #define MAX_CS 2 macro78 struct pasemi_mac_csring *cs[MAX_CS];
348 for (i = 0; i < MAX_CS; i++) in pasemi_mac_setup_csrings()
80 #define MAX_CS 4 macro87 struct tango_chip *chips[MAX_CS];597 if (cs >= MAX_CS) in chip_init()642 for (cs = 0; cs < MAX_CS; ++cs) { in tango_nand_remove()