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Searched refs:CLK_TOP_AUD_2_SEL (Results 1 – 5 of 5) sorted by relevance

/OK3568_Linux_fs/kernel/include/dt-bindings/clock/
H A Dmt8173-clk.h120 #define CLK_TOP_AUD_2_SEL 110 macro
H A Dmt2712-clk.h157 #define CLK_TOP_AUD_2_SEL 126 macro
/OK3568_Linux_fs/kernel/drivers/clk/mediatek/
H A Dclk-mt8173.c581 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel", aud_2_parents, 0x00b0, 0, 2, 7),
H A Dclk-mt2712.c799 MUX_GATE(CLK_TOP_AUD_2_SEL, "aud_2_sel",
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi817 <&topckgen CLK_TOP_AUD_2_SEL>;