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Searched refs:CGU_CLK_DIV (Results 1 – 8 of 8) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/clk/ingenic/
H A Djz4770-cgu.c152 "cclk", CGU_CLK_DIV,
160 "h0clk", CGU_CLK_DIV,
168 "h1clk", CGU_CLK_DIV | CGU_CLK_GATE,
177 "h2clk", CGU_CLK_DIV,
185 "c1clk", CGU_CLK_DIV | CGU_CLK_GATE,
194 "pclk", CGU_CLK_DIV,
205 "mmc0_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
212 "mmc1_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
219 "mmc2_mux", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
226 "cim", CGU_CLK_DIV | CGU_CLK_GATE | CGU_CLK_MUX,
[all …]
H A Djz4740-cgu.c95 "pll half", CGU_CLK_DIV,
104 "cclk", CGU_CLK_DIV,
113 "hclk", CGU_CLK_DIV,
122 "pclk", CGU_CLK_DIV,
131 "mclk", CGU_CLK_DIV,
140 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
150 "lcd_pclk", CGU_CLK_DIV,
156 "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
164 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
172 "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
H A Djz4725b-cgu.c80 "pll half", CGU_CLK_DIV,
89 "cclk", CGU_CLK_DIV,
98 "hclk", CGU_CLK_DIV,
107 "pclk", CGU_CLK_DIV,
116 "mclk", CGU_CLK_DIV,
125 "ipu", CGU_CLK_DIV | CGU_CLK_GATE,
135 "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
142 "i2s", CGU_CLK_MUX | CGU_CLK_DIV,
149 "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
157 "mmc_mux", CGU_CLK_DIV,
[all …]
H A Djz4780-cgu.c343 "cpu", CGU_CLK_DIV,
349 "l2cache", CGU_CLK_DIV,
355 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
370 "ahb2", CGU_CLK_DIV,
376 "pclk", CGU_CLK_DIV,
382 "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
389 "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
398 "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
411 "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
419 "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
[all …]
H A Dx1000-cgu.c253 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
260 "l2cache", CGU_CLK_DIV,
266 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
279 "ahb2", CGU_CLK_DIV,
285 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
292 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
300 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
308 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
322 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
329 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
H A Dx1830-cgu.c227 "cpu", CGU_CLK_DIV | CGU_CLK_GATE,
234 "l2cache", CGU_CLK_DIV,
240 "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
253 "ahb2", CGU_CLK_DIV,
259 "pclk", CGU_CLK_DIV | CGU_CLK_GATE,
266 "ddr", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
274 "mac", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
283 "lcd", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
299 "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
306 "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
[all …]
H A Dcgu.c373 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_recalc_rate()
450 if (clk_info->type & CGU_CLK_DIV) in ingenic_clk_round_rate()
482 if (clk_info->type & CGU_CLK_DIV) { in ingenic_clk_set_rate()
640 if (caps & CGU_CLK_DIV) { in ingenic_register_clock()
641 caps &= ~CGU_CLK_DIV; in ingenic_register_clock()
H A Dcgu.h155 CGU_CLK_DIV = BIT(5), enumerator