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/rk3399_rockchip-uboot/common/
H A Dcli.c127 int i; in do_run() local
132 for (i = 1; i < argc; ++i) { in do_run()
135 arg = env_get(argv[i]); in do_run()
137 printf("## Error: \"%s\" not defined\n", argv[i]); in do_run()
H A Dupdate.c104 int i, bank, cnt; in update_flash_protect() local
139 for (i = 0; i < info->sector_count; i++) { in update_flash_protect()
142 s = info->start[i]; in update_flash_protect()
144 sp_info_ptr[i] = info->protect[i]; in update_flash_protect()
149 if (sp_info_ptr[i] == 1) { in update_flash_protect()
151 if (flash_real_protect(info, i, prot)) in update_flash_protect()
154 info->protect[i] = prot; in update_flash_protect()
/rk3399_rockchip-uboot/drivers/core/
H A Ddump.c15 int i, is_last; in show_devices() local
23 for (i = depth; i >= 0; i--) { in show_devices()
24 is_last = (last_flag >> i) & 1; in show_devices()
25 if (i) { in show_devices()
/rk3399_rockchip-uboot/drivers/ata/
H A Dlibata.c140 unsigned int i; in ata_swap_buf_le16() local
142 for (i = 0; i < buf_words; i++) in ata_swap_buf_le16()
143 buf[i] = le16_to_cpu(buf[i]); in ata_swap_buf_le16()
H A Dsata_ceva.c79 int i; in ceva_init_sata() local
94 for (i = 0; i < NR_PORTS; i++) { in ceva_init_sata()
96 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | (PCFG_PAD_VAL + i); in ceva_init_sata()
109 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); in ceva_init_sata()
/rk3399_rockchip-uboot/drivers/crypto/fsl/
H A Dsec.c133 int i; in caam_get_era() local
138 for (i = 0; i < ARRAY_SIZE(caam_eras); i++) in caam_get_era()
139 if (caam_eras[i].ip_id == ip_id && in caam_get_era()
140 caam_eras[i].maj_rev == maj_rev) in caam_get_era()
141 return caam_eras[i].era; in caam_get_era()
/rk3399_rockchip-uboot/post/lib_powerpc/
H A Dthreex.c117 unsigned int i, reg; in cpu_post_test_threex() local
120 for (i = 0; i < cpu_post_threex_size && ret == 0; i++) in cpu_post_test_threex()
122 struct cpu_post_threex_s *test = cpu_post_threex_table + i; in cpu_post_test_threex()
184 post_log ("Error at threex test %d !\n", i); in cpu_post_test_threex()
197 post_log ("Error at threex test %d !\n", i); in cpu_post_test_threex()
H A Drlwnm.c52 unsigned int i, reg; in cpu_post_test_rlwnm() local
55 for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++) in cpu_post_test_rlwnm()
57 struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i; in cpu_post_test_rlwnm()
120 post_log ("Error at rlwnm test %d !\n", i); in cpu_post_test_rlwnm()
133 post_log ("Error at rlwnm test %d !\n", i); in cpu_post_test_rlwnm()
H A Drlwimi.c54 unsigned int i, reg; in cpu_post_test_rlwimi() local
57 for (i = 0; i < cpu_post_rlwimi_size && ret == 0; i++) in cpu_post_test_rlwimi()
59 struct cpu_post_rlwimi_s *test = cpu_post_rlwimi_table + i; in cpu_post_test_rlwimi()
117 post_log ("Error at rlwimi test %d !\n", i); in cpu_post_test_rlwimi()
130 post_log ("Error at rlwimi test %d !\n", i); in cpu_post_test_rlwimi()
/rk3399_rockchip-uboot/board/imgtec/malta/
H A Dmalta.c38 int i; in malta_lcd_puts() local
42 for (i = 0; i < min((int)strlen(str), 8); i++) { in malta_lcd_puts()
43 __raw_writel(str[i], reg); in malta_lcd_puts()
48 for (; i < 8; i++) { in malta_lcd_puts()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc83xx/
H A Dcpu.c37 int i; in checkcpu() local
94 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++) in checkcpu()
95 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) { in checkcpu()
97 puts(cpu_type_list[i].name); in checkcpu()
109 if (i == ARRAY_SIZE(cpu_type_list)) in checkcpu()
/rk3399_rockchip-uboot/drivers/i2c/
H A Dfsl_i2c.c183 unsigned int i; in set_i2c_bus_speed() local
185 for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) in set_i2c_bus_speed()
186 if (fsl_i2c_speed_map[i].divider >= divider) { in set_i2c_bus_speed()
189 fdr = fsl_i2c_speed_map[i].fdr; in set_i2c_bus_speed()
190 speed = i2c_clk / fsl_i2c_speed_map[i].divider; in set_i2c_bus_speed()
359 int i; in __i2c_write_data() local
361 for (i = 0; i < length; i++) { in __i2c_write_data()
362 writeb(data[i], &base->dr); in __i2c_write_data()
368 return i; in __i2c_write_data()
374 int i; in __i2c_read_data() local
[all …]
/rk3399_rockchip-uboot/drivers/video/drm/
H A Dinno_video_phy.c108 int i; in phy_multi_write() local
110 for (i = 0; i < num_regs; i++) { in phy_multi_write()
111 phy_write(inno, regs[i].reg, regs[i].def); in phy_multi_write()
113 if (regs[i].delay_us) in phy_multi_write()
114 udelay(regs[i].delay_us); in phy_multi_write()
H A Dinno_hdmi.c286 ssize_t rc, i; in inno_hdmi_upload_frame() local
293 for (i = 0; i < rc; i++) in inno_hdmi_upload_frame()
294 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i, in inno_hdmi_upload_frame()
295 packed_frame[i]); in inno_hdmi_upload_frame()
348 int i; in inno_hdmi_config_video_csc() local
404 for (i = 0; i < 24; i++) in inno_hdmi_config_video_csc()
405 hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i, in inno_hdmi_config_video_csc()
406 coeff_csc[csc_mode][i]); in inno_hdmi_config_video_csc()
530 int interrupt = 0, i = 20; in inno_hdmi_i2c_read() local
532 while (i--) { in inno_hdmi_i2c_read()
[all …]
/rk3399_rockchip-uboot/drivers/spi/
H A Domap3_spi.c141 int i, chconf; in omap3_spi_write() local
154 for (i = 0; i < len; i++) { in omap3_spi_write()
168 writel(((u32 *)txp)[i], tx); in omap3_spi_write()
170 writel(((u16 *)txp)[i], tx); in omap3_spi_write()
172 writel(((u8 *)txp)[i], tx); in omap3_spi_write()
195 int i, chconf; in omap3_spi_read() local
211 for (i = 0; i < len; i++) { in omap3_spi_read()
224 if (i == (len - 1)) in omap3_spi_read()
230 ((u32 *)rxp)[i] = readl(rx); in omap3_spi_read()
232 ((u16 *)rxp)[i] = (u16)readl(rx); in omap3_spi_read()
[all …]
/rk3399_rockchip-uboot/drivers/power/regulator/
H A Drk801_regulator.c180 int i; in linear_range_get_value_array() local
182 for (i = 0; i < ranges; i++) { in linear_range_get_value_array()
183 if (r[i].min_sel <= selector && r[i].max_sel >= selector) in linear_range_get_value_array()
184 return linear_range_get_value(&r[i], selector, uV); in linear_range_get_value_array()
227 uint voltage, i; in regulator_map_voltage_linear_range() local
232 for (i = 0; i < desc->n_linear_ranges; i++) { in regulator_map_voltage_linear_range()
233 range = &desc->linear_ranges[i]; in regulator_map_voltage_linear_range()
254 if (i == desc->n_linear_ranges) in regulator_map_voltage_linear_range()
263 int i, id; in rk801_get_desc() local
300 for (i = 0; i < ARRAY_SIZE(rk801_desc); i++) { in rk801_get_desc()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-exynos/
H A Dspl_boot.c66 void *dinp, void const *doutp, int i) in spi_rx_tx() argument
68 uint *rxp = (uint *)(dinp + (i * (32 * 1024))); in spi_rx_tx()
110 int i, timeout = 100; in exynos_spi_copy() local
153 for (upto = 0, i = 0; upto < uboot_size; upto += todo, i++) { in exynos_spi_copy()
156 (void *)(SPI_FLASH_UBOOT_POS), i); in exynos_spi_copy()
264 size_t i; in memzero() local
266 for (i = 0; i < n; i++) in memzero()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A Drk_meta.c34 uint32_t i = 1; in rk_meta_get_startup_part_info() local
56 for (i = 1; i < total_part_num; i++) { in rk_meta_get_startup_part_info()
57 if (info->read(info, sector + i * (*per_part_size / info->bl_len), in rk_meta_get_startup_part_info()
64 debug("Not read meta tag from meta part[%d], read from part[%d] by default.\n", i, i - 1); in rk_meta_get_startup_part_info()
68 debug("Check part[%d]:part_flag=%d part[%d]:part_flag=%d\n", i - 1, meta_p->part_flag, in rk_meta_get_startup_part_info()
69 i, meta_next.part_flag); in rk_meta_get_startup_part_info()
81 return i; in rk_meta_get_startup_part_info()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h2003 #define CCM_GPR(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i)) argument
2004 #define CCM_OBSERVE(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i)) argument
2005 #define CCM_SCTRL(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i)) argument
2006 #define CCM_CCGR(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i)) argument
2007 #define CCM_ROOT_TARGET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i)) argument
2009 #define CCM_GPR_SET(i) (CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4) argument
2010 #define CCM_OBSERVE_SET(i) (CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4) argument
2011 #define CCM_SCTRL_SET(i) (CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4) argument
2012 #define CCM_CCGR_SET(i) (CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4) argument
2013 #define CCM_ROOT_TARGET_SET(i) (CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4) argument
[all …]
/rk3399_rockchip-uboot/cmd/
H A Dmii.c137 ulong i; in MII_dump_0_to_5() local
139 for (i = 0; i < 6; i++) { in MII_dump_0_to_5()
140 if ((reglo <= i) && (i <= reghi)) in MII_dump_0_to_5()
141 dump_reg(regvals[i], &reg_0_5_desc_tbl[i], in MII_dump_0_to_5()
142 &desc_and_len_tbl[i]); in MII_dump_0_to_5()
151 ulong i; in dump_reg() local
158 for (i = 0; i < pdl->len; i++) { in dump_reg()
159 pdesc = &pdl->pdesc[i]; in dump_reg()
/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dclock.c44 int i; in wait_for_completion() local
45 for (i = 0; i < 100; i++) { in wait_for_completion()
93 u32 tmp, pllod, i, alnctl_val = 0; in configure_main_pll() local
129 for (i = 0; i < PLLDIV_MAX; i++) { in configure_main_pll()
130 if (i < 3) in configure_main_pll()
131 offset = pllctl_reg(data->pll, div1) + i; in configure_main_pll()
133 offset = pllctl_reg(data->pll, div4) + (i - 3); in configure_main_pll()
135 if (divn_val[i] != -1) { in configure_main_pll()
136 __raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset); in configure_main_pll()
137 alnctl_val |= BIT(i); in configure_main_pll()
/rk3399_rockchip-uboot/arch/mips/mach-au1x00/
H A Dau1x00_usb_ohci.c109 static u32 roothub_portstatus (struct ohci *hc, int i) in roothub_portstatus() argument
110 { return read_roothub (hc, portstatus [i], 0xffe0fce0); } in roothub_portstatus()
127 int i; in urb_free_priv() local
133 for (i = 0; i <= last; i++) { in urb_free_priv()
134 td = urb->td[i]; in urb_free_priv()
137 urb->td[i] = NULL; in urb_free_priv()
168 int i, len; in pkt_print() local
172 for (i = 0; i < 8 ; i++) in pkt_print()
173 printf (" %02x", ((__u8 *) setup) [i]); in pkt_print()
182 for (i = 0; i < 16 && i < len; i++) in pkt_print()
[all …]
/rk3399_rockchip-uboot/drivers/net/
H A Dcpsw.c324 int i; in cpsw_ale_get_addr() local
326 for (i = 0; i < 6; i++) in cpsw_ale_get_addr()
327 addr[i] = cpsw_ale_get_field(ale_entry, 40 - 8*i, 8); in cpsw_ale_get_addr()
332 int i; in cpsw_ale_set_addr() local
334 for (i = 0; i < 6; i++) in cpsw_ale_set_addr()
335 cpsw_ale_set_field(ale_entry, 40 - 8*i, 8, addr[i]); in cpsw_ale_set_addr()
340 int i; in cpsw_ale_read() local
344 for (i = 0; i < ALE_ENTRY_WORDS; i++) in cpsw_ale_read()
345 ale_entry[i] = __raw_readl(priv->ale_regs + ALE_TABLE + 4 * i); in cpsw_ale_read()
352 int i; in cpsw_ale_write() local
[all …]
/rk3399_rockchip-uboot/drivers/mtd/onenand/
H A Dsamsung.c278 int i, mcount, scount; in s3c_onenand_command() local
315 for (i = 0; i < mcount; i++) in s3c_onenand_command()
322 for (i = 0; i < mcount; i++) in s3c_onenand_command()
326 for (i = 0; i < scount; i++) in s3c_onenand_command()
334 for (i = 0; i < mcount; i++) in s3c_onenand_command()
342 for (i = 0; i < mcount; i++) in s3c_onenand_command()
346 for (i = 0; i < scount; i++) in s3c_onenand_command()
/rk3399_rockchip-uboot/board/phytec/pfla02/
H A Dpfla02.c213 int i; in board_mmc_init() local
215 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { in board_mmc_init()
216 switch (i) { in board_mmc_init()
229 i + 1, CONFIG_SYS_FSL_USDHC_NUM); in board_mmc_init()
233 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); in board_mmc_init()
314 int i; in get_board_rev() local
316 for (i = 0, rev = 0; i < 4; i++) in get_board_rev()
317 rev |= (gpio_get_value(IMX_GPIO_NR(2, 12 + i)) << i); in get_board_rev()
605 int i; in pfla02_detect_chiptype() local
607 for (i = 0; i < 2; i++) { in pfla02_detect_chiptype()
[all …]

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