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/rk3399_rockchip-uboot/board/renesas/blanche/
H A Dblanche.c112 volatile u32 i = 0x10000 * cnt; \
113 while (i > 0) \
114 i--; \
H A Dqos.c64 int i; in qos_init() local
128 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init()
129 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; in qos_init()
143 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init()
144 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; in qos_init()
/rk3399_rockchip-uboot/arch/powerpc/cpu/mpc85xx/
H A Dt4240_serdes.c496 int i; in is_serdes_prtcl_valid() local
512 for (i = 0; i < SRDS_MAX_LANES; i++) { in is_serdes_prtcl_valid()
513 if (ptr->lanes[i] != NONE) in is_serdes_prtcl_valid()
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3562.c1177 u32 i, div, sel, best_div = 0, best_sel = 0; in rk3562_vop_set_rate() local
1213 for (i = 0; i <= DCLK_VOP_SEL_APLL; i++) { in rk3562_vop_set_rate()
1214 switch (i) { in rk3562_vop_set_rate()
1236 best_sel = i; in rk3562_vop_set_rate()
1739 int i, ret; in soc_clk_dump() local
1756 for (i = 0; i < clk_count; i++) { in soc_clk_dump()
1757 clk_dump = &clks_dump[i]; in soc_clk_dump()
1766 if (i == 0) { in soc_clk_dump()
H A Dclk_rv1103b.c1111 int i, ret; in soc_clk_dump() local
1134 for (i = 0; i < clk_count; i++) { in soc_clk_dump()
1135 clk_dump = &clks_dump[i]; in soc_clk_dump()
1145 if (i == 0) { in soc_clk_dump()
H A Dclk_rk322x.c1106 int i, ret; in soc_clk_dump() local
1123 for (i = 0; i < clk_count; i++) { in soc_clk_dump()
1124 clk_dump = &clks_dump[i]; in soc_clk_dump()
1134 if (i == 0) { in soc_clk_dump()
H A Dclk_rv1126.c1224 u32 i, div, best_div = 0, best_sel = 0; in rv1126_dclk_vop_set_clk() local
1226 for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) { in rv1126_dclk_vop_set_clk()
1227 switch (i) { in rv1126_dclk_vop_set_clk()
1246 best_sel = i; in rv1126_dclk_vop_set_clk()
2275 int i, ret; in soc_clk_dump() local
2300 for (i = 0; i < clk_count; i++) { in soc_clk_dump()
2301 clk_dump = &clks_dump[i]; in soc_clk_dump()
2313 if (i == 0) { in soc_clk_dump()
/rk3399_rockchip-uboot/drivers/usb/gadget/
H A Dether.c1952 int i; in is_eth_addr_valid() local
1960 for (i = 0; i < 6; i++) { in is_eth_addr_valid()
1961 char term = (i == 5 ? '\0' : ':'); in is_eth_addr_valid()
1963 ea[i] = simple_strtol(p, &q, 16); in is_eth_addr_valid()
1990 unsigned i; in get_ether_addr() local
1992 for (i = 0; i < 6; i++) { in get_ether_addr()
1999 dev_addr[i] = num; in get_ether_addr()
/rk3399_rockchip-uboot/scripts/
H A Dfit-sign.sh404 for ((i = 0; i < ${ITB_MAX_NUM}; i++));
H A Dmkbootimg204 choices=[2**i for i in range(11,15)], default=2048)
/rk3399_rockchip-uboot/scripts/dtc/
H A Ddtc-lexer.lex.c_shipped204 /* Whether we "own" the buffer - i.e., we know we created it,
1399 int number_to_move, i;
1430 for ( i = 0; i < number_to_move; ++i )
1989 int i;
1997 for ( i = 0; i < _yybytes_len; ++i )
1998 buf[i] = yybytes[i];
2179 int i;
2180 for ( i = 0; i < n; ++i )
2181 s1[i] = s2[i];
/rk3399_rockchip-uboot/board/gateworks/gw_ventana/
H A DREADME15 The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading
20 - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
57 The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
62 addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two
77 (IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM
105 More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
155 More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dnonsec_virt.S124 add \addr, \addr, #GIC_DIST_OFFSET @ GIC dist i/f offset
143 cpsid i
/rk3399_rockchip-uboot/drivers/usb/musb-new/
H A Dmusb_regs.h453 static inline void __iomem *musb_read_target_reg_base(u8 i, void __iomem *mbase) in musb_read_target_reg_base() argument
455 return (MUSB_BUSCTL_OFFSET(i, 0) + mbase); in musb_read_target_reg_base()
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx6/
H A Dclock.c626 u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1; in mxs_set_lcdclk() local
678 for (i = 1; i <= max_pred; i++) { in mxs_set_lcdclk()
680 temp = freq * i * j; in mxs_set_lcdclk()
685 pred = i; in mxs_set_lcdclk()
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rv1108_pctl_phy.c35 int i; in copy_to_reg() local
37 for (i = 0; i < n / sizeof(u32); i++) { in copy_to_reg()
/rk3399_rockchip-uboot/board/renesas/gose/
H A Dqos.c84 int i; in qos_init() local
176 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init()
177 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; in qos_init()
191 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init()
192 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; in qos_init()
/rk3399_rockchip-uboot/board/freescale/ls2080ardb/
H A DREADME71 During boot i.e. IFC Region #1:-
75 After relocate to DDR i.e. IFC Region #2:-
/rk3399_rockchip-uboot/drivers/net/phy/
H A Dmarvell.c138 int i = 0; in m88e1xxx_parse_status() local
143 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { in m88e1xxx_parse_status()
149 if ((i++ % 1000) == 0) in m88e1xxx_parse_status()
/rk3399_rockchip-uboot/board/renesas/stout/
H A Dqos.c68 int i; in qos_init_es1() local
134 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init_es1()
135 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; in qos_init_es1()
149 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init_es1()
150 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; in qos_init_es1()
1159 int i; in qos_init_es2() local
1252 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init_es2()
1253 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; in qos_init_es2()
1267 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init_es2()
1268 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; in qos_init_es2()
/rk3399_rockchip-uboot/board/renesas/lager/
H A Dqos.c66 int i; in qos_init_es1() local
132 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init_es1()
133 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; in qos_init_es1()
147 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init_es1()
148 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; in qos_init_es1()
1157 int i; in qos_init_es2() local
1250 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init_es2()
1251 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; in qos_init_es2()
1265 for (i = DBSC3_00; i < DBSC3_NR; i++) { in qos_init_es2()
1266 qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; in qos_init_es2()
/rk3399_rockchip-uboot/drivers/ata/
H A Dsata_sil3114.c427 int i; in msleep() local
429 for (i = 0; i < count; i++) in msleep()
H A Dsata_sil.c122 int i; in sil_read_fis() local
128 for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4) in sil_read_fis()
/rk3399_rockchip-uboot/include/jffs2/
H A Djffs2.h187 struct jffs2_raw_inode i; member
/rk3399_rockchip-uboot/doc/
H A DREADME.mpc85xx45 A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
91 B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot

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