| /rk3399_ARM-atf/plat/xilinx/common/pm_service/ |
| H A D | pm_ipi.c | 95 for (size_t i = 0; i < PAYLOAD_ARG_CNT; i++) { in pm_ipi_send_common() local
96 mmio_write_32(buffer_base + offset, payload[i]); in pm_ipi_send_common()
170 size_t i; in pm_ipi_buff_read() local
186 for (i = 0U; i < count; i++) { in pm_ipi_buff_read()
187 value[i] = mmio_read_32(buffer_base + ((i + 1U) * PAYLOAD_ARG_SIZE)); in pm_ipi_buff_read()
225 size_t i; in pm_ipi_buff_read_callb() local
235 for (i = 0; i < count; i++) { in pm_ipi_buff_read_callb()
236 value[i] = mmio_read_32(buffer_base + (i * PAYLOAD_ARG_SIZE)); in pm_ipi_buff_read_callb()
321 uint32_t i, j, c, bit, datain, crcmask, crchighbit; in calculate_crc() local
327 for (i = 0U; i < buffersize; i++) { in calculate_crc()
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/apusys/ |
| H A D | mtk_apusys_apc.c | 143 uint32_t d, i; in dump_apusys_noc_dapc() local
148 for (i = 0U; i <= reg_num; i++) { in dump_apusys_noc_dapc()
149 INFO("[NOCDAPC] D%d_APC_%d: 0x%x\n", d, i, in dump_apusys_noc_dapc()
151 (d * 0x40) + (i * 4))); in dump_apusys_noc_dapc()
431 uint32_t d, i; in dump_apusys_ao_apc() local
436 for (i = 0U; i <= reg_num; i++) { in dump_apusys_ao_apc()
437 INFO("[APUAPC] D%d_APC_%d: 0x%x\n", d, i, in dump_apusys_ao_apc()
439 (d * 0x40) + (i * 4))); in dump_apusys_ao_apc()
448 uint32_t i; in set_apusys_noc_dapc() local
451 for (i = 0U; i < ARRAY_SIZE(APUSYS_NOC_DAPC_AO); i++) { in set_apusys_noc_dapc()
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| /rk3399_ARM-atf/tools/cert_create/src/ |
| H A D | cert.c | 110 int i, num, rc = 0; in cert_new() local
203 for (i = 0; i < num; i++) { in cert_new()
204 ex = sk_X509_EXTENSION_value(sk, i); in cert_new()
227 unsigned int i; in cert_init() local
251 for (i = 0; i < num_certs; i++) { in cert_init()
252 cert = &certs[i]; in cert_init()
267 unsigned int i; in cert_get_by_opt() local
269 for (i = 0; i < num_certs; i++) { in cert_get_by_opt()
270 cert = &certs[i]; in cert_get_by_opt()
281 unsigned int i; in cert_cleanup() local
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| /rk3399_ARM-atf/tools/encrypt_fw/src/ |
| H A D | main.c | 39 int rem, i = 0; in print_help() local
68 printf("\t%-32s %s\n", line, cmd_opt_get_help_msg(i)); in print_help()
70 i++; in print_help()
77 int i; in get_key_alg() local
79 for (i = 0 ; i < NUM_ELEM(key_algs_str) ; i++) { in get_key_alg()
80 if (strcmp(key_alg_str, key_algs_str[i]) == 0) { in get_key_alg()
81 return i; in get_key_alg()
137 int i, key_alg, ret; in main() local
152 for (i = 0; i < NUM_ELEM(common_cmd_opt); i++) { in main()
153 cmd_opt_add(&common_cmd_opt[i]); in main()
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| /rk3399_ARM-atf/drivers/qti/qtimer/ |
| H A D | qtimer.c | 23 uint8_t i; in qti_qtimer_init() local
27 for (i = 0; i < QTIMER_NBR_FRAMES; i++) { in qti_qtimer_init()
28 mmio_write_32(QTI_QTIMER_BASE + ACR_FG0_OFFSET(i), 0x3F); in qti_qtimer_init()
29 mmio_write_32(QTI_QTIMER_BASE + VOFF_FG0_LO_OFFSET(i), 0x0); in qti_qtimer_init()
30 mmio_write_32(QTI_QTIMER_BASE + VOFF_FG0_HI_OFFSET(i), 0x0); in qti_qtimer_init()
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| /rk3399_ARM-atf/drivers/arm/gic/v3/ |
| H A D | gic600ae_fmu.c | 269 for (unsigned int i = 0U; i < num_blk; i++) { in gic600_fmu_init() local
275 if ((blk_present_mask & BIT(i)) == 0U) { in gic600_fmu_init()
276 gic_fmu_disable_all_sm_blkid(base, i); in gic600_fmu_init()
281 errctlr = gic_fmu_read_errctlr(base, i); in gic600_fmu_init()
292 gic_fmu_write_errctlr(base, i, errctlr); in gic600_fmu_init()
315 for (unsigned int i = FMU_BLK_PPI0; i < FMU_BLK_PPI31; i++) { in gic600_fmu_init() local
316 if ((blk_present_mask & BIT(i)) != 0U) { in gic600_fmu_init()
318 (i << FMU_SMEN_BLK_SHIFT) | in gic600_fmu_init()
323 (i << FMU_SMEN_BLK_SHIFT) | in gic600_fmu_init()
329 for (unsigned int i = FMU_BLK_ITS0; i < FMU_BLK_ITS7; i++) { in gic600_fmu_init() local
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| /rk3399_ARM-atf/plat/mediatek/drivers/cirq/ |
| H A D | mt_cirq.c | 173 unsigned int i; in collect_all_wakeup_events() local
188 for (i = 0U; i < cirq_all_events.num_of_events; i++) { in collect_all_wakeup_events()
189 if (cirq_all_events.wakeup_events[i] > 0U) { in collect_all_wakeup_events()
190 gic_irq = cirq_all_events.wakeup_events[i]; in collect_all_wakeup_events()
205 cirq_all_events.wakeup_events[i]) in collect_all_wakeup_events()
217 if (mt_irq_get_sens(cirq_all_events.wakeup_events[i]) in collect_all_wakeup_events()
314 unsigned int i; in __cirq_fast_clone() local
316 for (i = 0U; i < CIRQ_REG_NUM ; ++i) { in __cirq_fast_clone()
319 reg = &cirq_all_events.table[i]; in __cirq_fast_clone()
411 static int mt_cirq_get_mask_vec(unsigned int i) in mt_cirq_get_mask_vec() argument
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| /rk3399_ARM-atf/plat/imx/imx8m/imx8mq/ |
| H A D | gpc.c | 171 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) { in imx_gpc_core_wake() local
172 if (cpumask & (1 << i)) { in imx_gpc_core_wake()
173 imx_gpc_mask_irq0(i, false); in imx_gpc_core_wake()
204 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) { in imx_gpc_set_affinity() local
205 if (cpu_idx != i) { in imx_gpc_set_affinity()
206 gpc_imr_core_spin_lock(i); in imx_gpc_set_affinity()
207 reg = gpc_imr_offset[i] + (hwirq / 32) * 4; in imx_gpc_set_affinity()
211 gpc_imr_core_spin_unlock(i); in imx_gpc_set_affinity()
342 unsigned int i; in imx_anamix_override() local
345 for (i = 0; i < MAX_PLL_NUM; i++) { in imx_anamix_override()
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| /rk3399_ARM-atf/plat/xilinx/versal_net/ |
| H A D | plat_psci_pm.c | 75 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_off() local
77 __func__, i, target_state->pwr_domain_state[i]); in versal_net_pwr_domain_off()
221 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_suspend() local
223 __func__, i, target_state->pwr_domain_state[i]); in versal_net_pwr_domain_suspend()
263 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_suspend_finish() local
265 __func__, i, target_state->pwr_domain_state[i]); in versal_net_pwr_domain_suspend_finish()
341 uint64_t i; in versal_net_get_sys_suspend_power_state() local
343 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_get_sys_suspend_power_state()
344 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in versal_net_get_sys_suspend_power_state()
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| /rk3399_ARM-atf/plat/imx/imx8m/ |
| H A D | imx8m_ccm.c | 35 unsigned int i; in imx8m_uart_get_base() local
37 for (i = 0; i < ARRAY_SIZE(imx8m_uart_info); i++) { in imx8m_uart_get_base()
44 val = mmio_read_32(IMX_CCM_BASE + imx8m_uart_info[i].ccm_reg); in imx8m_uart_get_base()
46 val = mmio_read_32(imx8m_uart_info[i].uart_base + UCR1); in imx8m_uart_get_base()
48 return imx8m_uart_info[i].uart_base; in imx8m_uart_get_base()
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| /rk3399_ARM-atf/drivers/fwu/ |
| H A D | fwu.c | 198 uint32_t i; in fwu_get_alternate_boot_bank() local
207 for (i = 0U; i < NR_OF_FW_BANKS; i++) { in fwu_get_alternate_boot_bank()
208 if (i == metadata.active_index || in fwu_get_alternate_boot_bank()
209 i == metadata.previous_active_index) { in fwu_get_alternate_boot_bank()
213 if (metadata.bank_state[i] == FWU_BANK_STATE_ACCEPTED) { in fwu_get_alternate_boot_bank()
214 return i; in fwu_get_alternate_boot_bank()
227 for (i = 0U; i < NR_OF_FW_BANKS; i++) { in fwu_get_alternate_boot_bank()
228 if (i == metadata.active_index || in fwu_get_alternate_boot_bank()
229 i == metadata.previous_active_index) { in fwu_get_alternate_boot_bank()
233 if (metadata.bank_state[i] == FWU_BANK_STATE_VALID) { in fwu_get_alternate_boot_bank()
[all …]
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| /rk3399_ARM-atf/plat/imx/common/ |
| H A D | plat_imx8_gic.c | 132 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) in plat_gic_save() local
133 gicv3_rdistif_save(i, &ctx->rdist_ctx[i]); in plat_gic_save()
141 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) in plat_gic_restore() local
142 gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]); in plat_gic_restore()
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| H A D | imx_caam.c | 17 int i; in imx_caam_init() local
19 for (i = 0; i < CAAM_NUM_JOB_RINGS; i++) { in imx_caam_init()
20 reg = mmio_read_32((uintptr_t)&caam->jr[i].jrmidr_ms); in imx_caam_init()
22 mmio_write_32((uintptr_t)&caam->jr[i].jrmidr_ms, reg); in imx_caam_init()
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| /rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/ |
| H A D | ddrphy_phyinit_loadpieprodcode.c | 183 int i; in ddrphy_phyinit_loadpieprodcode() local
185 for (i = 0; i < PRODCODE_SIZE; i++) { in ddrphy_phyinit_loadpieprodcode()
186 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * prodcode_addr[i])), in ddrphy_phyinit_loadpieprodcode()
187 prodcode_data[i]); in ddrphy_phyinit_loadpieprodcode()
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| /rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/ras/ |
| H A D | nrd_ras_common.c | 26 int i; in nrd_find_ras_event_map_by_intr() local
36 for (i = 0; i < size; i++) { in nrd_find_ras_event_map_by_intr()
74 int i; in nrd_ras_platform_setup() local
91 for (i = 0; i < size; i++) { in nrd_ras_platform_setup()
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| /rk3399_ARM-atf/plat/mediatek/drivers/pmic/mt8196/ |
| H A D | pmic_shutdown_cfg.c | 163 int i, ret; in mt6316_key_lock_check() local
168 for (i = 0; i < 2; i++) { in mt6316_key_lock_check()
173 i = 0; in mt6316_key_lock_check()
184 i = 0; in mt6316_key_lock_check()
231 uint8_t i, slvid; in pmic_shutdown_cfg_init() local
233 for (i = 0; i < ARRAY_SIZE(cfg_arr); i++) { in pmic_shutdown_cfg_init()
234 slvid = cfg_arr[i].slvid; in pmic_shutdown_cfg_init()
248 uint8_t i, slvid; in pmic_shutdown_cfg() local
252 for (i = 0; i < ARRAY_SIZE(cfg_arr); i++) { in pmic_shutdown_cfg()
253 slvid = cfg_arr[i].slvid; in pmic_shutdown_cfg()
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| /rk3399_ARM-atf/plat/arm/common/ |
| H A D | arm_ni.c | 30 #define NI_CHILD_POINTER(i) (NI_CHILD_POINTERS_START + (i * 4)) argument
31 #define NI_COMP_SUBFEATURE_TYPE(i) (NI_COMP_SUBFEATURE_TYPE_START + (i * 8)) argument
32 #define NI_COMP_SUBFEATURE_SECURE_CTRL(i) (NI_COMP_SUBFEATURE_SECURE_CTRL_START + (i * 8)) argument
80 for (uint32_t i = 0U; i < subfeature_count; i++) { in ni_enable_fcu_ns_access() local
82 NI_NODE_TYPE(mmio_read_32(comp_addr + NI_COMP_SUBFEATURE_TYPE(i))); in ni_enable_fcu_ns_access()
84 subfeature_secure_ctrl = comp_addr + NI_COMP_SUBFEATURE_SECURE_CTRL(i); in ni_enable_fcu_ns_access()
145 for (uint32_t i = 0U; i < vd_count; i++) { in plat_arm_ni_setup() local
146 vd_addr = global_cfg + mmio_read_32(global_cfg + NI_CHILD_POINTER(i)); in plat_arm_ni_setup()
149 i, vd_addr, mmio_read_32(vd_addr)); in plat_arm_ni_setup()
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| /rk3399_ARM-atf/plat/arm/board/juno/ |
| H A D | juno_trusted_boot.c | 29 unsigned int words, i; in juno_get_rotpk_info_regs() local
68 for (i = 0 ; i < words ; i++) { in juno_get_rotpk_info_regs()
69 tmp = src[words - 1 - i]; in juno_get_rotpk_info_regs()
79 for (i = 0 ; i < words ; i++) { in juno_get_rotpk_info_regs()
80 tmp = src[words - 1 - i]; in juno_get_rotpk_info_regs()
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| /rk3399_ARM-atf/drivers/st/crypto/ |
| H A D | stm32_saes.c | 248 uint8_t i; in saes_write_iv() local
251 for (i = 0U; i < AES_IVSIZE / sizeof(uint32_t); i++) { in saes_write_iv()
252 mmio_write_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t), ctx->iv[i]); in saes_write_iv()
262 uint8_t i; in saes_write_key() local
264 for (i = 0U; i < AES_KEYSIZE_128 / sizeof(uint32_t); i++) { in saes_write_key()
265 mmio_write_32(ctx->base + _SAES_KEYR0 + i * sizeof(uint32_t), ctx->key[i]); in saes_write_key()
269 for (i = 0U; i < (AES_KEYSIZE_256 / 2U) / sizeof(uint32_t); i++) { in saes_write_key()
270 mmio_write_32(ctx->base + _SAES_KEYR4 + i * sizeof(uint32_t), in saes_write_key()
271 ctx->key[i + 4U]); in saes_write_key()
331 uint8_t i; in save_context() local
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| /rk3399_ARM-atf/drivers/arm/gic/v2/ |
| H A D | gicv2_helpers.c | 127 unsigned int i; in gicv2_secure_spis_configure_props() local
134 for (i = 0; i < interrupt_props_num; i++) { in gicv2_secure_spis_configure_props()
135 prop_desc = &interrupt_props[i]; in gicv2_secure_spis_configure_props()
168 unsigned int i; in gicv2_secure_ppi_sgi_setup_props() local
184 for (i = 0U; i < MIN_SPI_ID; i += 4U) { in gicv2_secure_ppi_sgi_setup_props()
185 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); in gicv2_secure_ppi_sgi_setup_props()
187 for (i = 0U; i < interrupt_props_num; i++) { in gicv2_secure_ppi_sgi_setup_props()
188 prop_desc = &interrupt_props[i]; in gicv2_secure_ppi_sgi_setup_props()
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| /rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_a/ |
| H A D | ddr_init_d3.c | 26 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1866() local
184 for (i = 0; i < 2; i++) { in init_ddr_d3_1866()
185 mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); in init_ddr_d3_1866()
187 mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); in init_ddr_d3_1866()
189 mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); in init_ddr_d3_1866()
193 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_d3_1866()
196 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_d3_1866()
198 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr_d3_1866()
200 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr_d3_1866()
203 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_d3_1866()
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| H A D | ddr_init_v3m.c | 17 uint32_t i, r2, r5, r6, r7, r12; in init_ddr_v3m_1600() local
193 for (i = 0; i < 4; i++) { in init_ddr_v3m_1600()
194 mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); in init_ddr_v3m_1600()
196 mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); in init_ddr_v3m_1600()
198 mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); in init_ddr_v3m_1600()
202 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_v3m_1600()
205 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_v3m_1600()
207 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr_v3m_1600()
209 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr_v3m_1600()
212 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_v3m_1600()
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/emi_mpu/ |
| H A D | emi_mpu.c | 57 int region, i; in dump_emi_mpu_regions() local
61 for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i) in dump_emi_mpu_regions()
62 apc[i] = mmio_read_32(EMI_MPU_APC(region, i)); in dump_emi_mpu_regions()
75 int i; in emi_mpu_set_protection() local
83 for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) { in emi_mpu_set_protection()
85 (i << 24); in emi_mpu_set_protection()
86 _emi_mpu_set_protection(start, end, region_info->apc[i]); in emi_mpu_set_protection()
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| /rk3399_ARM-atf/plat/st/stm32mp1/ |
| H A D | stm32mp1_fconf_firewall.c | 57 uint8_t i; in stm32mp1_security_setup() local
70 for (i = 1U; i <= nb_regions; i++) { in stm32mp1_security_setup()
71 tzc400_update_filters(i, STM32MP1_FILTER_BIT_ALL); in stm32mp1_security_setup()
81 unsigned int i; in fconf_populate_stm32mp1_firewall() local
101 for (i = 0U; i < (unsigned int)(len / (sizeof(uint32_t) * STM32MP_REGION_PARAMS)); i++) { in fconf_populate_stm32mp1_firewall()
102 uint32_t idx = i * STM32MP_REGION_PARAMS; in fconf_populate_stm32mp1_firewall()
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| /rk3399_ARM-atf/drivers/qti/accesscontrol/xpu/ |
| H A D | xpu3.c | 105 for (size_t i = 0; i < g_xpu_base_addr_array_count; i++) { in dump_log() local
106 if (g_xpu_base_addr_array[i].e_xpu != xpu) in dump_log()
109 xpu_addr = g_xpu_base_addr_array[i].base_addr + offset; in dump_log()
156 for (size_t i = 0; i < ACC_XPU_ERR_INT_REG_NUM; i++, p++) { in xpu_print_log() local
160 err_bitmask[i] = mmio_read_32(addr) & mask; in xpu_print_log()
179 for (size_t i = 0; row[i].bit_mask != 0; i++) { in xpu_print_log() local
182 if (i >= ACC_XPU_ERR_NUM_PER_REG) in xpu_print_log()
185 m = &row[i]; in xpu_print_log()
276 for (int i = 0; i < xpu->part_range_arr_size; i++, range++, owner++) { in set_mpu_permissions() local
280 if (i >= xpu->owner_arr_size) in set_mpu_permissions()
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