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/rk3399_ARM-atf/drivers/marvell/
H A Dtrng.c62 uint8_t i; in mv_trng_get_random32() local
82 for (i = 0U; i < CP110_TRNG_MAX_RETRIES; i++) { in mv_trng_get_random32()
90 if (i == CP110_TRNG_MAX_RETRIES) { in mv_trng_get_random32()
94 for (i = 0U; i < num; i++) { in mv_trng_get_random32()
95 rand[i] = mmio_read_32(CP110_TRNG_OUTPUT_REG(i)); in mv_trng_get_random32()
/rk3399_ARM-atf/plat/ti/common/
H A Dk3_gicv3.c97 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { in k3_gic_save_context() local
98 gicv3_rdistif_save(i, &rdist_ctx[i]); in k3_gic_save_context()
106 for (unsigned int i = 0U; i < PLATFORM_CORE_COUNT; i++) { in k3_gic_restore_context() local
107 gicv3_rdistif_init_restore(i, &rdist_ctx[i]); in k3_gic_restore_context()
/rk3399_ARM-atf/tools/cert_create/src/
H A Dcert.c110 int i, num, rc = 0; in cert_new() local
203 for (i = 0; i < num; i++) { in cert_new()
204 ex = sk_X509_EXTENSION_value(sk, i); in cert_new()
227 unsigned int i; in cert_init() local
251 for (i = 0; i < num_certs; i++) { in cert_init()
252 cert = &certs[i]; in cert_init()
267 unsigned int i; in cert_get_by_opt() local
269 for (i = 0; i < num_certs; i++) { in cert_get_by_opt()
270 cert = &certs[i]; in cert_get_by_opt()
281 unsigned int i; in cert_cleanup() local
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/rk3399_ARM-atf/plat/mediatek/drivers/cirq/
H A Dmt_cirq.c173 unsigned int i; in collect_all_wakeup_events() local
188 for (i = 0U; i < cirq_all_events.num_of_events; i++) { in collect_all_wakeup_events()
189 if (cirq_all_events.wakeup_events[i] > 0U) { in collect_all_wakeup_events()
190 gic_irq = cirq_all_events.wakeup_events[i]; in collect_all_wakeup_events()
205 cirq_all_events.wakeup_events[i]) in collect_all_wakeup_events()
217 if (mt_irq_get_sens(cirq_all_events.wakeup_events[i]) in collect_all_wakeup_events()
314 unsigned int i; in __cirq_fast_clone() local
316 for (i = 0U; i < CIRQ_REG_NUM ; ++i) { in __cirq_fast_clone()
319 reg = &cirq_all_events.table[i]; in __cirq_fast_clone()
411 static int mt_cirq_get_mask_vec(unsigned int i) in mt_cirq_get_mask_vec() argument
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/rk3399_ARM-atf/plat/imx/imx8m/imx8mq/
H A Dgpc.c171 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) { in imx_gpc_core_wake() local
172 if (cpumask & (1 << i)) { in imx_gpc_core_wake()
173 imx_gpc_mask_irq0(i, false); in imx_gpc_core_wake()
204 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) { in imx_gpc_set_affinity() local
205 if (cpu_idx != i) { in imx_gpc_set_affinity()
206 gpc_imr_core_spin_lock(i); in imx_gpc_set_affinity()
207 reg = gpc_imr_offset[i] + (hwirq / 32) * 4; in imx_gpc_set_affinity()
211 gpc_imr_core_spin_unlock(i); in imx_gpc_set_affinity()
342 unsigned int i; in imx_anamix_override() local
345 for (i = 0; i < MAX_PLL_NUM; i++) { in imx_anamix_override()
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/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgic600ae_fmu.c269 for (unsigned int i = 0U; i < num_blk; i++) { in gic600_fmu_init() local
275 if ((blk_present_mask & BIT(i)) == 0U) { in gic600_fmu_init()
276 gic_fmu_disable_all_sm_blkid(base, i); in gic600_fmu_init()
281 errctlr = gic_fmu_read_errctlr(base, i); in gic600_fmu_init()
292 gic_fmu_write_errctlr(base, i, errctlr); in gic600_fmu_init()
315 for (unsigned int i = FMU_BLK_PPI0; i < FMU_BLK_PPI31; i++) { in gic600_fmu_init() local
316 if ((blk_present_mask & BIT(i)) != 0U) { in gic600_fmu_init()
318 (i << FMU_SMEN_BLK_SHIFT) | in gic600_fmu_init()
323 (i << FMU_SMEN_BLK_SHIFT) | in gic600_fmu_init()
329 for (unsigned int i = FMU_BLK_ITS0; i < FMU_BLK_ITS7; i++) { in gic600_fmu_init() local
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/rk3399_ARM-atf/tools/encrypt_fw/src/
H A Dmain.c39 int rem, i = 0; in print_help() local
68 printf("\t%-32s %s\n", line, cmd_opt_get_help_msg(i)); in print_help()
70 i++; in print_help()
77 int i; in get_key_alg() local
79 for (i = 0 ; i < NUM_ELEM(key_algs_str) ; i++) { in get_key_alg()
80 if (strcmp(key_alg_str, key_algs_str[i]) == 0) { in get_key_alg()
81 return i; in get_key_alg()
137 int i, key_alg, ret; in main() local
152 for (i = 0; i < NUM_ELEM(common_cmd_opt); i++) { in main()
153 cmd_opt_add(&common_cmd_opt[i]); in main()
/rk3399_ARM-atf/plat/xilinx/versal_net/
H A Dplat_psci_pm.c75 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_off() local
77 __func__, i, target_state->pwr_domain_state[i]); in versal_net_pwr_domain_off()
221 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_suspend() local
223 __func__, i, target_state->pwr_domain_state[i]); in versal_net_pwr_domain_suspend()
263 for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_pwr_domain_suspend_finish() local
265 __func__, i, target_state->pwr_domain_state[i]); in versal_net_pwr_domain_suspend_finish()
341 uint64_t i; in versal_net_get_sys_suspend_power_state() local
343 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in versal_net_get_sys_suspend_power_state()
344 req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; in versal_net_get_sys_suspend_power_state()
/rk3399_ARM-atf/drivers/fwu/
H A Dfwu.c198 uint32_t i; in fwu_get_alternate_boot_bank() local
207 for (i = 0U; i < NR_OF_FW_BANKS; i++) { in fwu_get_alternate_boot_bank()
208 if (i == metadata.active_index || in fwu_get_alternate_boot_bank()
209 i == metadata.previous_active_index) { in fwu_get_alternate_boot_bank()
213 if (metadata.bank_state[i] == FWU_BANK_STATE_ACCEPTED) { in fwu_get_alternate_boot_bank()
214 return i; in fwu_get_alternate_boot_bank()
227 for (i = 0U; i < NR_OF_FW_BANKS; i++) { in fwu_get_alternate_boot_bank()
228 if (i == metadata.active_index || in fwu_get_alternate_boot_bank()
229 i == metadata.previous_active_index) { in fwu_get_alternate_boot_bank()
233 if (metadata.bank_state[i] == FWU_BANK_STATE_VALID) { in fwu_get_alternate_boot_bank()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/pmic/mt8196/
H A Dpmic_shutdown_cfg.c163 int i, ret; in mt6316_key_lock_check() local
168 for (i = 0; i < 2; i++) { in mt6316_key_lock_check()
173 i = 0; in mt6316_key_lock_check()
184 i = 0; in mt6316_key_lock_check()
231 uint8_t i, slvid; in pmic_shutdown_cfg_init() local
233 for (i = 0; i < ARRAY_SIZE(cfg_arr); i++) { in pmic_shutdown_cfg_init()
234 slvid = cfg_arr[i].slvid; in pmic_shutdown_cfg_init()
248 uint8_t i, slvid; in pmic_shutdown_cfg() local
252 for (i = 0; i < ARRAY_SIZE(cfg_arr); i++) { in pmic_shutdown_cfg()
253 slvid = cfg_arr[i].slvid; in pmic_shutdown_cfg()
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/rk3399_ARM-atf/plat/imx/common/
H A Dplat_imx8_gic.c132 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) in plat_gic_save() local
133 gicv3_rdistif_save(i, &ctx->rdist_ctx[i]); in plat_gic_save()
141 for (int i = 0; i < PLATFORM_CORE_COUNT; i++) in plat_gic_restore() local
142 gicv3_rdistif_init_restore(i, &ctx->rdist_ctx[i]); in plat_gic_restore()
H A Dimx_caam.c17 int i; in imx_caam_init() local
19 for (i = 0; i < CAAM_NUM_JOB_RINGS; i++) { in imx_caam_init()
20 reg = mmio_read_32((uintptr_t)&caam->jr[i].jrmidr_ms); in imx_caam_init()
22 mmio_write_32((uintptr_t)&caam->jr[i].jrmidr_ms, reg); in imx_caam_init()
/rk3399_ARM-atf/plat/imx/imx8m/
H A Dimx8m_ccm.c35 unsigned int i; in imx8m_uart_get_base() local
37 for (i = 0; i < ARRAY_SIZE(imx8m_uart_info); i++) { in imx8m_uart_get_base()
44 val = mmio_read_32(IMX_CCM_BASE + imx8m_uart_info[i].ccm_reg); in imx8m_uart_get_base()
46 val = mmio_read_32(imx8m_uart_info[i].uart_base + UCR1); in imx8m_uart_get_base()
48 return imx8m_uart_info[i].uart_base; in imx8m_uart_get_base()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_ni.c30 #define NI_CHILD_POINTER(i) (NI_CHILD_POINTERS_START + (i * 4)) argument
31 #define NI_COMP_SUBFEATURE_TYPE(i) (NI_COMP_SUBFEATURE_TYPE_START + (i * 8)) argument
32 #define NI_COMP_SUBFEATURE_SECURE_CTRL(i) (NI_COMP_SUBFEATURE_SECURE_CTRL_START + (i * 8)) argument
80 for (uint32_t i = 0U; i < subfeature_count; i++) { in ni_enable_fcu_ns_access() local
82 NI_NODE_TYPE(mmio_read_32(comp_addr + NI_COMP_SUBFEATURE_TYPE(i))); in ni_enable_fcu_ns_access()
84 subfeature_secure_ctrl = comp_addr + NI_COMP_SUBFEATURE_SECURE_CTRL(i); in ni_enable_fcu_ns_access()
145 for (uint32_t i = 0U; i < vd_count; i++) { in plat_arm_ni_setup() local
146 vd_addr = global_cfg + mmio_read_32(global_cfg + NI_CHILD_POINTER(i)); in plat_arm_ni_setup()
149 i, vd_addr, mmio_read_32(vd_addr)); in plat_arm_ni_setup()
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/common/ras/
H A Dnrd_ras_common.c26 int i; in nrd_find_ras_event_map_by_intr() local
36 for (i = 0; i < size; i++) { in nrd_find_ras_event_map_by_intr()
74 int i; in nrd_ras_platform_setup() local
91 for (i = 0; i < size; i++) { in nrd_ras_platform_setup()
/rk3399_ARM-atf/drivers/st/crypto/
H A Dstm32_saes.c248 uint8_t i; in saes_write_iv() local
251 for (i = 0U; i < AES_IVSIZE / sizeof(uint32_t); i++) { in saes_write_iv()
252 mmio_write_32(ctx->base + _SAES_IVR0 + i * sizeof(uint32_t), ctx->iv[i]); in saes_write_iv()
262 uint8_t i; in saes_write_key() local
264 for (i = 0U; i < AES_KEYSIZE_128 / sizeof(uint32_t); i++) { in saes_write_key()
265 mmio_write_32(ctx->base + _SAES_KEYR0 + i * sizeof(uint32_t), ctx->key[i]); in saes_write_key()
269 for (i = 0U; i < (AES_KEYSIZE_256 / 2U) / sizeof(uint32_t); i++) { in saes_write_key()
270 mmio_write_32(ctx->base + _SAES_KEYR4 + i * sizeof(uint32_t), in saes_write_key()
271 ctx->key[i + 4U]); in saes_write_key()
331 uint8_t i; in save_context() local
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/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/
H A Dddrphy_phyinit_loadpieprodcode.c183 int i; in ddrphy_phyinit_loadpieprodcode() local
185 for (i = 0; i < PRODCODE_SIZE; i++) { in ddrphy_phyinit_loadpieprodcode()
186 mmio_write_16((uintptr_t)(DDRPHYC_BASE + (4U * prodcode_addr[i])), in ddrphy_phyinit_loadpieprodcode()
187 prodcode_data[i]); in ddrphy_phyinit_loadpieprodcode()
/rk3399_ARM-atf/plat/arm/board/juno/
H A Djuno_trusted_boot.c29 unsigned int words, i; in juno_get_rotpk_info_regs() local
68 for (i = 0 ; i < words ; i++) { in juno_get_rotpk_info_regs()
69 tmp = src[words - 1 - i]; in juno_get_rotpk_info_regs()
79 for (i = 0 ; i < words ; i++) { in juno_get_rotpk_info_regs()
80 tmp = src[words - 1 - i]; in juno_get_rotpk_info_regs()
/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_a/
H A Dddr_init_d3.c26 uint32_t i, r2, r3, r5, r6, r7, r12; in init_ddr_d3_1866() local
184 for (i = 0; i < 2; i++) { in init_ddr_d3_1866()
185 mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); in init_ddr_d3_1866()
187 mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); in init_ddr_d3_1866()
189 mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); in init_ddr_d3_1866()
193 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_d3_1866()
196 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_d3_1866()
198 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr_d3_1866()
200 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr_d3_1866()
203 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_d3_1866()
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H A Dddr_init_v3m.c17 uint32_t i, r2, r5, r6, r7, r12; in init_ddr_v3m_1600() local
193 for (i = 0; i < 4; i++) { in init_ddr_v3m_1600()
194 mmio_write_32(DBSC_DBPDRGA_0, 0xB1 + i * 0x20); in init_ddr_v3m_1600()
196 mmio_write_32(DBSC_DBPDRGA_0, 0xB4 + i * 0x20); in init_ddr_v3m_1600()
198 mmio_write_32(DBSC_DBPDRGA_0, 0xB3 + i * 0x20); in init_ddr_v3m_1600()
202 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_v3m_1600()
205 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_v3m_1600()
207 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr_v3m_1600()
209 mmio_write_32(DBSC_DBPDRGA_0, 0xB0 + i * 0x20); in init_ddr_v3m_1600()
212 mmio_write_32(DBSC_DBPDRGA_0, 0xB2 + i * 0x20); in init_ddr_v3m_1600()
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/rk3399_ARM-atf/drivers/renesas/common/ddr/ddr_b/
H A Dboot_init_dram.c519 uint32_t i; in dbwait_loop() local
521 for (i = 0; i < wait_loop; i++) in dbwait_loop()
781 uint32_t i; in _tblcopy() local
783 for (i = 0; i < size; i++) { in _tblcopy()
784 to[i] = from[i]; in _tblcopy()
1029 int i; in _f_scale_js2() local
1031 for (i = 0; i < JS2_TBLCNT; i++) { in _f_scale_js2()
1032 _js2[i] = _f_scale(_ddr_mbps, _ddr_mbpsdiv, in _f_scale_js2()
1033 1UL * jedec_spec2[JS2_DERATE][i].ps, in _f_scale_js2()
1034 jedec_spec2[JS2_DERATE][i].cyc); in _f_scale_js2()
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/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_iossm_mailbox.c59 int i; in io96b_mb_req() local
79 for (i = 0; i < 6 ; i++) { in io96b_mb_req()
80 switch (i) { in io96b_mb_req()
152 for (i = 0; i < resp_data_len; i++) { in io96b_mb_req()
153 switch (i) { in io96b_mb_req()
195 int i, j, k; in io96b_mb_init() local
198 for (i = 0; i < io96b_ctrl->num_instance; i++) { in io96b_mb_init()
199 struct io96b_instance *inst = (i == 0) ? in io96b_mb_init()
271 for (int i = 0; i < io96b_ctrl->num_instance; i++) { in init_mem_cal() local
272 struct io96b_instance *inst = (i == 0) ? in init_mem_cal()
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/rk3399_ARM-atf/drivers/arm/gic/v2/
H A Dgicv2_helpers.c127 unsigned int i; in gicv2_secure_spis_configure_props() local
134 for (i = 0; i < interrupt_props_num; i++) { in gicv2_secure_spis_configure_props()
135 prop_desc = &interrupt_props[i]; in gicv2_secure_spis_configure_props()
168 unsigned int i; in gicv2_secure_ppi_sgi_setup_props() local
184 for (i = 0U; i < MIN_SPI_ID; i += 4U) { in gicv2_secure_ppi_sgi_setup_props()
185 gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL); in gicv2_secure_ppi_sgi_setup_props()
187 for (i = 0U; i < interrupt_props_num; i++) { in gicv2_secure_ppi_sgi_setup_props()
188 prop_desc = &interrupt_props[i]; in gicv2_secure_ppi_sgi_setup_props()
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/emi_mpu/
H A Demi_mpu.c57 int region, i; in dump_emi_mpu_regions() local
61 for (i = 0; i < EMI_MPU_DGROUP_NUM; ++i) in dump_emi_mpu_regions()
62 apc[i] = mmio_read_32(EMI_MPU_APC(region, i)); in dump_emi_mpu_regions()
75 int i; in emi_mpu_set_protection() local
83 for (i = EMI_MPU_DGROUP_NUM - 1; i >= 0; i--) { in emi_mpu_set_protection()
85 (i << 24); in emi_mpu_set_protection()
86 _emi_mpu_set_protection(start, end, region_info->apc[i]); in emi_mpu_set_protection()
/rk3399_ARM-atf/plat/amd/versal2/
H A Dbl31_setup.c207 uint32_t i; in request_intr_type_el3() local
217 for (i = 0; i < index; i++) { in request_intr_type_el3()
218 if (id == type_el3_interrupt_table[i].id) { in request_intr_type_el3()
239 uint32_t i; in rdo_el3_interrupt_handler() local
244 for (i = 0; i < MAX_INTR_EL3; i++) { in rdo_el3_interrupt_handler()
245 if (intr_id == type_el3_interrupt_table[i].id) { in rdo_el3_interrupt_handler()
246 handler = type_el3_interrupt_table[i].handler; in rdo_el3_interrupt_handler()
261 uint32_t i; in plat_spmd_handle_group0_interrupt() local
264 for (i = 0; i < MAX_INTR_EL3; i++) { in plat_spmd_handle_group0_interrupt()
265 if (intid == type_el3_interrupt_table[i].id) { in plat_spmd_handle_group0_interrupt()
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