| #
3eb25ebe |
| 18-Oct-2024 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge changes I7d9444d5,I7b104c8e into integration
* changes:
feat(mt8192): update memory protect region
feat(mt8195): update memory protect region
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| #
7587cfdd |
| 14-May-2024 |
kiwi liu <kiwi.liu@mediatek.corp-partner.google.com> |
feat(mt8192): update memory protect region
SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/bas
feat(mt8192): update memory protect region
SCP memory protect region need to align to SCP DRAM range.
Refer to
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/baseboard/mtscp-rv32i/baseboard.h;l=132
Change-Id: I7d9444d5339f71e6bfdd9999a217e0c177e8199f
Signed-off-by: Kiwi Liu <kiwi.liu@mediatek.corp-partner.google.com>
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| #
b085b990 |
| 09-Jun-2021 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(plat/mediatek/mpu): add MPU support for DSP" into integration
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| #
6c4973b0 |
| 28-Apr-2021 |
Jiaxin Yu <jiaxin.yu@mediatek.com> |
feat(plat/mediatek/mpu): add MPU support for DSP
Forbidden domain D4(DSP) access 0x40000000~0x1FFFF0000.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Change-Id: If409df10cecbcccc493d7958ab2765
feat(plat/mediatek/mpu): add MPU support for DSP
Forbidden domain D4(DSP) access 0x40000000~0x1FFFF0000.
Signed-off-by: Jiaxin Yu <jiaxin.yu@mediatek.com>
Change-Id: If409df10cecbcccc493d7958ab2765fd110d9009
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| #
88ddb601 |
| 03-Mar-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "mediatek: mt8192: Add MPU Support for SCP/PCIe" into integration
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| #
a564bdc5 |
| 06-Jan-2021 |
Xi Chen <xixi.chen@mediatek.com> |
mediatek: mt8192: Add MPU Support for SCP/PCIe
1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000;
2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000;
Signed-off-by: Xi
mediatek: mt8192: Add MPU Support for SCP/PCIe
1 Only enable domain D0 and D1:PCIe access 0xC0000000~0xC4000000;
2 Only enable domain D0 and D3(SCP) access 0x50000000~0x51400000;
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ic4f9e6d85bfd1cebdb24ffc1d14309c89c103b2a
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| #
8fdebc94 |
| 22-Dec-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes I65450c63,I71d0aa82,Ia395eb32,I4aaed371 into integration
* changes:
mediatek: mt8192: add rtc power off sequence
mediatek: mt8192: Fix non-MISRA compliant code
mediatek: mt8192:
Merge changes I65450c63,I71d0aa82,Ia395eb32,I4aaed371 into integration
* changes:
mediatek: mt8192: add rtc power off sequence
mediatek: mt8192: Fix non-MISRA compliant code
mediatek: mt8192: Fix non-MISRA compliant code
mediatek: mt8192: Add MPU support
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| #
42f2fa82 |
| 02-Nov-2020 |
Xi Chen <xixi.chen@mediatek.com> |
mediatek: mt8192: Add MPU support
1 Add Domain1(PCIe device) protect address: 0x80000000~0x83FF0000.
2 Add Domain2(SSPM/SPM/DPM/MCUPM) protect address: 0x40000000~0x1FFFF0000.
Signed-off-by: Xi Che
mediatek: mt8192: Add MPU support
1 Add Domain1(PCIe device) protect address: 0x80000000~0x83FF0000.
2 Add Domain2(SSPM/SPM/DPM/MCUPM) protect address: 0x40000000~0x1FFFF0000.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I4aaed37150076ae5943484c4adadac999a3d1762
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