| /rk3399_ARM-atf/plat/mediatek/mt8183/ |
| H A D | plat_pm.c | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/plat/socionext/synquacer/ |
| H A D | sq_psci.c | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/plat/mediatek/mt8173/ |
| H A D | plat_pm.c | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/bl31/ |
| H A D | interrupt_mgmt.c | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/plat/rockchip/common/ |
| H A D | plat_pm.c | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/plat/ti/k3/common/ |
| H A D | k3_psci.c | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/include/bl31/ |
| H A D | interrupt_mgmt.h | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/include/lib/el3_runtime/ |
| H A D | context_mgmt.h | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/plat/arm/common/ |
| H A D | arm_common.c | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/drivers/arm/gic/v3/ |
| H A D | gicv3_main.c | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|
| /rk3399_ARM-atf/lib/el3_runtime/aarch64/ |
| H A D | context_mgmt.c | f1be00da0b0acf90355558e01d5f8e1f79c0d481 Fri Jan 24 13:30:28 UTC 2020 Louis Mayencourt <louis.mayencourt@arm.com> Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
|