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4bbdc391 |
| 28-Jun-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "HEAD" into integration
* changes: feat(synquacer): add FWU Multi Bank Update support feat(synquacer): add TBBR support feat(synquacer): add BL2 support refactor(syn
Merge changes from topic "HEAD" into integration
* changes: feat(synquacer): add FWU Multi Bank Update support feat(synquacer): add TBBR support feat(synquacer): add BL2 support refactor(synquacer): move common source files
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48ab3904 |
| 03-Mar-2022 |
Jassi Brar <jaswinder.singh@linaro.org> |
feat(synquacer): add BL2 support
Add BL2 support by default. Move the legacy mode behind the RESET_TO_BL31 define.
Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro
feat(synquacer): add BL2 support
Add BL2 support by default. Move the legacy mode behind the RESET_TO_BL31 define.
Cc: Sumit Garg <sumit.garg@linaro.org> Cc: Masahisa Kojima <masahisa.kojima@linaro.org> Cc: Manish V Badarkhe <manish.badarkhe@arm.com> Cc: Leonardo Sandoval <leonardo.sandoval@linaro.org> Change-Id: Ic490745a7e8f6114172733428ebd6bd6adfcc1ec Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
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590fd53d |
| 09-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "refactor(plat/synquacer): update PSCI system_off handling" into integration
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e01acbe9 |
| 11-Nov-2021 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
refactor(plat/synquacer): update PSCI system_off handling
SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP) which manages system power. This commit modifies the PSCI system_off handli
refactor(plat/synquacer): update PSCI system_off handling
SynQuacer SoC contains a Cortex-M3 System Control Processor(SCP) which manages system power. This commit modifies the PSCI system_off handling to call SCMI, same as other PSCI calls. System power-off is done by turing off the ATX power supply through GPIO, this operation is transferred to SCP.
Note that this commit modifies only the SCMI case, obsolete SCPI implementation is not updated.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: I6c1009e67cccd1eb5d14c338c3df9103d63709dd
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3a355c2d |
| 14-Sep-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(plat/synquacer): update scmi power domain off handling" into integration
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f7f5d2c4 |
| 03-Aug-2021 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
fix(plat/synquacer): update scmi power domain off handling
In the SCMI power domain off handling, configure GIC to prevent interrupt toward to the core to be turned off, and configure CCN to disable
fix(plat/synquacer): update scmi power domain off handling
In the SCMI power domain off handling, configure GIC to prevent interrupt toward to the core to be turned off, and configure CCN to disable coherency when the cluster is turned off. The same operation is done in SCPI power domain off processing.
This commit adds the missing operation in SCMI power domain off handling.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Change-Id: Ib3523de488500c2e8bdc74e4cb8772a1442d9781
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f69a5828 |
| 30-Jan-2020 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "Use correct type when reading SCR register" into integration
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f1be00da |
| 24-Jan-2020 |
Louis Mayencourt <louis.mayencourt@arm.com> |
Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b6
Use correct type when reading SCR register
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this.
Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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eb9da9e1 |
| 13-Mar-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1856 from masahisak/synquacer-scmi-support
plat/synquacer: enable SCMI support
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b67d2029 |
| 07-Mar-2019 |
Masahisa Kojima <masahisa.kojima@linaro.org> |
plat/synquacer: enable SCMI support
Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific
plat/synquacer: enable SCMI support
Enable the SCMI protocol support in SynQuacer platform. Aside from power domain, system power and apcore management protocol, this commit adds the vendor specific protocol(0x80). This vendor specific protocol is used to get the dram mapping information from SCP.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
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9a207532 |
| 04-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1726 from antonio-nino-diaz-arm/an/includes
Sanitise includes across codebase
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09d40e0e |
| 14-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - inclu
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them).
For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems.
Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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520c9dd4 |
| 22-Jun-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1427 from b49020/integration
Add support for Socionext Synquacer SC2A11 SoC based Developerbox platform.
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753701cc |
| 15-Jun-2018 |
Sumit Garg <sumit.garg@linaro.org> |
synquacer: Enable PSCI framework
PSCI framework uses SCPI driver to communicate to SCP firmware for various power management operations. Following PSCI operations are supported: - CPU ON - CPU OFF -
synquacer: Enable PSCI framework
PSCI framework uses SCPI driver to communicate to SCP firmware for various power management operations. Following PSCI operations are supported: - CPU ON - CPU OFF - CPU STANDBY - SYSTEM RESET - SYSTEM OFF
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
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