Searched hist:c5c160cdddd1c365a447c1fcd148fabb9014cce0 (Results 1 – 4 of 4) sorted by relevance
| /rk3399_ARM-atf/lib/cpus/aarch32/ |
| H A D | cortex_a12.S | c5c160cdddd1c365a447c1fcd148fabb9014cce0 Sun Mar 19 19:30:58 UTC 2023 Stephan Gerhold <stephan@gerhold.net> fix(cpus): flush L2 cache for Cortex-A7/12/15/17
Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.
Fix this by adding the L2 cache flush similar to cortex_a53.S.
Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
|
| H A D | cortex_a7.S | c5c160cdddd1c365a447c1fcd148fabb9014cce0 Sun Mar 19 19:30:58 UTC 2023 Stephan Gerhold <stephan@gerhold.net> fix(cpus): flush L2 cache for Cortex-A7/12/15/17
Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.
Fix this by adding the L2 cache flush similar to cortex_a53.S.
Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
|
| H A D | cortex_a17.S | c5c160cdddd1c365a447c1fcd148fabb9014cce0 Sun Mar 19 19:30:58 UTC 2023 Stephan Gerhold <stephan@gerhold.net> fix(cpus): flush L2 cache for Cortex-A7/12/15/17
Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.
Fix this by adding the L2 cache flush similar to cortex_a53.S.
Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
|
| H A D | cortex_a15.S | c5c160cdddd1c365a447c1fcd148fabb9014cce0 Sun Mar 19 19:30:58 UTC 2023 Stephan Gerhold <stephan@gerhold.net> fix(cpus): flush L2 cache for Cortex-A7/12/15/17
Similar to Cortex-A53, the AArch32-only Cortex-A7/12/15/17 have an
(optional) integrated L2 cache that might need to be flushed if the
whole cluster is powered down. However, unlike Cortex-A53 there is
currently no L2 cache flush in the cluster_pwr_dwn implementation for
some reason. This causes problems if there is unwritten data left in
the L2 cache during a cluster power off.
Fix this by adding the L2 cache flush similar to cortex_a53.S.
Change-Id: Icd087bef9acff11e03edcaa0d26dd8b8e30796b7
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
|