Searched hist:aea772dd7aa85681a9ead19cad4ead1732bbc003 (Results 1 – 6 of 6) sorted by relevance
| /rk3399_ARM-atf/plat/intel/soc/agilex/soc/ |
| H A D | agilex_mmc.c | aea772dd7aa85681a9ead19cad4ead1732bbc003 Mon May 11 08:11:39 UTC 2020 Tien Hock Loh <tien.hock.loh@intel.com> plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
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| /rk3399_ARM-atf/plat/intel/soc/agilex/include/ |
| H A D | agilex_mmc.h | aea772dd7aa85681a9ead19cad4ead1732bbc003 Mon May 11 08:11:39 UTC 2020 Tien Hock Loh <tien.hock.loh@intel.com> plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
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| H A D | agilex_clock_manager.h | aea772dd7aa85681a9ead19cad4ead1732bbc003 Mon May 11 08:11:39 UTC 2020 Tien Hock Loh <tien.hock.loh@intel.com> plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
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| /rk3399_ARM-atf/plat/intel/soc/common/include/ |
| H A D | socfpga_system_manager.h | aea772dd7aa85681a9ead19cad4ead1732bbc003 Mon May 11 08:11:39 UTC 2020 Tien Hock Loh <tien.hock.loh@intel.com> plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
|
| /rk3399_ARM-atf/plat/intel/soc/agilex/ |
| H A D | bl2_plat_setup.c | aea772dd7aa85681a9ead19cad4ead1732bbc003 Mon May 11 08:11:39 UTC 2020 Tien Hock Loh <tien.hock.loh@intel.com> plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
|
| H A D | platform.mk | aea772dd7aa85681a9ead19cad4ead1732bbc003 Mon May 11 08:11:39 UTC 2020 Tien Hock Loh <tien.hock.loh@intel.com> plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
|