Merge changes from topic "fix-agilex-initialization" into integration

* changes:
plat: intel: Additional instruction required to enable global timer
plat: intel: Fix CCU initialization for Agile

Merge changes from topic "fix-agilex-initialization" into integration

* changes:
plat: intel: Additional instruction required to enable global timer
plat: intel: Fix CCU initialization for Agilex
plat: intel: Add FPGAINTF configuration to when configuring pinmux
plat: intel: set DRVSEL and SMPLSEL for DWMMC
plat: intel: Fix clock configuration bugs

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plat: intel: set DRVSEL and SMPLSEL for DWMMC

DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.

Signed-o

plat: intel: set DRVSEL and SMPLSEL for DWMMC

DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.

Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677

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