| #
f3083e2e |
| 07-Aug-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): move common functions to common lib files" into integration
|
| #
6fcd047b |
| 07-Apr-2025 |
Jit Loon Lim <jit.loon.lim@altera.com> |
feat(intel): move common functions to common lib files
This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share a
feat(intel): move common functions to common lib files
This patch is used to move common functions that used across
files into commmon lib files to prevent multiple functions
declaration and share among files.
Change-Id: I19d9727eac895e7bf597a66076a7b68755cbe0ef
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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| #
5a162642 |
| 14-Mar-2025 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): provide atf build version via smc call" into integration
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| #
d1c58d86 |
| 02-Dec-2024 |
Girisha Dengi <girisha.dengi@intel.com> |
feat(intel): provide atf build version via smc call
This patch provides ATF build version via SMC call
on Agilex7, Agilex5, Stratix10 and N5X platforms.
Change-Id: I61af83433fe61f85987f38ffc86380a4
feat(intel): provide atf build version via smc call
This patch provides ATF build version via SMC call
on Agilex7, Agilex5, Stratix10 and N5X platforms.
Change-Id: I61af83433fe61f85987f38ffc86380a41cdb5289
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
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| #
2c878eb6 |
| 28-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "feat(intel): add build option for boot source" into integration
|
| #
02711885 |
| 28-Oct-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge "fix(intel): refactor SDMMC driver for Altera products" into integration
|
| #
beba2040 |
| 25-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): refactor SDMMC driver for Altera products
Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.
Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
S
fix(intel): refactor SDMMC driver for Altera products
Refactor to be more robust. Removed duplicated and not used functions.
Add in ADMA read.
Change-Id: I1a5a00397ece6f9ccc5916225ab5317010b01b52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
ef8b05f5 |
| 24-Oct-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): add build option for boot source
Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update n
feat(intel): add build option for boot source
Existing boot source is hardcoded in socfpga_plat_def.h.
To change boot source, user need to update code.
Thus adding this will remove the code update needed when
need to change boot source.
Also, it will have ARM_LINUX_KERNEL_AS_BL33 flag for each
platform in platform.mk. This will be easily to control
based on platform build.
Change-Id: I383beb8cbca5ec0f247221ad42796554adc3daae
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
44c5f8e5 |
| 22-Aug-2024 |
Mark Dykes <mark.dykes@arm.com> |
Merge changes I23bdbbe1,Ic22ab741 into integration
* changes:
feat(intel): enable VAB support for Intel products
feat(intel): add in SHA384 authentication
|
| #
3eb5640a |
| 19-Jul-2024 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): enable VAB support for Intel products
This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.
Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b
feat(intel): enable VAB support for Intel products
This patch is to implement Vendor Authorize Bootloader
support for Intel Agilex, Agilex5 and N5X.
Change-Id: I23bdbbe15b3732775cea028665e2efcbd04b3aff
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
51ff56e4 |
| 19-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(intel): enable SDMMC frontdoor load for ATF->Linux" into integration
|
| #
b3a7396d |
| 19-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes Iaa189c54,I8856b495 into integration
* changes:
feat(intel): enable query of fip offset on RSU
feat(intel): support query of fip offset using RSU
|
| #
6cbe2c5d |
| 22-Aug-2023 |
Mahesh Rao <mahesh.rao@intel.com> |
feat(intel): enable query of fip offset on RSU
Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform
Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Sign
feat(intel): enable query of fip offset on RSU
Enable query of fip offset from QSPI on RSU boot for
Intel agilex and intel agilex5 platform
Change-Id: Iaa189c54723a8656b9691da5849fd86b9986cfa1
Signed-off-by: Mahesh Rao <mahesh.rao@intel.com>
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| #
07edc5cf |
| 10-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(intel): support wipe DDR after calibration" into integration
|
| #
68bb3e83 |
| 14-Aug-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): support wipe DDR after calibration
After a calibration we cannot trust the DDR content. Let's explicitly
clear the DDR content using the built-in scrubber in this case.
Signed-off-by:
feat(intel): support wipe DDR after calibration
After a calibration we cannot trust the DDR content. Let's explicitly
clear the DDR content using the built-in scrubber in this case.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I6f429623f76a21f61f85efbb660cf65d99c04f56
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| #
32a87d44 |
| 15-Oct-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): enable SDMMC frontdoor load for ATF->Linux
SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR f
feat(intel): enable SDMMC frontdoor load for ATF->Linux
SDMMC is 1 of the boot source for Agilex5 and legacy products.
By enabling this, ATF is able to read out the DTB binary and
loaded it to DDR for Linux boot.
Change-Id: Ida303fb43ea63013a08083ce65952c5ad4e28f93
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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|
| #
455cd0d3 |
| 19-Sep-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "chore: remove MULTI_CONSOLE_API references" into integration
|
| #
13ff6e9d |
| 12-Sep-2023 |
Michal Simek <michal.simek@amd.com> |
chore: remove MULTI_CONSOLE_API references
MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
reference
chore: remove MULTI_CONSOLE_API references
MULTI_CONSOLE_API have been removed long time ago by commit 5b6ebeec9c99
("Remove MULTI_CONSOLE_API flag and references to it") that's why remove
references in platform.mk files and also in one rst which is not valid
anymore.
Change-Id: I45f8e7db0a14ce63de62509100d8159b7aca2657
Signed-off-by: Michal Simek <michal.simek@amd.com>
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| #
a4c69581 |
| 15-Mar-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3" into integration
|
| #
42d4d3ba |
| 22-Nov-2022 |
Arvind Ram Prakash <arvind.ramprakash@arm.com> |
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is runnin
refactor(build): distinguish BL2 as TF-A entry point and BL2 running at EL3
BL2_AT_EL3 is an overloaded macro which has two uses:
1. When BL2 is entry point into TF-A(no BL1)
2. When BL2 is running at EL3 exception level
These two scenarios are not exactly same even though first implicitly
means second to be true. To distinguish between these two use cases we
introduce new macros.
BL2_AT_EL3 is renamed to RESET_TO_BL2 to better convey both 1. and 2.
Additional macro BL2_RUNS_AT_EL3 is added to cover all scenarious where
BL2 runs at EL3 (including four world systems).
BREAKING CHANGE: BL2_AT_EL3 renamed to RESET_TO_BL2 across the
repository.
Change-Id: I477e1d0f843b44b799c216670e028fcb3509fb72
Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Signed-off-by: Maksims Svecovs <maksims.svecovs@arm.com>
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| #
ca3f25dc |
| 21-Nov-2022 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): fix UART baud rate and clock" into integration
|
| #
8e53b2fa |
| 01-Jul-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): fix UART baud rate and clock
Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id:
fix(intel): fix UART baud rate and clock
Revise the UART baud rate and clock for general platform build,
SIMIC build and EMU build.
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I62fefe7b96d5124e75d2810b4fbc1640422b1353
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| #
be1d3a1a |
| 19-May-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "gpt-crc" into integration
* changes:
feat(partition): verify crc while loading gpt header
build(hikey): platform changes for verifying gpt header crc
build(agilex): p
Merge changes from topic "gpt-crc" into integration
* changes:
feat(partition): verify crc while loading gpt header
build(hikey): platform changes for verifying gpt header crc
build(agilex): platform changes for verifying gpt header crc
build(stratix10): platform changes for verifying gpt header crc
build(stm32mp1): platform changes for verifying gpt header crc
show more ...
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| #
7a756a57 |
| 11-May-2022 |
Rohit Ner <rohitner@google.com> |
build(agilex): platform changes for verifying gpt header crc
This change makes the necessary additions to makefile of
platforms using partition driver.
Signed-off-by: Rohit Ner <rohitner@google.com
build(agilex): platform changes for verifying gpt header crc
This change makes the necessary additions to makefile of
platforms using partition driver.
Signed-off-by: Rohit Ner <rohitner@google.com>
Change-Id: I1290972c7d2626262d4b6d68b99bb8f2c4b6744c
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| #
868f9768 |
| 12-May-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration
* changes:
fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
fix(intel): ex
Merge changes Ie9451e35,I1815deeb,If277b2b3,Ie2ceaf24,I7996d505, ... into integration
* changes:
fix(intel): add flash dcache after return response for INTEL_SIP_SMC_MBOX_SEND_CMD
fix(intel): extending to support large file size for SHA2/HMAC get digest and verifying
fix(intel): extending to support large file size for SHA-2 ECDSA data signing and signature verifying
fix(intel): extending to support large file size for AES encryption and decryption
feat(intel): support version 2 SiP SVC SMC function ID for mailbox commands
feat(intel): support version 2 SiP SVC SMC function ID for non-mailbox commands
fix(intel): update certificate mask for FPGA Attestation
feat(intel): update to support maximum response data size
feat(intel): support ECDSA HASH Verification
feat(intel): support ECDSA HASH Signing
feat(intel): support ECDH request
feat(intel): support ECDSA SHA-2 Data Signature Verification
feat(intel): support ECDSA SHA-2 Data Signing
feat(intel): support ECDSA Get Public Key
feat(intel): support session based SDOS encrypt and decrypt
feat(intel): support AES Crypt Service
feat(intel): support HMAC SHA-2 MAC verify request
feat(intel): support SHA-2 hash digest generation on a blob
feat(intel): support extended random number generation
feat(intel): support crypto service key operation
feat(intel): support crypto service session
feat(intel): extend attestation service to Agilex family
fix(intel): flush dcache before sending certificate to mailbox
fix(intel): introduce a generic response error code
fix(intel): allow non-secure access to FPGA Crypto Services (FCS)
feat(intel): single certificate feature enablement
feat(intel): initial commit for attestation service
fix(intel): update encryption and decryption command logic
show more ...
|