| #
9118bdf4 |
| 19-Dec-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration
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| #
150d2be0 |
| 07-Jul-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06a
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
ffc56bd0 |
| 17-Apr-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes I43a9d83c,Ibfaa47fb into integration
* changes:
fix(intel): fix Agilex and N5X clock manager to main PLL C0
feat(intel): implement timer init divider via CPU frequency for N5X
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| #
5f06bffa |
| 22-Dec-2022 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): fix Agilex and N5X clock manager to main PLL C0
Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ
fix(intel): fix Agilex and N5X clock manager to main PLL C0
Update Agilex and N5X clock manager to get MPU clock from mainPLL C0
and PeriPLLC0.
1. Updated macro name PLAT_SYS_COUNTER_CONVERT_TO_MHZ to
PLAT_HZ_CONVERT_TO_MHZ.
2. Updated get_cpu_clk to point to get_mpu_clk and added comment.
3. Added get_mpu_clk to get clock from main PLL C0 and Peri PLL C0.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I43a9d83caa832b61eba93a830e2a671fd4dffa19
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| #
02a9d70c |
| 23-Jun-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): implement timer init divider via CPU frequency for N5X
Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.
Signe
feat(intel): implement timer init divider via CPU frequency for N5X
Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibfaa47fb7a25176eebf06f4828bf9729d56f12ed
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| #
026dfed8 |
| 06-May-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(intel): implement timer init divider via cpu frequency. (#1)" into integration
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| #
f65bdf3a |
| 06-Apr-2022 |
BenjaminLimJL <jit.loon.lim@intel.com> |
feat(intel): implement timer init divider via cpu frequency. (#1)
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The impl
feat(intel): implement timer init divider via cpu frequency. (#1)
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The implementation shall apply to only Agilex and S10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422
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| #
141568da |
| 08-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "fix-agilex-initialization" into integration
* changes:
plat: intel: Additional instruction required to enable global timer
plat: intel: Fix CCU initialization for Agile
Merge changes from topic "fix-agilex-initialization" into integration
* changes:
plat: intel: Additional instruction required to enable global timer
plat: intel: Fix CCU initialization for Agilex
plat: intel: Add FPGAINTF configuration to when configuring pinmux
plat: intel: set DRVSEL and SMPLSEL for DWMMC
plat: intel: Fix clock configuration bugs
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| #
aea772dd |
| 11-May-2020 |
Tien Hock Loh <tien.hock.loh@intel.com> |
plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-o
plat: intel: set DRVSEL and SMPLSEL for DWMMC
DRVSEL and SMPLSEL needs to be set so that it can properly go into full
speed mode. This needs to be done in EL3 as the registers are secured.
Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com>
Change-Id: Ia2f348e7742ff7b76da74d392ef1ce71e2f41677
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| #
b33772eb |
| 04-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge changes from topic "platform-refactor" into integration
* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform c
Merge changes from topic "platform-refactor" into integration
* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform code [2/5]
intel: Refactor common platform code [1/5]
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| #
328718f2 |
| 23-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Refactor common platform code [1/5]
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both
intel: Refactor common platform code [1/5]
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
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| #
3441952f |
| 28-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "intel: agilex: Clear PLL lostlock bypass mode" into integration
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| #
960a12b3 |
| 16-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: agilex: Clear PLL lostlock bypass mode
To provide glitchless clock to downstream logic even if clock toggles
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-
intel: agilex: Clear PLL lostlock bypass mode
To provide glitchless clock to downstream logic even if clock toggles
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I728d64d0ba3b4492125bea5b0737fc83180356f1
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| #
2102198c |
| 14-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge "intel: agilex: Fix reliance on hard coded clock information" into integration
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| #
4e865bd2 |
| 14-Aug-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: agilex: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the clock manager
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@
intel: agilex: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the clock manager
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
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| #
b514ee86 |
| 19-Jul-2019 |
Soby Mathew <soby.mathew@arm.com> |
Merge "intel: Adds support for Agilex platform" into integration
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| #
2f11d548 |
| 27-Jun-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Adds support for Agilex platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
|