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| /rk3399_rockchip-uboot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | immap_lsch2.h | 4de6ce1594fcff6fa9e626d094fa922f4889e167 Mon Aug 08 07:07:20 UTC 2016 Tang Yuantian <Yuantian.Tang@nxp.com> armv8: fsl-lsch2: enable snoopable sata read and write
By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
|
| H A D | soc.h | 4de6ce1594fcff6fa9e626d094fa922f4889e167 Mon Aug 08 07:07:20 UTC 2016 Tang Yuantian <Yuantian.Tang@nxp.com> armv8: fsl-lsch2: enable snoopable sata read and write
By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/ |
| H A D | soc.c | 4de6ce1594fcff6fa9e626d094fa922f4889e167 Mon Aug 08 07:07:20 UTC 2016 Tang Yuantian <Yuantian.Tang@nxp.com> armv8: fsl-lsch2: enable snoopable sata read and write
By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.
Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
|