Merge git://git.denx.de/u-boot-fsl-qoriq

config: ls1012aqds: Enable USB EHCI support for ls1012aqds

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <y

config: ls1012aqds: Enable USB EHCI support for ls1012aqds

Signed-off-by: Rajat Srivastava <rajat.srivastava@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
[YS: Revise subject, remove commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

armv8/ls1043a: fixup GIC offset for ls1043a rev1

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choos

armv8/ls1043a: fixup GIC offset for ls1043a rev1

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.

The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.

If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.

Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.

The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8/fsl-lsch2: refactor the clock system initialization

Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differen

armv8/fsl-lsch2: refactor the clock system initialization

Up to now, there are 3 kind of SoCs under Layerscape Chassis 2,
like LS1043A, LS1046A and LS1012A. But the clocks tree has a
lot of differences, for instance, the IP modules have different
dividers to derive its clock from Platform PLL. And the core
cluster PLL and platform PLL maybe have different reference
clocks, such as LS1012A. Another problem is which clock/PLL
should be described by sys_info->freq_systembus, it is confused
in Layerscape Chissis 2.

This patch is to bind the sys_info->freq_systembus to the Platform
PLL, and handle the different divider of IP modules separately
between different SoCs, and separate reference clocks of core
cluster PLL and platform PLL.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: QSPI: Add AHB bus 16MB+ size support

The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao <yao.y

armv8: QSPI: Add AHB bus 16MB+ size support

The default configuration for QSPI AHB bus can't support 16MB+.
But some flash on NXP layerscape board are more than 16MB.

Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-mpc85xx

script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list

Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT
in Kconfig. Drop this macro for LSCH2 and remove from white list.

Sig

script: remove CONFIG_SYS_CCSRBAR_DEFAULT from white list

Now all mpc85xx and mpc86xx have converted to use SYS_CCSRBAR_DEFAULT
in Kconfig. Drop this macro for LSCH2 and remove from white list.

Signed-off-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h

armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539

Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC

armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539

Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-lsch2: enable snoopable sata read and write

By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCN

armv8: fsl-lsch2: enable snoopable sata read and write

By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>

armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A

Move this config to Kconfig option and clean up existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Calvin Johnson <c

armv8: ls1012a: Convert CONFIG_LS1012A to Kconfig option ARCH_LS1021A

Move this config to Kconfig option and clean up existing uses.

Signed-off-by: York Sun <york.sun@nxp.com>
CC: Calvin Johnson <calvin.johnson@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: fsl_lsch2: Add SerDes 2 support

New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will

armv8: fsl_lsch2: Add SerDes 2 support

New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.

Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-layerscape: Add A72 core detection

Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.

Signed-off-by: Alison Wang <alison.wang@nxp

armv8: fsl-layerscape: Add A72 core detection

Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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include: usb: Rename USB controller base address mapping

Remove Soc specific defines and use generic chasis specific defines
for USB controller base address mapping.

Signed-off-by: Rajesh Bhagat <r

include: usb: Rename USB controller base address mapping

Remove Soc specific defines and use generic chasis specific defines
for USB controller base address mapping.

Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot-usb

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper

Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms,
similar to PPC and ARMv7.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-o

arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper

Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms,
similar to PPC and ARMv7.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwa

armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC

The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.

This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4

Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq