Merge branch 'next-dev' into thunder-boot

UPSTREAM: armv8: ls1043a/ls2080a: check SoC by device ID

Check LS1043A/LS2080a by device ID without using personality ID to
determine revision number. This check applies to all various
personalities

UPSTREAM: armv8: ls1043a/ls2080a: check SoC by device ID

Check LS1043A/LS2080a by device ID without using personality ID to
determine revision number. This check applies to all various
personalities of the same SoC family.

Change-Id: I7be6b46fc17aa7f7a3a40677de0c18c9dd095c52
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit a8f33034f2ed029dd04aae4cfdf11bf1f13a03a2)

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Merge git://git.denx.de/u-boot-fsl-qoriq

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
include/configs/ls1046aqds.h
include/configs/ls1046ardb.h

soc/fsl-layerscape: Update SVR number for LS2081A and LS2041A

Update SVR as per the SOC document.
-LS2081A: 0x870919 -> 0x870918
-LS2041A: 0x870915 -> 0x870914

Signed-off-by: Santan Kumar <santan

soc/fsl-layerscape: Update SVR number for LS2081A and LS2041A

Update SVR as per the SOC document.
-LS2081A: 0x870919 -> 0x870918
-LS2041A: 0x870915 -> 0x870914

Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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common: arm: freescale: layerscape: Move header files out of common.h

We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.

common: arm: freescale: layerscape: Move header files out of common.h

We should not have an arch-specific header file in common.h. Adjust the
board files a little so it is not needed, and drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>

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Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A

armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support

The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and
is built on layerscape architecture. It is 40-pin derivative of
LS2084A (non-AIOP personality of LS2088A). So feature-wise it is
same as LS2084A. LS2041A is a 4-core personality of LS2081A.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

armv8/ls1043a: fixup GIC offset for ls1043a rev1

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choos

armv8/ls1043a: fixup GIC offset for ls1043a rev1

The LS1043A rev1.1 silicon supports two types of GIC offset: 4K
alignment and 64K alignment. The bit SCFG_GIC400_ALIGN[GIC_ADDR_BIT]
is used to choose which offset will be used.

The LS1043A rev1.0 silicon only supports the CIG offset with 4K
alignment.

If GIC_ADDR_BIT bit is set, 4K alignment is used, or else 64K alignment
is used. 64K alignment is the default setting.

Overriding the weak smp_kick_all_cpus, the new impletment is able to
detect GIC offset.

The default GIC offset in kernel device tree is using 4K alignment, it
need to be fixed if 64K alignment is detected.

Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8/fsl_lsch2: Add chip power supply voltage setup

Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed a

armv8/fsl_lsch2: Add chip power supply voltage setup

Set up chip power supply voltage according to voltage ID.
The fuse status register provides the values from on-chip
voltage ID fuses programmed at the factory. These values
define the voltage requirements for the chip.

Main operations:
1. Set up the core voltage
2. Set up the SERDES voltage and reset SERDES lanes
3. Enable/disable DDR controller support 0.9V if needed

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>

Merge git://git.denx.de/u-boot-fsl-qoriq

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
arch/arm/Kconfig

armv8: fsl-layerscape: Add NXP LS2088A SoC support

The QorIQ LS2088A SoC is built on layerscape architecture.

It is similar to LS2080A SoC with some differences like
1)Timer controller offset is di

armv8: fsl-layerscape: Add NXP LS2088A SoC support

The QorIQ LS2088A SoC is built on layerscape architecture.

It is similar to LS2080A SoC with some differences like
1)Timer controller offset is different
2)It has A72 cores
3)It supports TZASC module

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: lsch3: Use SVR based timer base address detection

Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.

Use SVR based tim

armv8: lsch3: Use SVR based timer base address detection

Timer controller base address has been changed from
LS2080A SoC (and its personalities) to new SoCs like
LS2088A, LS1088A.

Use SVR based timer base address detection to avoid compile time #ifdef.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
include/configs/ls1021aqds.h
include/configs/ls1021atwr.h

armv8: fsl-lsch2: enable snoopable sata read and write

By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCN

armv8: fsl-lsch2: enable snoopable sata read and write

By default the SATA IP on the ls1043a/ls1046a SoCs does not
generating coherent/snoopable transactions. This patch enable
it in the SCFG_SNPCNFGCR register along with sata axicc register.
In addition, the dma-coherent property must be set on the SATA
controller nodes.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

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armv8: fsl-lsch2: adjust sata parameter

The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp

armv8: fsl-lsch2: adjust sata parameter

The default values for Port Phy2Cfg register and
Port Phy3Cfg register are better, no need to overwrite them.

Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

trini: Drop local memset() from
examples/standalone/mem_to_mem_idma2intr.c

Signed-off-by: Tom Rini <trini@konsulko.com>

fsl-layerscape: Add workaround for PCIe erratum A010315

As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including

fsl-layerscape: Add workaround for PCIe erratum A010315

As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: fsl_lsch2: Add LS1046A SoC support

The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.

Signed-off-by: Hou Zhiqian

armv8: fsl_lsch2: Add LS1046A SoC support

The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCs

Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.

So append "A" to SoC names.

Signed-of

armv8: fsl-layerscape: Append "A" in SoC name for ARM based SoCs

Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.

So append "A" to SoC names.

Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

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Merge branch 'master' of git://git.denx.de/u-boot-usb

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>