| /rk3399_ARM-atf/plat/allwinner/sun50i_h616/include/ |
| H A D | sunxi_spc.h | 26123ca35313426b2f88a5983e5e69173d1d62d0 Sat Nov 28 01:39:17 UTC 2020 Andre Przywara <andre.przywara@arm.com> allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| H A D | sunxi_ccu.h | 26123ca35313426b2f88a5983e5e69173d1d62d0 Sat Nov 28 01:39:17 UTC 2020 Andre Przywara <andre.przywara@arm.com> allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| H A D | sunxi_mmap.h | 26123ca35313426b2f88a5983e5e69173d1d62d0 Sat Nov 28 01:39:17 UTC 2020 Andre Przywara <andre.przywara@arm.com> allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| H A D | sunxi_cpucfg.h | 26123ca35313426b2f88a5983e5e69173d1d62d0 Sat Nov 28 01:39:17 UTC 2020 Andre Przywara <andre.przywara@arm.com> allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| /rk3399_ARM-atf/plat/allwinner/sun50i_h616/ |
| H A D | platform.mk | 26123ca35313426b2f88a5983e5e69173d1d62d0 Sat Nov 28 01:39:17 UTC 2020 Andre Przywara <andre.przywara@arm.com> allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| H A D | sunxi_power.c | 26123ca35313426b2f88a5983e5e69173d1d62d0 Sat Nov 28 01:39:17 UTC 2020 Andre Przywara <andre.przywara@arm.com> allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| /rk3399_ARM-atf/docs/plat/ |
| H A D | allwinner.rst | 26123ca35313426b2f88a5983e5e69173d1d62d0 Sat Nov 28 01:39:17 UTC 2020 Andre Przywara <andre.przywara@arm.com> allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| /rk3399_ARM-atf/plat/allwinner/common/include/ |
| H A D | platform_def.h | 26123ca35313426b2f88a5983e5e69173d1d62d0 Sat Nov 28 01:39:17 UTC 2020 Andre Przywara <andre.przywara@arm.com> allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|
| /rk3399_ARM-atf/plat/allwinner/common/ |
| H A D | sunxi_common.c | 26123ca35313426b2f88a5983e5e69173d1d62d0 Sat Nov 28 01:39:17 UTC 2020 Andre Przywara <andre.przywara@arm.com> allwinner: Add Allwinner H616 SoC support
The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.
The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.
Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
|