Merge changes from topic "h616_pmics" into integration

* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: ad

Merge changes from topic "h616_pmics" into integration

* changes:
feat(allwinner): adjust H616 L2 cache size in DTB
feat(allwinner): h616: add support for AXP717 PMIC
feat(allwinner): h616: add support for AXP313 PMIC
feat(allwinner): h616: add I2C PMIC support
refactor(allwinner): h616: prepare for more than one PMIC model

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feat(allwinner): adjust H616 L2 cache size in DTB

The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cac

feat(allwinner): adjust H616 L2 cache size in DTB

The Allwinner H616 and its siblings come in different die revisions,
some have 256 KB of L2 cache, some have 1 MB. This prevents a single
static cache description in the devicetree.

Use the cache size ID register (CCSIDR_EL1) to query the topology of the
L2 cache, and adjust the cache-sets and cache-size properties in the L2
cache DT node accordingly.

The ARM ARM does not promise (anymore) that the cache size can be derived
*architecturally* from this register, but the reading is definitely
correct for the Arm Cortex-A53 core used.

Change-Id: Id7dc324d783b8319fe5df6164be2f941d4cac82d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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feat(allwinner): h616: add I2C PMIC support

The X-Powers AXP305 PMIC can be controlled via both I2C or RSB (an
Allwinner specific bus similar to I2C), but we chose to use only RSB,
because that's ea

feat(allwinner): h616: add I2C PMIC support

The X-Powers AXP305 PMIC can be controlled via both I2C or RSB (an
Allwinner specific bus similar to I2C), but we chose to use only RSB,
because that's easier to program and also used by Linux. The AXP313a
PMIC however supports only I2C, so we need to support both buses, and
need to decide which to use at runtime.

Prepare the PMIC code to add (back) I2C support. We initially used I2C
on the H6/AXP805 combination, but replaced that later with RSB. So this
patch is bringing some of that older code back.

The decision whether to use I2C or RSB is made by the devicetree, since
on some boards even RSB capable PMICs are controlled via I2C, since they
share the bus with only I2C capable devices, for instance RTCs.

At the moment this will still use RSB to drive the AXP305, but the
(dynamic) I2C code will be used shortly to support the AXP313.

This increases the code size by one 4K page, but with 80K out of the
reserved 256K we are still very far away from our limit.

Change-Id: I65c1e7df93dbd2dcd171b3fc486533a2948cc75b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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refactor(allwinner): h616: prepare for more than one PMIC model

Most devices based on Allwinner SoCs come with a certain fixed
combination of Power Management ICs (PMICs) and SoC, for instance the
A

refactor(allwinner): h616: prepare for more than one PMIC model

Most devices based on Allwinner SoCs come with a certain fixed
combination of Power Management ICs (PMICs) and SoC, for instance the
A64 with the AXP803, or the H6 with the AXP805. This allowed us to
include the respective PMIC support code into each build target at build
time.

Similarly on H616 devices we initially saw only the AXP305, but for a
while now the simpler (and cheaper) AXP313a is a popular companion to
the H616 on many new boards. On at least one new device the AXP717 is
used as well.
With some rudimentary AXP version check in place we at least detected
the case of an unsupported SoC, but threw an error message, and lost
support for powering off the device.

Refactor the existing PMIC code to be able to support more than one
PMIC model, detected at runtime. For this we use a variable for the RSB
runtime address instead of hardcoding the address used on the AXP305,
and read the hardware bus address from the devicetree.
Also we look up the used PMIC in the devicetree, and set the PMIC model
accordingly. To be on the safe side, we also confirm the real PMIC used
by checking its version register and comparing that with the expected
value. Finally the register offset and value to power off the PMIC is
moved direclty into the platform code, as those values differ between
the different PMICs.

This is just refactoring and better error report, we still only support
the AXP305 on RSB at the moment.

Change-Id: I00b26ce4d30bb570ee1cd4979d0cdc9d6c020729
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge changes from topic "allwinner-idle" into integration

* changes:
feat(allwinner): provide CPU idle states to the rich OS
feat(allwinner): simplify CPU_SUSPEND power state encoding
feat(al

Merge changes from topic "allwinner-idle" into integration

* changes:
feat(allwinner): provide CPU idle states to the rich OS
feat(allwinner): simplify CPU_SUSPEND power state encoding
feat(allwinner): choose PSCI states to avoid translation
feat(fdt): add the ability to supply idle state information
fix(allwinner): improve DTB patching error handling
refactor(allwinner): patch the DTB after setting up PSCI
refactor(allwinner): move DTB change code into allwinner/common

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refactor(allwinner): move DTB change code into allwinner/common

So far the H616 was the only Allwinner SoC needed to amend the DTB, to
reserve the DRAM portion that BL31 occupies.
To allow other SoC

refactor(allwinner): move DTB change code into allwinner/common

So far the H616 was the only Allwinner SoC needed to amend the DTB, to
reserve the DRAM portion that BL31 occupies.
To allow other SoCs to modify the DTB as well, without duplicating code,
move the DTB change routines into Allwinner common code, and generalise
the current code to allow other modifications.

No functional change intended.

Change-Id: I080ea07b6470367f3c2573a4368f8ef5196d411c
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>

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Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
all

Merge changes from topic "allwinner_h616" into integration

* changes:
allwinner: H616: Add reserved-memory node to DT
allwinner: Add Allwinner H616 SoC support
allwinner: Add H616 SoC ID
allwinner: Express memmap more dynamically
allwinner: Move sunxi_cpu_power_off_self() into platforms
allwinner: Move SEPARATE_NOBITS_REGION to platforms
doc: allwinner: Reorder sections, document memory mapping

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allwinner: H616: Add reserved-memory node to DT

When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.

Add a reserved-

allwinner: H616: Add reserved-memory node to DT

When the BL31 for the Allwinner H616 runs in DRAM, we need to make sure
we tell the non-secure world about the memory region it uses.

Add a reserved-memory node to the DT, which covers the area that BL31
could occupy. The "no-map" property will prevent OSes from mapping
the area, so there would be no speculative accesses.

Change-Id: I808f3e1a8089da53bbe4fc6435a808e9159831e1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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allwinner: Add Allwinner H616 SoC support

The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DR

allwinner: Add Allwinner H616 SoC support

The new Allwinner H616 SoC lacks the management controller and the secure
SRAM A2, so we need to tweak the memory map quite substantially:
We run BL31 in DRAM. Since the DRAM starts at 1GB, we cannot use our
compressed virtual address space (max 256MB) anymore, so we revert to
the full 32bit VA space and use a flat mapping throughout all of it.

The missing controller also means we need to always use the native PSCI
ops, using the CPUIDLE hardware, as SCPI and suspend depend on the ARISC.

Change-Id: I77169b452cb7f5dc2ef734f3fc6e5d931749141d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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