Searched +full:video +full:- +full:core0 (Results 1 – 15 of 15) sorted by relevance
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)4 ---5 $id: "http://devicetree.org/schemas/media/qcom,sdm845-venus.yaml#"6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"8 title: Qualcomm Venus video encode and decode accelerators11 - Stanimir Varbanov <stanimir.varbanov@linaro.org>14 The Venus IP is a video encode and decode accelerator present19 const: qcom,sdm845-venus27 power-domains:33 clock-names:[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)4 ---5 $id: "http://devicetree.org/schemas/media/qcom,sdm845-venus-v2.yaml#"6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"8 title: Qualcomm Venus video encode and decode accelerators11 - Stanimir Varbanov <stanimir.varbanov@linaro.org>14 The Venus IP is a video encode and decode accelerator present19 const: qcom,sdm845-venus-v227 power-domains:31 power-domain-names:[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Benoit Parrot <bparrot@ti.com>12 description: |-15 processing capability to connect CSI2 image-sensor modules to the21 Documentation/devicetree/bindings/media/video-interfaces.txt.27 - ti,dra72-cal29 - ti,dra72-pre-es2-cal31 - ti,dra76-cal[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC5 * Copyright (C) 2016-2017 Renesas Electronics Corp.8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/power/r8a77961-sysc.h>16 #address-cells = <2>;17 #size-cells = <2>;25 compatible = "fixed-clock";26 #clock-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.08 #include <dt-bindings/interrupt-controller/irq.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>11 #include <dt-bindings/power/r8a774a1-sysc.h>17 #address-cells = <2>;18 #size-cells = <2>;37 compatible = "fixed-clock";38 #clock-cells = <0>;39 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car M3-W (R8A77960) SoC5 * Copyright (C) 2016-2017 Renesas Electronics Corp.8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/power/r8a7796-sysc.h>16 #address-cells = <2>;17 #size-cells = <2>;36 compatible = "fixed-clock";37 #clock-cells = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.08 #include <dt-bindings/interrupt-controller/irq.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>11 #include <dt-bindings/power/r8a774e1-sysc.h>17 #address-cells = <2>;18 #size-cells = <2>;26 compatible = "fixed-clock";27 #clock-cells = <0>;28 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Device Tree Source for the R-Car H3 (R8A77951) SoC8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>9 #include <dt-bindings/interrupt-controller/arm-gic.h>10 #include <dt-bindings/power/r8a7795-sysc.h>16 #address-cells = <2>;17 #size-cells = <2>;36 compatible = "fixed-clock";37 #clock-cells = <0>;38 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only2 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.5 #include <dt-bindings/interrupt-controller/arm-gic.h>6 #include <dt-bindings/clock/qcom,gcc-msm8996.h>7 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>8 #include <dt-bindings/clock/qcom,rpmcc.h>9 #include <dt-bindings/soc/qcom,apr.h>12 interrupt-parent = <&intc>;14 #address-cells = <2>;15 #size-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.08 #include <dt-bindings/clock/qcom,camcc-sdm845.h>9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>11 #include <dt-bindings/clock/qcom,gpucc-sdm845.h>12 #include <dt-bindings/clock/qcom,lpass-sdm845.h>13 #include <dt-bindings/clock/qcom,rpmh.h>14 #include <dt-bindings/clock/qcom,videocc-sdm845.h>15 #include <dt-bindings/interconnect/qcom,osm-l3.h>16 #include <dt-bindings/interconnect/qcom,sdm845.h>[all …]
1 // SPDX-License-Identifier: BSD-3-Clause8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>12 #include <dt-bindings/clock/qcom,rpmh.h>13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>14 #include <dt-bindings/interconnect/qcom,osm-l3.h>15 #include <dt-bindings/interconnect/qcom,sc7180.h>16 #include <dt-bindings/interrupt-controller/arm-gic.h>[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/rk3399-cru.h>7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/interrupt-controller/irq.h>10 #include <dt-bindings/pinctrl/rockchip.h>11 #include <dt-bindings/power/rk3399-power.h>12 #include <dt-bindings/soc/rockchip,boot-mode.h>13 #include <dt-bindings/soc/rockchip-system-status.h>14 #include <dt-bindings/suspend/rockchip-rk3399.h>[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)6 #include <dt-bindings/clock/rk3528-cru.h>7 #include <dt-bindings/gpio/gpio.h>8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/interrupt-controller/irq.h>10 #include <dt-bindings/phy/phy.h>11 #include <dt-bindings/pinctrl/rockchip.h>12 #include <dt-bindings/power/rk3528-power.h>13 #include <dt-bindings/soc/rockchip,boot-mode.h>14 #include <dt-bindings/soc/rockchip-system-status.h>[all …]
... d dbm, %d mW Override is %s -o -d -q -m Error: Missing ...
2 * Chip-specific hardware definitions for14 * <<Broadcom-WL-IPTag/Proprietary:>>70 #define TX_AC_BE_FIFO 1 /**< Access Category Best-Effort TX FIFO */71 #define TX_AC_VI_FIFO 2 /**< Access Class Video TX FIFO */82 #define TX_TRIG_BE_FIFO 7 /**< Access Category Best-Effort TX FIFO */83 #define TX_TRIG_VI_FIFO 8 /**< Access Class Video TX FIFO */239 #define MI_ATIMWINEND (1 << 5) /**< end of ATIM-window (IBSS) */242 #define MI_NSPECGEN_1 (1 << 8) /**< non-specific gen-stat bits that are set by PSM */247 #define MI_GP0 (1 << 13) /**< General-purpose timer0 */248 #define MI_GP1 (1 << 14) /**< General-purpose timer1 */[all …]