1 /* 2 * Chip-specific hardware definitions for 3 * Broadcom 802.11abg Networking Device Driver 4 * 5 * Broadcom Proprietary and Confidential. Copyright (C) 2020, 6 * All Rights Reserved. 7 * 8 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom; 9 * the contents of this file may not be disclosed to third parties, 10 * copied or duplicated in any form, in whole or in part, without 11 * the prior written permission of Broadcom. 12 * 13 * 14 * <<Broadcom-WL-IPTag/Proprietary:>> 15 */ 16 17 #ifndef _D11_H 18 #define _D11_H 19 20 /* 21 * Notes: 22 * 1. pre40/pre rev40: corerev < 40 23 * 2. pre80/pre rev80: 40 <= corerev < 80 24 * 3. rev40/D11AC: 80 > corerev >= 40 25 * 4. rev80: corerev >= 80 26 */ 27 28 #include <typedefs.h> 29 #include <hndsoc.h> 30 #include <sbhnddma.h> 31 #include <802.11.h> 32 33 #if defined(BCMDONGLEHOST) || defined(WL_UNITTEST) 34 typedef struct { 35 uint32 pad; 36 } shmdefs_t; 37 #else /* defined(BCMDONGLEHOST)|| defined(WL_UNITTEST) */ 38 #include <d11shm.h> 39 #ifdef USE_BCMCONF_H 40 #include <bcmconf.h> 41 #else 42 #include <wlc_cfg.h> 43 #endif 44 #endif /* !defined(BCMDONGLEHOST)|| !defined(WL_UNITTEST) */ 45 46 #include <d11regs.h> 47 48 /* This marks the start of a packed structure section. */ 49 #include <packed_section_start.h> 50 51 /* cpp contortions to concatenate w/arg prescan */ 52 #ifndef PAD 53 #define _PADLINE(line) pad ## line 54 #define _XSTR(line) _PADLINE(line) 55 #define PAD _XSTR(__LINE__) 56 #endif 57 58 #define D11AC_BCN_TMPL_LEN 640 /**< length of the BCN template area for 11AC */ 59 60 #define LPRS_TMPL_LEN 512 /**< length of the legacy PRS template area */ 61 62 /* RX FIFO numbers */ 63 #define RX_FIFO 0 /**< data and ctl frames */ 64 #define RX_FIFO1 1 /**< ctl frames */ 65 #define RX_FIFO2 2 /**< ctl frames */ 66 #define RX_FIFO_NUMBER 3 67 68 /* TX FIFO numbers using WME Access Classes */ 69 #define TX_AC_BK_FIFO 0 /**< Access Category Background TX FIFO */ 70 #define TX_AC_BE_FIFO 1 /**< Access Category Best-Effort TX FIFO */ 71 #define TX_AC_VI_FIFO 2 /**< Access Class Video TX FIFO */ 72 #define TX_AC_VO_FIFO 3 /**< Access Class Voice TX FIFO */ 73 #define TX_BCMC_FIFO 4 /**< Broadcast/Multicast TX FIFO */ 74 #define TX_ATIM_FIFO 5 /**< TX fifo for ATIM window info */ 75 #define TX_AC_N_DATA_FIFO 4 /**< Number of legacy Data Fifos (BK, BE, VI, VO) */ 76 77 /* TX FIFO numbers for trigger queues for HE STA only chips (i.e 78 * This is valid only for 4369 or similar STA chips that supports 79 * a single HE STA connection. 80 */ 81 #define TX_TRIG_BK_FIFO 6 /**< Access Category Background TX FIFO */ 82 #define TX_TRIG_BE_FIFO 7 /**< Access Category Best-Effort TX FIFO */ 83 #define TX_TRIG_VI_FIFO 8 /**< Access Class Video TX FIFO */ 84 #define TX_TRIG_VO_FIFO 9 /**< Access Class Voice TX FIFO */ 85 #define TX_TRIG_HP_FIFO 10 /**< Access High Priority TX FIFO */ 86 #define TX_TRIG_N_DATA_FIFO 4 /**< Number of Trigger Data Fifos (BK, BE, VI, VO) */ 87 88 #if defined(WL11AX_TRIGGERQ) && !defined(WL11AX_TRIGGERQ_DISABLED) 89 #define IS_TRIG_FIFO(fifo) \ 90 (((fifo) >= TX_TRIG_BK_FIFO) && ((fifo) < (TX_TRIG_BK_FIFO + TX_TRIG_N_DATA_FIFO))) 91 #else 92 #define IS_TRIG_FIFO(fifo) FALSE 93 #endif /* defined(WL11AX_TRIGGERQ) && !defined(WL11AX_TRIGGERQ_DISABLED) */ 94 95 #define IS_AC_FIFO(fifo) \ 96 ((fifo) < (TX_AC_BK_FIFO + TX_AC_N_DATA_FIFO)) 97 98 /** Legacy TX FIFO numbers */ 99 #define TX_DATA_FIFO TX_AC_BE_FIFO 100 #define TX_CTL_FIFO TX_AC_VO_FIFO 101 102 /** Trig TX FIFO numbers */ 103 #define TX_TRIG_DATA_FIFO TX_TRIG_BE_FIFO 104 #define TX_TRIG_CTL_FIFO TX_TRIG_VO_FIFO 105 106 /* Extended FIFOs for corerev >= 64 */ 107 #define TX_FIFO_6 6 108 #define TX_FIFO_7 7 109 #define TX_FIFO_16 16 110 #define TX_FIFO_23 23 111 #define TX_FIFO_25 25 112 113 #define TX_FIFO_EXT_START TX_FIFO_6 /* Starting index of extendied HW TX FIFOs */ 114 #define TX_FIFO_MU_START 8 /* index at which MU TX FIFOs start */ 115 116 #define D11REG_IHR_WBASE 0x200 117 #define D11REG_IHR_BASE (D11REG_IHR_WBASE << 1) 118 119 #define PIHR_BASE 0x0400 /**< byte address of packed IHR region */ 120 121 /* biststatus */ 122 #define BT_DONE (1U << 31) /**< bist done */ 123 #define BT_B2S (1 << 30) /**< bist2 ram summary bit */ 124 125 /* DMA intstatus and intmask */ 126 #define I_PC (1 << 10) /**< pci descriptor error */ 127 #define I_PD (1 << 11) /**< pci data error */ 128 #define I_DE (1 << 12) /**< descriptor protocol error */ 129 #define I_RU (1 << 13) /**< receive descriptor underflow */ 130 #define I_RO (1 << 14) /**< receive fifo overflow */ 131 #define I_XU (1 << 15) /**< transmit fifo underflow */ 132 #define I_RI (1 << 16) /**< receive interrupt */ 133 #define I_XI (1 << 24) /**< transmit interrupt */ 134 135 /* interrupt receive lazy */ 136 #define IRL_TO_MASK 0x00ffffff /**< timeout */ 137 #define IRL_FC_MASK 0xff000000 /**< frame count */ 138 #define IRL_FC_SHIFT 24 /**< frame count */ 139 #define IRL_DISABLE 0x01000000 /**< Disabled value: int on 1 frame, zero time */ 140 141 /** for correv >= 80. prev rev uses bit 21 */ 142 #define MCTL_BCNS_PROMISC_SHIFT 21 143 /** for correv < 80. prev rev uses bit 20 */ 144 #define MCTL_BCNS_PROMISC_SHIFT_LT80 20 145 146 /* maccontrol register */ 147 #define MCTL_GMODE (1U << 31) 148 #define MCTL_DISCARD_PMQ (1 << 30) 149 #define MCTL_DISCARD_TXSTATUS (1 << 29) 150 #define MCTL_TBTT_HOLD (1 << 28) 151 #define MCTL_CLOSED_NETWORK (1 << 27) 152 #define MCTL_WAKE (1 << 26) 153 #define MCTL_HPS (1 << 25) 154 #define MCTL_PROMISC (1 << 24) 155 #define MCTL_KEEPBADFCS (1 << 23) 156 #define MCTL_KEEPCONTROL (1 << 22) 157 #define MCTL_BCNS_PROMISC (1 << MCTL_BCNS_PROMISC_SHIFT) 158 #define MCTL_BCNS_PROMISC_LT80 (1 << MCTL_BCNS_PROMISC_SHIFT_LT80) 159 #define MCTL_NO_TXDMA_LAST_PTR (1 << 20) /** for correv >= 85 */ 160 #define MCTL_LOCK_RADIO (1 << 19) 161 #define MCTL_AP (1 << 18) 162 #define MCTL_INFRA (1 << 17) 163 #define MCTL_BIGEND (1 << 16) 164 #define MCTL_DISABLE_CT (1 << 14) /** for corerev >= 83.1 */ 165 #define MCTL_GPOUT_SEL_MASK (3 << 14) 166 #define MCTL_GPOUT_SEL_SHIFT 14 167 #define MCTL_EN_PSMDBG (1 << 13) 168 #define MCTL_IHR_EN (1 << 10) 169 #define MCTL_SHM_UPPER (1 << 9) 170 #define MCTL_SHM_EN (1 << 8) 171 #define MCTL_PSM_JMP_0 (1 << 2) 172 #define MCTL_PSM_RUN (1 << 1) 173 #define MCTL_EN_MAC (1 << 0) 174 175 /* maccontrol1 register */ 176 #define MCTL1_GCPS (1u << 0u) 177 #define MCTL1_EGS_MASK 0x0000c000 178 #define MCTL1_EGS_SHIFT 14u 179 #define MCTL1_AVB_ENABLE (1u << 1u) 180 #define MCTL1_GPIOSEL_SHIFT 8u 181 #define MCTL1_GPIOSEL (0x3F) 182 #define MCTL1_GPIOSEL_MASK (MCTL1_GPIOSEL << MCTL1_GPIOSEL_SHIFT) 183 /* Select MAC_SMPL_CPTR debug data that is placed in pc<7:1> & ifs_gpio_out<8:0> GPIOs */ 184 #define MCTL1_GPIOSEL_TSF_PC_IFS(_corerev) (D11REV_GE(_corerev, 85) ? 0x3b : 0x36) 185 #define MCTL1_AVB_TRIGGER (1u << 2u) 186 #define MCTL1_THIRD_AXI1_FOR_PSM (1u << 3u) 187 #define MCTL1_AXI1_FOR_RX (1u << 4u) 188 #define MCTL1_TXDMA_ENABLE_PASS (1u << 5u) 189 /* SampleCollectPlayCtrl */ 190 #define SC_PLAYCTRL_MASK_ENABLE (1u << 8u) 191 #define SC_PLAYCTRL_TRANS_MODE (1u << 6u) 192 #define SC_PLAYCTRL_SRC_SHIFT 3u 193 #define SC_PLAYCTRL_SRC_MASK (3u << SC_PLAYCTRL_SRC_SHIFT) 194 #define SC_PLAYCTRL_SRC_PHY_DBG (3u << SC_PLAYCTRL_SRC_SHIFT) 195 #define SC_PLAYCTRL_SRC_GPIO_OUT (2u << SC_PLAYCTRL_SRC_SHIFT) 196 #define SC_PLAYCTRL_SRC_GPIO_IN (1u << SC_PLAYCTRL_SRC_SHIFT) 197 #define SC_PLAYCTRL_SRC_PHY_SMPL (0u << SC_PLAYCTRL_SRC_SHIFT) 198 #define SC_PLAYCTRL_STOP (1u << 2u) 199 #define SC_PLAYCTRL_PAUSE (1u << 1u) 200 #define SC_PLAYCTRL_START (1u << 0u) 201 /* SCPortalSel fields */ 202 #define SC_PORTAL_SEL_AUTO_INCR (1u << 15u) /* Autoincr */ 203 #define SC_PORTAL_SEL_STORE_MASK (0u << 5u) /* Bits 14:5 SCStoreMask15to0 */ 204 #define SC_PORTAL_SEL_MATCH_MASK (4u << 5u) /* Bits 14:5 SCMatchMask15to0 */ 205 #define SC_PORTAL_SEL_MATCH_VALUE (8u << 5u) /* Bits 14:5 SCMatchValue15to0 */ 206 #define SC_PORTAL_SEL_TRIGGER_MASK (12u << 0u) /* Bits 4:0 SCTriggerMask15to0 */ 207 #define SC_PORTAL_SEL_TRIGGER_VALUE (16u << 0u) /* Bits 4:0 SCTriggerValue15to0 */ 208 #define SC_PORTAL_SEL_TRANS_MASK (20u << 0u) /* Bits 4:0 SCTransMask15to0 */ 209 210 /* GpioOut register */ 211 #define MGPIO_OUT_RXQ1_IFIFO_CNT_MASK 0x1fc0u 212 #define MGPIO_OUT_RXQ1_IFIFO_CNT_SHIFT 6u 213 214 #define MAC_RXQ1_IFIFO_CNT_ADDR 0x26u 215 #define MAC_RXQ1_IFIFO_MAXLEN 3u 216 217 /* maccommand register */ 218 #define MCMD_BCN0VLD (1 << 0) 219 #define MCMD_BCN1VLD (1 << 1) 220 #define MCMD_DIRFRMQVAL (1 << 2) 221 #define MCMD_CCA (1 << 3) 222 #define MCMD_BG_NOISE (1 << 4) 223 #define MCMD_SKIP_SHMINIT (1 << 5) /**< only used for simulation */ 224 #define MCMD_SLOWCAL (1 << 6) 225 #define MCMD_SAMPLECOLL MCMD_SKIP_SHMINIT /**< reuse for sample collect */ 226 #define MCMD_IF_DOWN (1 << 8 ) /**< indicate interface is going down */ 227 #define MCMD_TOF (1 << 9) /**< wifi ranging processing in ucode for rxd frames */ 228 #define MCMD_TSYNC (1 << 10) /**< start timestamp sync process in ucode */ 229 #define MCMD_RADIO_DOWN (1 << 11) /**< radio down by ucode */ 230 #define MCMD_RADIO_UP (1 << 12) /**< radio up by ucode */ 231 #define MCMD_TXPU (1 << 13) /**< txpu control by ucode */ 232 233 /* macintstatus/macintmask */ 234 #define MI_MACSSPNDD (1 << 0) /**< MAC has gracefully suspended */ 235 #define MI_BCNTPL (1 << 1) /**< beacon template available */ 236 #define MI_TBTT (1 << 2) /**< TBTT indication */ 237 #define MI_BCNSUCCESS (1 << 3) /**< beacon successfully tx'd */ 238 #define MI_BCNCANCLD (1 << 4) /**< beacon canceled (IBSS) */ 239 #define MI_ATIMWINEND (1 << 5) /**< end of ATIM-window (IBSS) */ 240 #define MI_PMQ (1 << 6) /**< PMQ entries available */ 241 #define MI_ALTTFS (1 << 7) /**< TX status interrupt for ARM offloads */ 242 #define MI_NSPECGEN_1 (1 << 8) /**< non-specific gen-stat bits that are set by PSM */ 243 #define MI_MACTXERR (1 << 9) /**< MAC level Tx error */ 244 #define MI_PMQERR (1 << 10) 245 #define MI_PHYTXERR (1 << 11) /**< PHY Tx error */ 246 #define MI_PME (1 << 12) /**< Power Management Event */ 247 #define MI_GP0 (1 << 13) /**< General-purpose timer0 */ 248 #define MI_GP1 (1 << 14) /**< General-purpose timer1 */ 249 #define MI_DMAINT (1 << 15) /**< (ORed) DMA-interrupts */ 250 #define MI_TXSTOP (1 << 16) /**< MAC has completed a TX FIFO Suspend/Flush */ 251 #define MI_CCA (1 << 17) /**< MAC has completed a CCA measurement */ 252 #define MI_BG_NOISE (1 << 18) /**< MAC has collected background noise samples */ 253 #define MI_DTIM_TBTT (1 << 19) /**< MBSS DTIM TBTT indication */ 254 #define MI_PRQ (1 << 20) /**< Probe response queue needs attention */ 255 #define MI_HEB (1 << 21) /**< HEB (Hardware Event Block) interrupt - 11ax cores */ 256 #define MI_BT_RFACT_STUCK (1 << 22) /**< MAC has detected invalid BT_RFACT pin, 257 * valid when rev < 15 258 */ 259 #define MI_TTTT (1 << 22) /**< Target TIM Transmission Time, 260 * valid in rev = 26/29, or rev >= 42 261 */ 262 #define MI_BT_PRED_REQ (1 << 23) /**< MAC requested driver BTCX predictor calc */ 263 #define MI_BCNTRIM_RX (1 << 24) /**< PSM received a partial beacon */ 264 #define MI_P2P (1 << 25) /**< WiFi P2P interrupt */ 265 #define MI_DMATX (1 << 26) /**< MAC new frame ready */ 266 #define MI_TSSI_LIMIT (1 << 27) /**< Tssi Limit Reach, TxIdx=0/127 Interrupt */ 267 #define MI_HWACI_NOTIFY (1 << 27) /**< HWACI detects ACI, Apply Mitigation settings */ 268 #define MI_RFDISABLE (1 << 28) /**< MAC detected a change on RF Disable input 269 * (corerev >= 10) 270 */ 271 #define MI_TFS (1 << 29) /**< MAC has completed a TX (corerev >= 5) */ 272 #define MI_LEGACY_BUS_ERROR (1 << 30) /**< uCode indicated bus error */ 273 #define MI_TO (1U << 31) /**< general purpose timeout (corerev >= 3) */ 274 275 #define MI_RXOV MI_NSPECGEN_1 /**< rxfifo overflow interrupt */ 276 277 /* macintstatus_ext/macintmask_ext */ 278 #define MI_BUS_ERROR (1U << 0u) /**< uCode indicated bus error */ 279 #define MI_VCOPLL (1U << 1u) /**< uCode indicated PLL lock issue */ 280 #define MI_EXT_PS_CHG (1U << 2u) /**< Power state is changing (PS 0 <-> 1) */ 281 #define MI_DIS_ULOFDMA (1U << 3u) /**< ucode indicated disabling ULOFDMA request */ 282 #define MI_EXT_PM_OFFLOAD (1U << 4u) /**< PM offload */ 283 #define MI_OBSS_INTR (1U << 5u) /**< OBSS detection interrupt */ 284 #define MI_SENSORC_CX_REQ (1U << 6u) /**< SensorC Mitigation Request interrupt */ 285 #define MI_RLL_NAV_HOF (1U << 7u) /**< RLLW Switch */ 286 287 #define MI_EXT_TXE_SHARED_ERR (1U << 28u) /* Error event in blocks inside TXE shared 288 * (BMC/AQM/AQM-DMA/MIF) 289 */ 290 291 /* Mac capabilities registers */ 292 #define MCAP_TKIPMIC 0x80000000 /**< TKIP MIC hardware present */ 293 #define MCAP_TKIPPH2KEY 0x40000000 /**< TKIP phase 2 key hardware present */ 294 #define MCAP_BTCX 0x20000000 /**< BT coexistence hardware and pins present */ 295 #define MCAP_MBSS 0x10000000 /**< Multi-BSS hardware present */ 296 #define MCAP_RXFSZ_MASK 0x0ff80000 /**< Rx fifo size in blocks (revid >= 16) */ 297 #define MCAP_RXFSZ_SHIFT 19 298 #define MCAP_NRXQ_MASK 0x00070000 /**< Max Rx queues supported - 1 */ 299 #define MCAP_NRXQ_SHIFT 16 300 #define MCAP_UCMSZ_MASK 0x0000e000 /**< Ucode memory size */ 301 #define MCAP_UCMSZ_3K3 0 /**< 3328 Words Ucode memory, in unit of 50-bit */ 302 #define MCAP_UCMSZ_4K 1 /**< 4096 Words Ucode memory */ 303 #define MCAP_UCMSZ_5K 2 /**< 5120 Words Ucode memory */ 304 #define MCAP_UCMSZ_6K 3 /**< 6144 Words Ucode memory */ 305 #define MCAP_UCMSZ_8K 4 /**< 8192 Words Ucode memory */ 306 #define MCAP_UCMSZ_SHIFT 13 307 #define MCAP_TXFSZ_MASK 0x00000ff8 /**< Tx fifo size (* 512 bytes) */ 308 #define MCAP_TXFSZ_SHIFT 3 309 #define MCAP_NTXQ_MASK 0x00000007 /**< Max Tx queues supported - 1 */ 310 #define MCAP_NTXQ_SHIFT 0 311 312 #define MCAP_BTCX_SUP(corerev) (MCAP_BTCX) 313 314 #define MCAP_UCMSZ_TYPES 8 /**< different Ucode memory size types */ 315 316 /* machwcap1 */ 317 #define MCAP1_ERC_MASK 0x00000001 /**< external radio coexistence */ 318 #define MCAP1_ERC_SHIFT 0 319 #define MCAP1_SHMSZ_MASK 0x0000000e /**< shm size (corerev >= 16) */ 320 #define MCAP1_SHMSZ_SHIFT 1 321 #define MCAP1_SHMSZ_1K 0 /**< 1024 words in unit of 32-bit */ 322 #define MCAP1_SHMSZ_2K 1 /**< 1536 words in unit of 32-bit */ 323 #define MCAP1_NUMMACCHAINS 0x00003000 /**< Indicates one less than the 324 number of MAC Chains in the MAC. 325 */ 326 #define MCAP1_NUMMACCHAINS_SHIFT 12 327 #define MCAP1_RXBLMAX_MASK 0x1800000u 328 #define MCAP1_RXBLMAX_SHIFT 23u 329 #define MCAP1_NUM_HEB_MASK 0xE0000000u 330 #define MCAP1_NUM_HEB_SHIFT 29u 331 #define MCAP1_NUM_HEB_FACTOR 3u 332 #define MCAP1_CT_CAPABLE_SHIFT 17 333 334 /* BTCX control */ 335 #define BTCX_CTRL_EN 0x0001 /**< Enable BTCX module */ 336 #define BTCX_CTRL_SW 0x0002 /**< Enable software override */ 337 #define BTCX_CTRL_DSBLBTCXOUT 0x8000 /* Disable txconf/prisel signal output from btcx module */ 338 339 #define BTCX_CTRL_PRI_POL 0x0080 /* Invert prisel polarity */ 340 #define BTCX_CTRL_TXC_POL 0x0020 /* Invert txconf polarity */ 341 342 #define SW_PRI_ON 1 /* switch prisel polarity */ 343 #define SW_TXC_ON 2 /* switch txconf polarity */ 344 345 /* BTCX status */ 346 #define BTCX_STAT_RA 0x0001 /**< RF_ACTIVE state */ 347 348 /* BTCX transaction control */ 349 #define BTCX_TRANS_ANTSEL 0x0040 /**< ANTSEL output */ 350 #define BTCX_TRANS_TXCONF 0x0080 /**< TX_CONF output */ 351 352 /* pmqhost data */ 353 #define PMQH_DATA_MASK 0xffff0000 /**< data entry of head pmq entry */ 354 #define PMQH_BSSCFG 0x00100000 /**< PM entry for BSS config */ 355 #define PMQH_PMOFF 0x00010000 /**< PM Mode OFF: power save off */ 356 #define PMQH_PMON 0x00020000 /**< PM Mode ON: power save on */ 357 #define PMQH_PMPS 0x00200000 /**< PM Mode PRETEND */ 358 #define PMQH_DASAT 0x00040000 /**< Dis-associated or De-authenticated */ 359 #define PMQH_ATIMFAIL 0x00080000 /**< ATIM not acknowledged */ 360 #define PMQH_DEL_ENTRY 0x00000001 /**< delete head entry */ 361 #define PMQH_DEL_MULT 0x00000002 /**< delete head entry to cur read pointer -1 */ 362 #define PMQH_OFLO 0x00000004 /**< pmq overflow indication */ 363 #define PMQH_NOT_EMPTY 0x00000008 /**< entries are present in pmq */ 364 365 /* phydebug (corerev >= 3) */ 366 #define PDBG_CRS (1 << 0) /**< phy is asserting carrier sense */ 367 #define PDBG_TXA (1 << 1) /**< phy is taking xmit byte from mac this cycle */ 368 #define PDBG_TXF (1 << 2) /**< mac is instructing the phy to transmit a frame */ 369 #define PDBG_TXE (1 << 3) /**< phy is signaling a transmit Error to the mac */ 370 #define PDBG_RXF (1 << 4) /**< phy detected the end of a valid frame preamble */ 371 #define PDBG_RXS (1 << 5) /**< phy detected the end of a valid PLCP header */ 372 #define PDBG_RXFRG (1 << 6) /**< rx start not asserted */ 373 #define PDBG_RXV (1 << 7) /**< mac is taking receive byte from phy this cycle */ 374 #define PDBG_RFD (1 << 16) /**< RF portion of the radio is disabled */ 375 376 /* objaddr register */ 377 #define OBJADDR_UCM_SEL 0x00000000 378 #define OBJADDR_SHM_SEL 0x00010000 379 #define OBJADDR_SCR_SEL 0x00020000 380 #define OBJADDR_IHR_SEL 0x00030000 381 #define OBJADDR_RCMTA_SEL 0x00040000 382 #define OBJADDR_AMT_SEL 0x00040000 383 #define OBJADDR_SRCHM_SEL 0x00060000 384 #define OBJADDR_KEYTBL_SEL 0x000c0000 385 #define OBJADDR_HEB_SEL 0x00120000 386 #define OBJADDR_TXDC_TBL_SEL 0x00140000 387 #define OBJADDR_TXDC_RIB_SEL 0x00150000 388 #define OBJADDR_FCBS_SEL 0x00160000 389 #define OBJADDR_LIT_SEL 0x00170000 390 #define OBJADDR_LIB_SEL 0x00180000 391 #define OBJADDR_WINC 0x01000000 392 #define OBJADDR_RINC 0x02000000 393 #define OBJADDR_AUTO_INC 0x03000000 394 /* SHM/SCR/IHR/SHMX/SCRX/IHRX allow 2 bytes read/write, else only 4 bytes */ 395 #define OBJADDR_2BYTES_ACCESS(sel) \ 396 (((sel & 0x70000) == OBJADDR_SHM_SEL) || \ 397 ((sel & 0x70000) == OBJADDR_SCR_SEL) || \ 398 ((sel & 0x70000) == OBJADDR_IHR_SEL)) 399 400 /* objdata register */ 401 #define OBJDATA_WR_COMPLT 0x00000001 402 403 /* frmtxstatus */ 404 #define TXS_V (1 << 0) /**< valid bit */ 405 406 #define TXS_STATUS_MASK 0xffff 407 /* sw mask to map txstatus for corerevs <= 4 to be the same as for corerev > 4 */ 408 #define TXS_COMPAT_MASK 0x3 409 #define TXS_COMPAT_SHIFT 1 410 #define TXS_FID_MASK 0xffff0000 411 #define TXS_FID_SHIFT 16 412 413 /* frmtxstatus2 */ 414 #define TXS_SEQ_MASK 0xffff 415 #define TXS_PTX_MASK 0xff0000 416 #define TXS_PTX_SHIFT 16 417 #define TXS_MU_MASK 0x01000000 418 #define TXS_MU_SHIFT 24 419 420 /* clk_ctl_st, corerev >= 17 */ 421 #define CCS_ERSRC_REQ_D11PLL 0x00000100 /**< d11 core pll request */ 422 #define CCS_ERSRC_REQ_PHYPLL 0x00000200 /**< PHY pll request */ 423 #define CCS_ERSRC_REQ_PTMPLL 0x00001000 /* PTM clock request */ 424 #define CCS_ERSRC_AVAIL_D11PLL 0x01000000 /**< d11 core pll available */ 425 #define CCS_ERSRC_AVAIL_PHYPLL 0x02000000 /**< PHY pll available */ 426 #define CCS_ERSRC_AVAIL_PTMPLL 0x10000000 /**< PHY pll available */ 427 428 /* tsf_cfprep register */ 429 #define CFPREP_CBI_MASK 0xffffffc0 430 #define CFPREP_CBI_SHIFT 6 431 #define CFPREP_CFPP 0x00000001 432 433 /* receive fifo control */ 434 #define RFC_FR (1 << 0) /**< frame ready */ 435 #define RFC_DR (1 << 1) /**< data ready */ 436 437 /* tx fifo sizes for corerev >= 9 */ 438 /* tx fifo sizes values are in terms of 256 byte blocks */ 439 #define TXFIFOCMD_RESET_MASK (1 << 15) /**< reset */ 440 #define TXFIFOCMD_FIFOSEL_SHIFT 8 /**< fifo */ 441 #define TXFIFOCMD_FIFOSEL_SET(val) ((val & 0x7) << TXFIFOCMD_FIFOSEL_SHIFT) /* fifo */ 442 #define TXFIFOCMD_FIFOSEL_GET(val) ((val >> TXFIFOCMD_FIFOSEL_SHIFT) & 0x7) /* fifo */ 443 #define TXFIFO_FIFOTOP_SHIFT 8 /**< fifo start */ 444 445 #define TXFIFO_FIFO_START(def, def1) ((def & 0xFF) | ((def1 & 0xFF) << 8)) 446 #define TXFIFO_FIFO_END(def, def1) (((def & 0xFF00) >> 8) | (def1 & 0xFF00)) 447 448 /* Must redefine to 65 for 16 MBSS */ 449 #ifdef WLLPRS 450 #define TXFIFO_START_BLK16 (65+16) /**< Base address + 32 * 512 B/P + 8 * 512 11g P */ 451 #else /* WLLPRS */ 452 #define TXFIFO_START_BLK16 65 /**< Base address + 32 * 512 B/P */ 453 #endif /* WLLPRS */ 454 #define TXFIFO_START_BLK 6 /**< Base address + 6 * 256 B */ 455 #define TXFIFO_START_BLK_NIN 7 /**< Base address + 6 * 256 B */ 456 457 #define TXFIFO_AC_SIZE_PER_UNIT 512 /**< one unit corresponds to 512 bytes */ 458 459 #define MBSS16_TEMPLMEM_MINBLKS 65 /**< one unit corresponds to 256 bytes */ 460 461 /* phy versions, PhyVersion:Revision field */ 462 #define PV_AV_MASK 0xf000 /**< analog block version */ 463 #define PV_AV_SHIFT 12 /**< analog block version bitfield offset */ 464 #define PV_PT_MASK 0x0f00 /**< phy type */ 465 #define PV_PT_SHIFT 8 /**< phy type bitfield offset */ 466 #define PV_PV_MASK 0x00ff /**< phy version */ 467 #define PHY_TYPE(v) ((v & PV_PT_MASK) >> PV_PT_SHIFT) 468 469 /* phy types, PhyVersion:PhyType field */ 470 #ifndef USE_BCMCONF_H 471 #define PHY_TYPE_A 0 /**< A-Phy value */ 472 #define PHY_TYPE_B 1 /**< B-Phy value */ 473 #define PHY_TYPE_G 2 /**< G-Phy value */ 474 #define PHY_TYPE_N 4 /**< N-Phy value */ 475 /* #define PHY_TYPE_LP 5 */ /**< LP-Phy value */ 476 /* #define PHY_TYPE_SSN 6 */ /**< SSLPN-Phy value */ 477 #define PHY_TYPE_HT 7 /**< 3x3 HTPhy value */ 478 #define PHY_TYPE_LCN 8 /**< LCN-Phy value */ 479 #define PHY_TYPE_LCNXN 9 /**< LCNXN-Phy value */ 480 #define PHY_TYPE_LCN40 10 /**< LCN40-Phy value */ 481 #define PHY_TYPE_AC 11 /**< AC-Phy value */ 482 #define PHY_TYPE_LCN20 12 /**< LCN20-Phy value */ 483 #define PHY_TYPE_HE 13 /**< HE-Phy value */ 484 #define PHY_TYPE_NULL 0xf /**< Invalid Phy value */ 485 #endif /* USE_BCMCONF_H */ 486 487 /* analog types, PhyVersion:AnalogType field */ 488 #define ANA_11G_018 1 489 #define ANA_11G_018_ALL 2 490 #define ANA_11G_018_ALLI 3 491 #define ANA_11G_013 4 492 #define ANA_11N_013 5 493 #define ANA_11LP_013 6 494 495 /** 802.11a PLCP header def */ 496 typedef struct ofdm_phy_hdr ofdm_phy_hdr_t; 497 BWL_PRE_PACKED_STRUCT struct ofdm_phy_hdr { 498 uint8 rlpt[3]; /**< rate, length, parity, tail */ 499 uint16 service; 500 uint8 pad; 501 } BWL_POST_PACKED_STRUCT; 502 503 #define D11A_PHY_HDR_GRATE(phdr) ((phdr)->rlpt[0] & 0x0f) 504 #define D11A_PHY_HDR_GRES(phdr) (((phdr)->rlpt[0] >> 4) & 0x01) 505 #define D11A_PHY_HDR_GLENGTH(phdr) (((*((uint32 *)((phdr)->rlpt))) >> 5) & 0x0fff) 506 #define D11A_PHY_HDR_GPARITY(phdr) (((phdr)->rlpt[3] >> 1) & 0x01) 507 #define D11A_PHY_HDR_GTAIL(phdr) (((phdr)->rlpt[3] >> 2) & 0x3f) 508 509 /** rate encoded per 802.11a-1999 sec 17.3.4.1 */ 510 #define D11A_PHY_HDR_SRATE(phdr, rate) \ 511 ((phdr)->rlpt[0] = ((phdr)->rlpt[0] & 0xf0) | ((rate) & 0xf)) 512 /** set reserved field to zero */ 513 #define D11A_PHY_HDR_SRES(phdr) ((phdr)->rlpt[0] &= 0xef) 514 /** length is number of octets in PSDU */ 515 #define D11A_PHY_HDR_SLENGTH(phdr, length) \ 516 (*(uint32 *)((phdr)->rlpt) = *(uint32 *)((phdr)->rlpt) | \ 517 (((length) & 0x0fff) << 5)) 518 /** set the tail to all zeros */ 519 #define D11A_PHY_HDR_STAIL(phdr) ((phdr)->rlpt[3] &= 0x03) 520 521 #define D11A_PHY_HDR_LEN_L 3 /**< low-rate part of PLCP header */ 522 #define D11A_PHY_HDR_LEN_R 2 /**< high-rate part of PLCP header */ 523 524 #define D11A_PHY_TX_DELAY (2) /**< 2.1 usec */ 525 526 #define D11A_PHY_HDR_TIME (4) /**< low-rate part of PLCP header */ 527 #define D11A_PHY_PRE_TIME (16) 528 #define D11A_PHY_PREHDR_TIME (D11A_PHY_PRE_TIME + D11A_PHY_HDR_TIME) 529 530 /** 802.11b PLCP header def */ 531 typedef struct cck_phy_hdr cck_phy_hdr_t; 532 BWL_PRE_PACKED_STRUCT struct cck_phy_hdr { 533 uint8 signal; 534 uint8 service; 535 uint16 length; 536 uint16 crc; 537 } BWL_POST_PACKED_STRUCT; 538 539 #define D11B_PHY_HDR_LEN 6 540 541 #define D11B_PHY_TX_DELAY (3) /**< 3.4 usec */ 542 543 #define D11B_PHY_LHDR_TIME (D11B_PHY_HDR_LEN << 3) 544 #define D11B_PHY_LPRE_TIME (144) 545 #define D11B_PHY_LPREHDR_TIME (D11B_PHY_LPRE_TIME + D11B_PHY_LHDR_TIME) 546 547 #define D11B_PHY_SHDR_TIME (D11B_PHY_LHDR_TIME >> 1) 548 #define D11B_PHY_SPRE_TIME (D11B_PHY_LPRE_TIME >> 1) 549 #define D11B_PHY_SPREHDR_TIME (D11B_PHY_SPRE_TIME + D11B_PHY_SHDR_TIME) 550 551 #define D11B_PLCP_SIGNAL_LOCKED (1 << 2) 552 #define D11B_PLCP_SIGNAL_LE (1 << 7) 553 554 /* AMPDUXXX: move to ht header file once it is ready: Mimo PLCP */ 555 #define MIMO_PLCP_MCS_MASK 0x7f /**< mcs index */ 556 #define MIMO_PLCP_40MHZ 0x80 /**< 40 Hz frame */ 557 #define MIMO_PLCP_AMPDU 0x08 /**< ampdu */ 558 559 #define WLC_GET_CCK_PLCP_LEN(plcp) (plcp[4] + (plcp[5] << 8)) 560 #define WLC_GET_MIMO_PLCP_LEN(plcp) (plcp[1] + (plcp[2] << 8)) 561 #define WLC_SET_MIMO_PLCP_LEN(plcp, len) \ 562 plcp[1] = len & 0xff; plcp[2] = ((len >> 8) & 0xff); 563 564 #define WLC_SET_MIMO_PLCP_AMPDU(plcp) (plcp[3] |= MIMO_PLCP_AMPDU) 565 #define WLC_CLR_MIMO_PLCP_AMPDU(plcp) (plcp[3] &= ~MIMO_PLCP_AMPDU) 566 #define WLC_IS_MIMO_PLCP_AMPDU(plcp) (plcp[3] & MIMO_PLCP_AMPDU) 567 568 /** 569 * The dot11a PLCP header is 5 bytes. To simplify the software (so that we don't need eg different 570 * tx DMA headers for 11a and 11b), the PLCP header has padding added in the ucode. 571 */ 572 #define D11_PHY_HDR_LEN 6u 573 574 /** For the AC phy PLCP is 12 bytes and not all bytes are used for all the modulations */ 575 #define D11AC_PHY_HDR_LEN 12 576 #define D11AC_PHY_VHT_PLCP_OFFSET 0 577 #define D11AC_PHY_HTMM_PLCP_OFFSET 0 578 #define D11AC_PHY_HTGF_PLCP_OFFSET 3 579 #define D11AC_PHY_OFDM_PLCP_OFFSET 3 580 #define D11AC_PHY_CCK_PLCP_OFFSET 6 581 #define D11AC_PHY_BEACON_PLCP_OFFSET 0 582 583 #define D11_PHY_RXPLCP_LEN(rev) (D11_PHY_HDR_LEN) 584 #define D11_PHY_RXPLCP_OFF(rev) (0) 585 586 /** TX descriptor - pre40 */ 587 typedef struct d11txh_pre40 d11txh_pre40_t; 588 BWL_PRE_PACKED_STRUCT struct d11txh_pre40 { 589 uint16 MacTxControlLow; /* 0x0 */ 590 uint16 MacTxControlHigh; /* 0x1 */ 591 uint16 MacFrameControl; /* 0x2 */ 592 uint16 TxFesTimeNormal; /* 0x3 */ 593 uint16 PhyTxControlWord; /* 0x4 */ 594 uint16 PhyTxControlWord_1; /* 0x5 */ 595 uint16 PhyTxControlWord_1_Fbr; /* 0x6 */ 596 uint16 PhyTxControlWord_1_Rts; /* 0x7 */ 597 uint16 PhyTxControlWord_1_FbrRts; /* 0x8 */ 598 uint16 MainRates; /* 0x9 */ 599 uint16 XtraFrameTypes; /* 0xa */ 600 uint8 IV[16]; /* 0x0b - 0x12 */ 601 uint8 TxFrameRA[6]; /* 0x13 - 0x15 */ 602 uint16 TxFesTimeFallback; /* 0x16 */ 603 uint8 RTSPLCPFallback[6]; /* 0x17 - 0x19 */ 604 uint16 RTSDurFallback; /* 0x1a */ 605 uint8 FragPLCPFallback[6]; /* 0x1b - 1d */ 606 uint16 FragDurFallback; /* 0x1e */ 607 uint16 MModeLen; /* 0x1f */ 608 uint16 MModeFbrLen; /* 0x20 */ 609 uint16 TstampLow; /* 0x21 */ 610 uint16 TstampHigh; /* 0x22 */ 611 uint16 ABI_MimoAntSel; /* 0x23 */ 612 uint16 PreloadSize; /* 0x24 */ 613 uint16 AmpduSeqCtl; /* 0x25 */ 614 uint16 TxFrameID; /* 0x26 */ 615 uint16 TxStatus; /* 0x27 */ 616 uint16 MaxNMpdus; /* 0x28 corerev >=16 */ 617 BWL_PRE_PACKED_STRUCT union { 618 uint16 MaxAggDur; /* 0x29 corerev >=16 */ 619 uint16 MaxAggLen; 620 } BWL_POST_PACKED_STRUCT u1; 621 BWL_PRE_PACKED_STRUCT union { 622 BWL_PRE_PACKED_STRUCT struct { /* 0x29 corerev >=16 */ 623 uint8 MaxRNum; 624 uint8 MaxAggBytes; /* Max Agg Bytes in power of 2 */ 625 } BWL_POST_PACKED_STRUCT s1; 626 uint16 MaxAggLen_FBR; 627 } BWL_POST_PACKED_STRUCT u2; 628 uint16 MinMBytes; /* 0x2b corerev >=16 */ 629 uint8 RTSPhyHeader[D11_PHY_HDR_LEN]; /* 0x2c - 0x2e */ 630 struct dot11_rts_frame rts_frame; /* 0x2f - 0x36 */ 631 uint16 pad; /* 0x37 */ 632 } BWL_POST_PACKED_STRUCT; 633 634 #define D11_TXH_LEN 112 /**< bytes */ 635 636 /* Frame Types */ 637 #define FT_LEGACY (-1) 638 #define FT_CCK 0 639 #define FT_OFDM 1 640 #define FT_HT 2 641 #define FT_VHT 3 642 #define FT_HE 4 643 #define FT_EHT 6 644 645 /* HE PPDU type */ 646 #define HE_SU_PPDU 0 647 #define HE_SU_RE_PPDU 1 648 #define HE_MU_PPDU 2 649 #define HE_TRIG_PPDU 3 650 651 /* Position of MPDU inside A-MPDU; indicated with bits 10:9 of MacTxControlLow */ 652 #define TXC_AMPDU_SHIFT 9 /**< shift for ampdu settings */ 653 #define TXC_AMPDU_NONE 0 /**< Regular MPDU, not an A-MPDU */ 654 #define TXC_AMPDU_FIRST 1 /**< first MPDU of an A-MPDU */ 655 #define TXC_AMPDU_MIDDLE 2 /**< intermediate MPDU of an A-MPDU */ 656 #define TXC_AMPDU_LAST 3 /**< last (or single) MPDU of an A-MPDU */ 657 658 /* MacTxControlLow */ 659 #define TXC_AMIC 0x8000 660 #define TXC_USERIFS 0x4000 661 #define TXC_LIFETIME 0x2000 662 #define TXC_FRAMEBURST 0x1000 663 #define TXC_SENDCTS 0x0800 664 #define TXC_AMPDU_MASK 0x0600 665 #define TXC_BW_40 0x0100 666 #define TXC_FREQBAND_5G 0x0080 667 #define TXC_DFCS 0x0040 668 #define TXC_IGNOREPMQ 0x0020 669 #define TXC_HWSEQ 0x0010 670 #define TXC_STARTMSDU 0x0008 671 #define TXC_SENDRTS 0x0004 672 #define TXC_LONGFRAME 0x0002 673 #define TXC_IMMEDACK 0x0001 674 675 /* MacTxControlHigh */ 676 #define TXC_PREAMBLE_RTS_FB_SHORT 0x8000 /* RTS fallback preamble type 1 = SHORT 0 = LONG */ 677 #define TXC_PREAMBLE_RTS_MAIN_SHORT 0x4000 /* RTS main rate preamble type 1 = SHORT 0 = LONG */ 678 #define TXC_PREAMBLE_DATA_FB_SHORT 0x2000 /**< Main fallback rate preamble type 679 * 1 = SHORT for OFDM/GF for MIMO 680 * 0 = LONG for CCK/MM for MIMO 681 */ 682 /* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */ 683 #define TXC_AMPDU_FBR 0x1000 /**< use fallback rate for this AMPDU */ 684 #define TXC_SECKEY_MASK 0x0FF0 685 #define TXC_SECKEY_SHIFT 4 686 #define TXC_ALT_TXPWR 0x0008 /**< Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */ 687 #define TXC_SECTYPE_MASK 0x0007 688 #define TXC_SECTYPE_SHIFT 0 689 690 /* Null delimiter for Fallback rate */ 691 #define AMPDU_FBR_NULL_DELIM 5 /**< Location of Null delimiter count for AMPDU */ 692 693 /* PhyTxControl for Mimophy */ 694 #define PHY_TXC_PWR_MASK 0xFC00 695 #define PHY_TXC_PWR_SHIFT 10 696 #define PHY_TXC_ANT_MASK 0x03C0 /**< bit 6, 7, 8, 9 */ 697 #define PHY_TXC_ANT_SHIFT 6 698 #define PHY_TXC_ANT_0_1 0x00C0 /**< auto, last rx */ 699 #define PHY_TXC_LPPHY_ANT_LAST 0x0000 700 #define PHY_TXC_ANT_3 0x0200 /**< virtual antenna 3 */ 701 #define PHY_TXC_ANT_2 0x0100 /**< virtual antenna 2 */ 702 #define PHY_TXC_ANT_1 0x0080 /**< virtual antenna 1 */ 703 #define PHY_TXC_ANT_0 0x0040 /**< virtual antenna 0 */ 704 705 #define PHY_TXC_SHORT_HDR 0x0010 706 #define PHY_TXC_FT_MASK 0x0003 707 708 #define PHY_TXC_FT_CCK 0x0000 709 #define PHY_TXC_FT_OFDM 0x0001 710 #define PHY_TXC_FT_HT 0x0002 711 #define PHY_TXC_FT_VHT 0x0003 712 #define PHY_TXC_FT_HE 0x0004 713 #define PHY_TXC_FT_EHT 0x0006 714 715 #define PHY_TXC_OLD_ANT_0 0x0000 716 #define PHY_TXC_OLD_ANT_1 0x0100 717 #define PHY_TXC_OLD_ANT_LAST 0x0300 718 719 /** PhyTxControl_1 for Mimophy */ 720 #define PHY_TXC1_BW_MASK 0x0007 721 #define PHY_TXC1_BW_10MHZ 0 722 #define PHY_TXC1_BW_10MHZ_UP 1 723 #define PHY_TXC1_BW_20MHZ 2 724 #define PHY_TXC1_BW_20MHZ_UP 3 725 #define PHY_TXC1_BW_40MHZ 4 726 #define PHY_TXC1_BW_40MHZ_DUP 5 727 #define PHY_TXC1_MODE_SHIFT 3 728 #define PHY_TXC1_MODE_MASK 0x0038 729 #define PHY_TXC1_MODE_SISO 0 730 #define PHY_TXC1_MODE_CDD 1 731 #define PHY_TXC1_MODE_STBC 2 732 #define PHY_TXC1_MODE_SDM 3 733 #define PHY_TXC1_CODE_RATE_SHIFT 8 734 #define PHY_TXC1_CODE_RATE_MASK 0x0700 735 #define PHY_TXC1_CODE_RATE_1_2 0 736 #define PHY_TXC1_CODE_RATE_2_3 1 737 #define PHY_TXC1_CODE_RATE_3_4 2 738 #define PHY_TXC1_CODE_RATE_4_5 3 739 #define PHY_TXC1_CODE_RATE_5_6 4 740 #define PHY_TXC1_CODE_RATE_7_8 6 741 #define PHY_TXC1_MOD_SCHEME_SHIFT 11 742 #define PHY_TXC1_MOD_SCHEME_MASK 0x3800 743 #define PHY_TXC1_MOD_SCHEME_BPSK 0 744 #define PHY_TXC1_MOD_SCHEME_QPSK 1 745 #define PHY_TXC1_MOD_SCHEME_QAM16 2 746 #define PHY_TXC1_MOD_SCHEME_QAM64 3 747 #define PHY_TXC1_MOD_SCHEME_QAM256 4 748 749 /* PhyTxControl for HTphy that are different from Mimophy */ 750 #define PHY_TXC_HTANT_MASK 0x3fC0 /**< bit 6, 7, 8, 9, 10, 11, 12, 13 */ 751 #define PHY_TXC_HTCORE_MASK 0x03C0 /**< core enable core3:core0, 1=enable, 0=disable */ 752 #define PHY_TXC_HTCORE_SHIFT 6 /**< bit 6, 7, 8, 9 */ 753 #define PHY_TXC_HTANT_IDX_MASK 0x3C00 /**< 4-bit, 16 possible antenna configuration */ 754 #define PHY_TXC_HTANT_IDX_SHIFT 10 755 #define PHY_TXC_HTANT_IDX0 0 756 #define PHY_TXC_HTANT_IDX1 1 757 #define PHY_TXC_HTANT_IDX2 2 758 #define PHY_TXC_HTANT_IDX3 3 759 760 /* PhyTxControl_1 for HTphy that are different from Mimophy */ 761 #define PHY_TXC1_HTSPARTIAL_MAP_MASK 0x7C00 /**< bit 14:10 */ 762 #define PHY_TXC1_HTSPARTIAL_MAP_SHIFT 10 763 #define PHY_TXC1_HTTXPWR_OFFSET_MASK 0x01f8 /**< bit 8:3 */ 764 #define PHY_TXC1_HTTXPWR_OFFSET_SHIFT 3 765 766 /* TxControl word follows new interface for AX */ 767 /* PhyTxControl_6 for AXphy */ 768 #define PHY_TXC5_AXTXPWR_OFFSET_C0_MASK 0xff00 /**< bit 15:8 */ 769 #define PHY_TXC5_AXTXPWR_OFFSET_C0_SHIFT 8 770 #define PHY_TXC6_AXTXPWR_OFFSET_C1_MASK 0x00ff /**< bit 7:0 */ 771 #define PHY_TXC6_AXTXPWR_OFFSET_C1_SHIFT 0 772 #define PHY_TXC5_AXTXPWR_OFFSET_C2_MASK 0x00ff /**< bit 7:0 */ 773 #define PHY_TXC5_AXTXPWR_OFFSET_C2_SHIFT 0 774 775 /* XtraFrameTypes */ 776 #define XFTS_RTS_FT_SHIFT 2 777 #define XFTS_FBRRTS_FT_SHIFT 4 778 #define XFTS_CHANNEL_SHIFT 8 779 780 /** Antenna diversity bit in ant_wr_settle */ 781 #define PHY_AWS_ANTDIV 0x2000 782 783 /* IFS ctl */ 784 #define IFS_USEEDCF (1 << 2) 785 786 /* IFS ctl1 */ 787 #define IFS_CTL1_EDCRS (1 << 3) 788 #define IFS_CTL1_EDCRS_20L (1 << 4) 789 #define IFS_CTL1_EDCRS_40 (1 << 5) 790 #define IFS_EDCRS_MASK (IFS_CTL1_EDCRS | IFS_CTL1_EDCRS_20L | IFS_CTL1_EDCRS_40) 791 #define IFS_EDCRS_SHIFT 3 792 793 /* IFS ctl sel pricrs */ 794 #define IFS_CTL_CRS_SEL_20LL 1 795 #define IFS_CTL_CRS_SEL_20LU 2 796 #define IFS_CTL_CRS_SEL_20UL 4 797 #define IFS_CTL_CRS_SEL_20UU 8 798 #define IFS_CTL_CRS_SEL_MASK (IFS_CTL_CRS_SEL_20LL | IFS_CTL_CRS_SEL_20LU | \ 799 IFS_CTL_CRS_SEL_20UL | IFS_CTL_CRS_SEL_20UU) 800 #define IFS_CTL_ED_SEL_20LL (1 << 8) 801 #define IFS_CTL_ED_SEL_20LU (1 << 9) 802 #define IFS_CTL_ED_SEL_20UL (1 << 10) 803 #define IFS_CTL_ED_SEL_20UU (1 << 11) 804 #define IFS_CTL_ED_SEL_MASK (IFS_CTL_ED_SEL_20LL | IFS_CTL_ED_SEL_20LU | \ 805 IFS_CTL_ED_SEL_20UL | IFS_CTL_ED_SEL_20UU) 806 807 /* ABI_MimoAntSel */ 808 #define ABI_MAS_ADDR_BMP_IDX_MASK 0x0f00 809 #define ABI_MAS_ADDR_BMP_IDX_SHIFT 8 810 #define ABI_MAS_FBR_ANT_PTN_MASK 0x00f0 811 #define ABI_MAS_FBR_ANT_PTN_SHIFT 4 812 #define ABI_MAS_MRT_ANT_PTN_MASK 0x000f 813 814 #ifdef WLAWDL 815 #define ABI_MAS_AWDL_TS_INSERT 0x1000 /**< bit 12 */ 816 #endif 817 818 #define ABI_MAS_TIMBC_TSF 0x2000 /**< Enable TIMBC tsf field present */ 819 820 /* MinMBytes */ 821 #define MINMBYTES_PKT_LEN_MASK 0x0300 822 #define MINMBYTES_FBRATE_PWROFFSET_MASK 0xFC00 823 #define MINMBYTES_FBRATE_PWROFFSET_SHIFT 10 824 825 /* Rev40 template constants */ 826 827 /** templates include a longer PLCP header that matches the MAC / PHY interface */ 828 #define D11_VHT_PLCP_LEN 12 829 830 /* 11AC TX DMA buffer header */ 831 832 #define D11AC_TXH_NUM_RATES 4 833 834 /** per rate info - rev40 */ 835 typedef struct d11actxh_rate d11actxh_rate_t; 836 BWL_PRE_PACKED_STRUCT struct d11actxh_rate { 837 uint16 PhyTxControlWord_0; /* 0 - 1 */ 838 uint16 PhyTxControlWord_1; /* 2 - 3 */ 839 uint16 PhyTxControlWord_2; /* 4 - 5 */ 840 uint8 plcp[D11_PHY_HDR_LEN]; /* 6 - 11 */ 841 uint16 FbwInfo; /* 12 -13, fall back bandwidth info */ 842 uint16 TxRate; /* 14 */ 843 uint16 RtsCtsControl; /* 16 */ 844 uint16 Bfm0; /* 18 */ 845 } BWL_POST_PACKED_STRUCT; 846 847 /* Bit definition for FbwInfo field */ 848 #define FBW_BW_MASK 3 849 #define FBW_BW_SHIFT 0 850 #define FBW_TXBF 4 851 #define FBW_TXBF_SHIFT 2 852 /* this needs to be re-visited if we want to use this feature */ 853 #define FBW_BFM0_TXPWR_MASK 0x1F8 854 #define FBW_BFM0_TXPWR_SHIFT 3 855 #define FBW_BFM_TXPWR_MASK 0x7E00 856 #define FBW_BFM_TXPWR_SHIFT 9 857 858 /* Bit definition for Bfm0 field */ 859 #define BFM0_TXPWR_MASK 0x3f 860 #define BFM0_STBC_SHIFT 6 861 #define BFM0_STBC (1 << BFM0_STBC_SHIFT) 862 /* should find a chance to converge the two */ 863 #define D11AC2_BFM0_TXPWR_MASK 0x7f 864 #define D11AC2_BFM0_STBC_SHIFT 7 865 #define D11AC2_BFM0_STBC (1 << D11AC2_BFM0_STBC_SHIFT) 866 867 /* per packet info */ 868 typedef struct d11pktinfo_common d11pktinfo_common_t; 869 typedef struct d11pktinfo_common d11actxh_pkt_t; 870 BWL_PRE_PACKED_STRUCT struct d11pktinfo_common { 871 /* Per pkt info */ 872 uint16 TSOInfo; /* 0 */ 873 uint16 MacTxControlLow; /* 2 */ 874 uint16 MacTxControlHigh; /* 4 */ 875 uint16 Chanspec; /* 6 */ 876 uint8 IVOffset; /* 8 */ 877 uint8 PktCacheLen; /* 9 */ 878 uint16 FrameLen; /* 10. In [bytes] units. */ 879 uint16 TxFrameID; /* 12 */ 880 uint16 Seq; /* 14 */ 881 uint16 Tstamp; /* 16 */ 882 uint16 TxStatus; /* 18 */ 883 } BWL_POST_PACKED_STRUCT; 884 885 /* common cache info between rev40 and rev80 formats */ 886 typedef struct d11txh_cache_common d11txh_cache_common_t; 887 BWL_PRE_PACKED_STRUCT struct d11txh_cache_common { 888 uint8 BssIdEncAlg; /* 0 */ 889 uint8 KeyIdx; /* 1 */ 890 uint8 PrimeMpduMax; /* 2 */ 891 uint8 FallbackMpduMax; /* 3 */ 892 uint16 AmpduDur; /* 4 - 5 */ 893 uint8 BAWin; /* 6 */ 894 uint8 MaxAggLen; /* 7 */ 895 } BWL_POST_PACKED_STRUCT; 896 897 /** Per cache info - rev40 */ 898 typedef struct d11actxh_cache d11actxh_cache_t; 899 BWL_PRE_PACKED_STRUCT struct d11actxh_cache { 900 d11txh_cache_common_t common; /* 0 - 7 */ 901 uint8 TkipPH1Key[10]; /* 8 - 17 */ 902 uint8 TSCPN[6]; /* 18 - 23 */ 903 } BWL_POST_PACKED_STRUCT; 904 905 /** Long format tx descriptor - rev40 */ 906 typedef struct d11actxh d11actxh_t; 907 BWL_PRE_PACKED_STRUCT struct d11actxh { 908 /* Per pkt info */ 909 d11actxh_pkt_t PktInfo; /* 0 - 19 */ 910 911 union { 912 913 /** Rev 40 to rev 63 layout */ 914 struct { 915 /** Per rate info */ 916 d11actxh_rate_t RateInfo[D11AC_TXH_NUM_RATES]; /* 20 - 99 */ 917 918 /** Per cache info */ 919 d11actxh_cache_t CacheInfo; /* 100 - 123 */ 920 } rev40; 921 922 /** Rev >= 64 layout */ 923 struct { 924 /** Per cache info */ 925 d11actxh_cache_t CacheInfo; /* 20 - 43 */ 926 927 /** Per rate info */ 928 d11actxh_rate_t RateInfo[D11AC_TXH_NUM_RATES]; /* 44 - 123 */ 929 } rev64; 930 931 }; 932 } BWL_POST_PACKED_STRUCT; 933 934 #define D11AC_TXH_LEN sizeof(d11actxh_t) /* 124 bytes */ 935 936 /* Short format tx descriptor only has per packet info */ 937 #define D11AC_TXH_SHORT_LEN sizeof(d11actxh_pkt_t) /* 20 bytes */ 938 939 /* -TXDC-TxH Excluding Rate Info 41 bytes (Note 1 byte of RATEINFO is removed */ 940 #define D11AC_TXH_SHORT_EXT_LEN (sizeof(d11txh_rev80_t) - 1) 941 942 /* Retry limit regs */ 943 /* Current retries for the fallback rates are hardcoded */ 944 #define D11AC_TXDC_SRL_FB (3u) /* Short Retry Limit - Fallback */ 945 #define D11AC_TXDC_LRL_FB (2u) /* Long Retry Limit - Fallback */ 946 947 #define D11AC_TXDC_RET_LIM_MASK (0x000Fu) 948 #define D11AC_TXDC_SRL_SHIFT (0u) /* Short Retry Limit */ 949 #define D11AC_TXDC_SRL_FB_SHIFT (4u) /* Short Retry Limit - Fallback */ 950 #define D11AC_TXDC_LRL_SHIFT (8u) /* Long Retry Limit */ 951 #define D11AC_TXDC_LRL_FB_SHIFT (12u) /* Long Retry Limit - Fallback */ 952 953 /* MacTxControlLow */ 954 #define D11AC_TXC_HDR_FMT_SHORT 0x0001 /**< 0: long format, 1: short format */ 955 #define D11AC_TXC_UPD_CACHE 0x0002 956 #define D11AC_TXC_CACHE_IDX_MASK 0x003C /**< Cache index 0 .. 15 */ 957 #define D11AC_TXC_CACHE_IDX_SHIFT 2 958 959 #define D11AC_TXDC_IDX_SHIFT 1 960 #define D11AC_TXDC_CPG_SHIFT 5 961 #define D11REV80_TXDC_RIB_CPG 0x0020 /**< Cache Index CPG (Bit 5) -TXDC- */ 962 #define D11REV80_TXDC_RIB_DEL_MASK 0x001E /**< Cache index CIPX 0 .. 15 (Bit 1-4 -TXDC- */ 963 #define D11REV80_TXDC_RIB_IMM_MASK 0x003E /**< Cache index CIPX 0 .. 31 (Bit 1-5) -TXDC- */ 964 #define D11AC_TXC_AMPDU 0x0040 /**< Is aggregate-able */ 965 #define D11AC_TXC_IACK 0x0080 /**< Expect immediate ACK */ 966 #define D11AC_TXC_LFRM 0x0100 /**< Use long/short retry frame count/limit */ 967 #define D11AC_TXC_IPMQ 0x0200 /**< Ignore PMQ */ 968 #define D11AC_TXC_MBURST 0x0400 /**< Burst mode */ 969 #define D11AC_TXC_ASEQ 0x0800 /**< Add ucode generated seq num */ 970 #define D11AC_TXC_AGING 0x1000 /**< Use lifetime */ 971 #define D11AC_TXC_AMIC 0x2000 /**< Compute and add TKIP MIC */ 972 #define D11AC_TXC_STMSDU 0x4000 /**< First MSDU */ 973 #define D11AC_TXC_URIFS 0x8000 /**< Use RIFS */ 974 975 /* MacTxControlHigh */ 976 #define D11AC_TXC_DISFCS 0x0001 /**< Discard FCS */ 977 #define D11AC_TXC_FIX_RATE 0x0002 /**< Use primary rate only */ 978 #define D11AC_TXC_SVHT 0x0004 /**< Single VHT mpdu ampdu */ 979 #define D11AC_TXC_PPS 0x0008 /**< Enable PS Pretend feature */ 980 #define D11AC_TXC_UCODE_SEQ 0x0010 /* Sequence counter for BK traffic, for offloads */ 981 #define D11AC_TXC_TIMBC_TSF 0x0020 /**< Enable TIMBC tsf field present */ 982 #define D11AC_TXC_TCPACK 0x0040 983 #define D11AC_TXC_AWDL_PHYTT 0x0080 /**< Fill in PHY Transmission Time for AWDL action frames */ 984 #define D11AC_TXC_TOF 0x0100 /**< Enable wifi ranging processing for rxd frames */ 985 #define D11AC_TXC_MU 0x0200 /**< MU Tx data */ 986 #define D11AC_TXC_BFIX 0x0800 /**< BFI from SHMx */ 987 #define D11AC_TXC_NORETRY 0x0800 /**< Disable retry for tsync frames */ 988 #define D11AC_TXC_UFP 0x1000 /**< UFP */ 989 #define D11AC_TXC_OVERRIDE_NAV 0x1000 /**< if set, ucode will tx without honoring NAV */ 990 #define D11AC_TXC_DYNBW 0x2000 /**< Dynamic BW */ 991 #define D11AC_TXC_TXPROF_EN 0x8000 /**< TxProfile Enable TODO: support multiple idx */ 992 #define D11AC_TXC_SLTF 0x8000 /**< 11az Secure Ranging frame */ 993 994 #define D11AC_TSTAMP_SHIFT 8 /**< Tstamp in 256us units */ 995 996 /* PhyTxControlWord_0 */ 997 #define D11AC_PHY_TXC_FT_MASK 0x0003 998 999 /* vht txctl0 */ 1000 #define D11AC_PHY_TXC_NON_SOUNDING 0x0004 1001 #define D11AC_PHY_TXC_BFM 0x0008 1002 #define D11AC_PHY_TXC_SHORT_PREAMBLE 0x0010 1003 #define D11AC2_PHY_TXC_STBC 0x0020 1004 #define D11AC_PHY_TXC_ANT_MASK 0x3FC0 1005 #define D11AC_PHY_TXC_CORE_MASK 0x03C0 1006 #define D11AC_PHY_TXC_CORE_SHIFT 6 1007 #define D11AC_PHY_TXC_ANT_IDX_MASK 0x3C00 1008 #define D11AC_PHY_TXC_ANT_IDX_SHIFT 10 1009 #define D11AC_PHY_TXC_BW_MASK 0xC000 1010 #define D11AC_PHY_TXC_BW_SHIFT 14 1011 #define D11AC_PHY_TXC_BW_20MHZ 0x0000 1012 #define D11AC_PHY_TXC_BW_40MHZ 0x4000 1013 #define D11AC_PHY_TXC_BW_80MHZ 0x8000 1014 #define D11AC_PHY_TXC_BW_160MHZ 0xC000 1015 1016 /* PhyTxControlWord_1 */ 1017 #define D11AC_PHY_TXC_PRIM_SUBBAND_MASK 0x0007 1018 #define D11AC_PHY_TXC_PRIM_SUBBAND_LLL 0x0000 1019 #define D11AC_PHY_TXC_PRIM_SUBBAND_LLU 0x0001 1020 #define D11AC_PHY_TXC_PRIM_SUBBAND_LUL 0x0002 1021 #define D11AC_PHY_TXC_PRIM_SUBBAND_LUU 0x0003 1022 #define D11AC_PHY_TXC_PRIM_SUBBAND_ULL 0x0004 1023 #define D11AC_PHY_TXC_PRIM_SUBBAND_ULU 0x0005 1024 #define D11AC_PHY_TXC_PRIM_SUBBAND_UUL 0x0006 1025 #define D11AC_PHY_TXC_PRIM_SUBBAND_UUU 0x0007 1026 #define D11AC_PHY_TXC_TXPWR_OFFSET_MASK 0x01F8 1027 #define D11AC_PHY_TXC_TXPWR_OFFSET_SHIFT 3 1028 #define D11AC2_PHY_TXC_TXPWR_OFFSET_MASK 0x03F8 1029 #define D11AC2_PHY_TXC_TXPWR_OFFSET_SHIFT 3 1030 #define D11AC_PHY_TXC_TXBF_USER_IDX_MASK 0x7C00 1031 #define D11AC_PHY_TXC_TXBF_USER_IDX_SHIFT 10 1032 #define D11AC2_PHY_TXC_DELTA_TXPWR_OFFSET_MASK 0x7C00 1033 #define D11AC2_PHY_TXC_DELTA_TXPWR_OFFSET_SHIFT 10 1034 /* Rather awkward bit mapping to keep pctl1 word same as legacy, for proprietary 11n rate support */ 1035 #define D11AC_PHY_TXC_11N_PROP_MCS 0x8000 /* this represents bit mcs[6] */ 1036 #define D11AC2_PHY_TXC_MU 0x8000 1037 1038 /* PhyTxControlWord_2 phy rate */ 1039 #define D11AC_PHY_TXC_PHY_RATE_MASK 0x003F 1040 #define D11AC2_PHY_TXC_PHY_RATE_MASK 0x007F 1041 1042 /* 11b phy rate */ 1043 #define D11AC_PHY_TXC_11B_PHY_RATE_MASK 0x0003 1044 #define D11AC_PHY_TXC_11B_PHY_RATE_1 0x0000 1045 #define D11AC_PHY_TXC_11B_PHY_RATE_2 0x0001 1046 #define D11AC_PHY_TXC_11B_PHY_RATE_5_5 0x0002 1047 #define D11AC_PHY_TXC_11B_PHY_RATE_11 0x0003 1048 1049 /* 11a/g phy rate */ 1050 #define D11AC_PHY_TXC_11AG_PHY_RATE_MASK 0x0007 1051 #define D11AC_PHY_TXC_11AG_PHY_RATE_6 0x0000 1052 #define D11AC_PHY_TXC_11AG_PHY_RATE_9 0x0001 1053 #define D11AC_PHY_TXC_11AG_PHY_RATE_12 0x0002 1054 #define D11AC_PHY_TXC_11AG_PHY_RATE_18 0x0003 1055 #define D11AC_PHY_TXC_11AG_PHY_RATE_24 0x0004 1056 #define D11AC_PHY_TXC_11AG_PHY_RATE_36 0x0005 1057 #define D11AC_PHY_TXC_11AG_PHY_RATE_48 0x0006 1058 #define D11AC_PHY_TXC_11AG_PHY_RATE_54 0x0007 1059 1060 /* 11ac phy rate */ 1061 #define D11AC_PHY_TXC_11AC_MCS_MASK 0x000F 1062 #define D11AC_PHY_TXC_11AC_NSS_MASK 0x0030 1063 #define D11AC_PHY_TXC_11AC_NSS_SHIFT 4 1064 1065 /* 11n phy rate */ 1066 #define D11AC_PHY_TXC_11N_MCS_MASK 0x003F 1067 #define D11AC2_PHY_TXC_11N_MCS_MASK 0x007F 1068 #define D11AC2_PHY_TXC_11N_PROP_MCS 0x0040 /* this represents bit mcs[6] */ 1069 1070 /* PhyTxControlWord_2 rest */ 1071 #define D11AC_PHY_TXC_STBC 0x0040 1072 #define D11AC_PHY_TXC_DYN_BW_IN_NON_HT_PRESENT 0x0080 1073 #define D11AC_PHY_TXC_DYN_BW_IN_NON_HT_DYNAMIC 0x0100 1074 #define D11AC2_PHY_TXC_TXBF_USER_IDX_MASK 0xFE00 1075 #define D11AC2_PHY_TXC_TXBF_USER_IDX_SHIFT 9 1076 1077 /* RtsCtsControl */ 1078 #define D11AC_RTSCTS_FRM_TYPE_MASK 0x0001 /**< frame type */ 1079 #define D11AC_RTSCTS_FRM_TYPE_11B 0x0000 /**< 11b */ 1080 #define D11AC_RTSCTS_FRM_TYPE_11AG 0x0001 /**< 11a/g */ 1081 #define D11AC_RTSCTS_USE_RTS 0x0004 /**< Use RTS */ 1082 #define D11AC_RTSCTS_USE_CTS 0x0008 /**< Use CTS */ 1083 #define D11AC_RTSCTS_SHORT_PREAMBLE 0x0010 /**< Long/short preamble: 0 - long, 1 - short? */ 1084 #define D11AC_RTSCTS_LAST_RATE 0x0020 /**< this is last rate */ 1085 #define D11AC_RTSCTS_IMBF 0x0040 /**< Implicit TxBF */ 1086 #define D11AC_RTSCTS_MIMOPS_RTS 0x8000 /**< Use RTS for mimops */ 1087 #define D11AC_RTSCTS_DPCU_VALID 0x0080 /**< DPCU Valid : Same bitfield as above */ 1088 #define D11AC_RTSCTS_BF_IDX_MASK 0xF000 /**< 4-bit index to the beamforming block */ 1089 #define D11AC_RTSCTS_BF_IDX_SHIFT 12 1090 #define D11AC_RTSCTS_RATE_MASK 0x0F00 /**< Rate table offset: bit 3-0 of PLCP byte 0 */ 1091 #define D11AC_RTSCTS_USE_RATE_SHIFT 8 1092 1093 /* BssIdEncAlg */ 1094 #define D11AC_BSSID_MASK 0x000F /**< BSS index */ 1095 #define D11AC_BSSID_SHIFT 0 1096 #define D11AC_ENCRYPT_ALG_MASK 0x00F0 /**< Encryption algoritm */ 1097 #define D11AC_ENCRYPT_ALG_SHIFT 4 1098 #define D11AC_ENCRYPT_ALG_NOSEC 0x0000 /**< No security */ 1099 #define D11AC_ENCRYPT_ALG_WEP 0x0010 /**< WEP */ 1100 #define D11AC_ENCRYPT_ALG_TKIP 0x0020 /**< TKIP */ 1101 #define D11AC_ENCRYPT_ALG_AES 0x0030 /**< AES */ 1102 #define D11AC_ENCRYPT_ALG_WEP128 0x0040 /**< WEP128 */ 1103 #define D11AC_ENCRYPT_ALG_NA 0x0050 /**< N/A */ 1104 #define D11AC_ENCRYPT_ALG_WAPI 0x0060 /**< WAPI */ 1105 1106 /* AmpduDur */ 1107 #define D11AC_AMPDU_MIN_DUR_IDX_MASK 0x000F /**< AMPDU minimum duration index */ 1108 #define D11AC_AMPDU_MIN_DUR_IDX_SHIFT 0 1109 #define D11AC_AMPDU_MAX_DUR_MASK 0xFFF0 /**< AMPDU maximum duration in unit 16 usec */ 1110 #define D11AC_AMPDU_MAX_DUR_SHIFT 4 1111 1112 /** 1113 * TX Descriptor definitions for supporting rev80 (HE) 1114 */ 1115 /* Maximum number of TX fallback rates per packet */ 1116 #define D11_REV80_TXH_NUM_RATES 4 1117 #define D11_REV80_TXH_PHYTXCTL_MIN_LENGTH 1 1118 1119 /** per rate info - fixed portion - rev80 */ 1120 typedef struct d11txh_rev80_rate_fixed d11txh_rev80_rate_fixed_t; 1121 BWL_PRE_PACKED_STRUCT struct d11txh_rev80_rate_fixed { 1122 uint16 TxRate; /* rate in 500Kbps */ 1123 uint16 RtsCtsControl; /* RTS - CTS control */ 1124 uint8 plcp[D11_PHY_HDR_LEN]; /* 6 bytes */ 1125 } BWL_POST_PACKED_STRUCT; 1126 1127 /* rev80 specific per packet info fields */ 1128 typedef struct d11pktinfo_rev80 d11pktinfo_rev80_t; 1129 BWL_PRE_PACKED_STRUCT struct d11pktinfo_rev80 { 1130 uint16 HEModeControl; /* 20 */ 1131 uint16 length; /* 22 - length of txd in bytes */ 1132 } BWL_POST_PACKED_STRUCT; 1133 1134 #define D11_REV80_TXH_TX_MODE_SHIFT 0 /* Bits 2:0 of HeModeControl */ 1135 #define D11_REV80_TXH_TX_MODE_MASK 0x3 1136 #define D11_REV80_TXH_HTC_OFFSET_SHIFT 4 /* Bits 8:4 of HeModeControl */ 1137 #define D11_REV80_TXH_HTC_OFFSET_MASK 0x01F0u 1138 #define D11_REV80_TXH_TWT_EOSP 0x0200u /* bit 9 indicate TWT EOSP */ 1139 #define D11_REV80_TXH_QSZ_QOS_CTL_IND_SHIFT 10 /* Bit 10 of HeModeControl */ 1140 #define D11_REV80_TXH_QSZ_QOS_CTL_IND_MASK (1 << D11_REV80_TXH_QSZ_QOS_CTL_IND_SHIFT) 1141 #define D11_REV80_TXH_USE_BSSCOLOR_SHM_SHIFT 15 /* Bit 15 of HEModeControl */ 1142 #define D11_REV80_TXH_USE_BSSCOLOR_SHM_MASK (1 << D11_REV80_TXH_USE_BSSCOLOR_SHM_SHIFT) 1143 1144 /* Calculate Length for short format TXD */ 1145 #define D11_TXH_SHORT_LEN(__corerev__) (D11REV_GE(__corerev__, 80) ? \ 1146 D11_REV80_TXH_SHORT_LEN : \ 1147 D11AC_TXH_SHORT_LEN) 1148 1149 /* Calculate Length for short format TXD (TXDC and/or FMF) */ 1150 #define D11_TXH_SHORT_EX_LEN(__corerev__) (D11REV_GE(__corerev__, 80) ? \ 1151 D11_REV80_TXH_SHORT_EX_LEN : \ 1152 D11AC_TXH_SHORT_LEN) 1153 1154 #define D11_REV80_TXH_IS_HE_AMPDU_SHIFT 11 /* Bit 11 of HeModeControl */ 1155 #define D11_REV80_TXH_IS_HE_AMPDU_MASK (1 << D11_REV80_TXH_IS_HE_AMPDU_SHIFT) 1156 1157 #define D11_REV80_PHY_TXC_EDCA 0x00 1158 #define D11_REV80_PHY_TXC_OFDMA_RA 0x01 /* Use Random Access Trigger for Tx */ 1159 #define D11_REV80_PHY_TXC_OFDMA_DT 0x02 /* Use Directed Trigger for Tx */ 1160 #define D11_REV80_PHY_TXC_OFDMA_ET 0x03 /* Use earliest Trigger Opportunity */ 1161 1162 /** Per cache info - rev80 */ 1163 typedef struct d11txh_rev80_cache d11txh_rev80_cache_t; 1164 BWL_PRE_PACKED_STRUCT struct d11txh_rev80_cache { 1165 d11txh_cache_common_t common; /* 0 - 7 */ 1166 uint16 ampdu_mpdu_all; /* 8 - 9 */ 1167 uint16 aggid; /* 10 - 11 */ 1168 uint8 tkipph1_index; /* 12 */ 1169 uint8 pktext; /* 13 */ 1170 uint16 hebid_map; /* 14 -15: HEB ID bitmap */ 1171 } BWL_POST_PACKED_STRUCT; 1172 1173 /** Fixed size portion of TX descriptor - rev80 */ 1174 typedef struct d11txh_rev80 d11txh_rev80_t; 1175 BWL_PRE_PACKED_STRUCT struct d11txh_rev80 { 1176 /** 1177 * Per pkt info fields (common + rev80 specific) 1178 * 1179 * Note : Ensure that PktInfo field is always the first member 1180 * of the d11txh_rev80 struct (that is at OFFSET - 0) 1181 */ 1182 d11pktinfo_common_t PktInfo; /* 0 - 19 */ 1183 d11pktinfo_rev80_t PktInfoExt; /* 20 - 23 */ 1184 1185 /** Per cache info */ 1186 d11txh_rev80_cache_t CacheInfo; /* 24 - 39 */ 1187 1188 /** 1189 * D11_REV80_TXH_NUM_RATES number of Rate Info blocks 1190 * contribute to the variable size portion of the TXD. 1191 * Each Rate Info element (block) is a funtion of 1192 * (N_PwrOffset, N_RU, N_User). 1193 */ 1194 uint8 RateInfoBlock[1]; 1195 } BWL_POST_PACKED_STRUCT; 1196 1197 /* Size of fixed portion in TX descriptor (without CacheInfo(Link info) and RateInfoBlock) 1198 * this portion never change regardless of TXDC/FMF support. 1199 */ 1200 /* OFFSETOF() is available in bcmutils.h but including it will cause 1201 * recursive inclusion of d11.h specifically on NDIS platforms. 1202 */ 1203 #ifdef BCMFUZZ 1204 /* use 0x10 offset to avoid undefined behavior error due to NULL access */ 1205 #define D11_REV80_TXH_FIXED_LEN (((uint)(uintptr)&((d11txh_rev80_t *)0x10)->CacheInfo) - 0x10) 1206 #else 1207 #define D11_REV80_TXH_FIXED_LEN ((uint)(uintptr)&((d11txh_rev80_t *)0)->CacheInfo) 1208 #endif /* BCMFUZZ */ 1209 1210 /* Short format tx descriptor only has per packet info (24 bytes) */ 1211 #define D11_REV80_TXH_SHORT_LEN (sizeof(d11pktinfo_common_t) + sizeof(d11pktinfo_rev80_t)) 1212 1213 /* Size of CacheInfo(Link info) in TX descriptor */ 1214 #define D11_REV80_TXH_LINK_INFO_LEN (sizeof(d11txh_rev80_cache_t)) 1215 1216 /* Size of Short format TX descriptor 1217 * with TXDC - Short TXD(40 bytes) shall include PktInfo and Cache info without Rate info 1218 * with TXDC+FMF - Short TXD(24 bytes) shall include PktInfo only without Link info and Rate info 1219 * do NOT use D11_REV80_TXH_SHORT_EX_LEN to calculate long TXD length, value depends on FMF feature 1220 */ 1221 #if defined(FMF_LIT) && !defined(FMF_LIT_DISABLED) 1222 #define D11_REV80_TXH_SHORT_EX_LEN D11_REV80_TXH_FIXED_LEN 1223 #else 1224 #define D11_REV80_TXH_SHORT_EX_LEN (D11_REV80_TXH_FIXED_LEN + D11_REV80_TXH_LINK_INFO_LEN) 1225 #endif /* FMF_LIT && !FMF_LIT_DISABLED */ 1226 1227 /* Length of BFM0 field in RateInfo Blk */ 1228 #define D11_REV80_TXH_BFM0_FIXED_LEN(pwr_offs) 2u 1229 1230 /** 1231 * Length of FBWInfo field in RateInfo Blk 1232 * 1233 * Note : for now return fixed length of 1 word 1234 */ 1235 #define D11_REV80_TXH_FBWINFO_FIXED_LEN(pwr_offs) 2 1236 1237 #define D11_REV80_TXH_FIXED_RATEINFO_LEN sizeof(d11txh_rev80_rate_fixed_t) 1238 1239 /** 1240 * Macros to find size of N-RUs field in the PhyTxCtlWord. 1241 */ 1242 #define D11_REV80_TXH_TXC_N_RUs_FIELD_SIZE 1 1243 #define D11_REV80_TXH_TXC_PER_RU_INFO_SIZE 4 1244 #define D11_REV80_TXH_TXC_PER_RU_MIN_SIZE 2 1245 1246 #define D11_REV80_TXH_TXC_RU_FIELD_SIZE(n_rus) ((n_rus == 1) ? \ 1247 (D11_REV80_TXH_TXC_PER_RU_MIN_SIZE) : \ 1248 ((D11_REV80_TXH_TXC_N_RUs_FIELD_SIZE) + \ 1249 ((n_rus) * D11_REV80_TXH_TXC_PER_RU_INFO_SIZE))) 1250 1251 /** 1252 * Macros to find size of N-Users field in the TXCTL_EXT 1253 */ 1254 #define D11_REV80_TXH_TXC_EXT_N_USERs_FIELD_SIZE 1 1255 #define D11_REV80_TXH_TXC_EXT_PER_USER_INFO_SIZE 4 1256 1257 #define D11_REV80_TXH_TXC_N_USERs_FIELD_SIZE(n_users) \ 1258 ((n_users) ? \ 1259 (((n_users) * \ 1260 (D11_REV80_TXH_TXC_EXT_PER_USER_INFO_SIZE)) + \ 1261 (D11_REV80_TXH_TXC_EXT_N_USERs_FIELD_SIZE)) : \ 1262 (n_users)) 1263 1264 /** 1265 * Size of each Tx Power Offset field in PhyTxCtlWord. 1266 */ 1267 #define D11_REV80_TXH_TXC_PWR_OFFSET_SIZE 1u 1268 1269 /** 1270 * Size of fixed / static fields in PhyTxCtlWord (all fields except N-RUs, N-Users and Pwr offsets) 1271 */ 1272 #define D11_REV80_TXH_TXC_CONST_FIELDS_SIZE 6u 1273 1274 /** 1275 * Macros used for filling PhyTxCtlWord 1276 */ 1277 1278 /* PhyTxCtl Byte 0 */ 1279 #define D11_REV80_PHY_TXC_FT_MASK 0x0007u 1280 #define D11_REV80_PHY_TXC_HE_FMT_MASK 0x0018u 1281 #define D11_REV80_PHY_TXC_SOFT_AP_MODE 0x0020u 1282 #define D11_REV80_PHY_TXC_NON_SOUNDING 0x0040u 1283 #define D11_REV80_PHY_TXC_SHORT_PREAMBLE 0x0080u 1284 #define D11_REV80_PHY_TXC_FRAME_TYPE_VHT 0X0003u 1285 #define D11_REV80_PHY_TXC_FRAME_TYPE_HT 0X0002u 1286 #define D11_REV80_PHY_TXC_FRAME_TYPE_LEG 0X0001u 1287 1288 #define D11_REV80_PHY_TXC_HE_FMT_SHIFT 3u 1289 1290 /* PhyTxCtl Byte 1 */ 1291 #define D11_REV80_PHY_TXC_STBC 0x0080u 1292 1293 /* PhyTxCtl Word 1 (Bytes 2 - 3) */ 1294 #define D11_REV80_PHY_TXC_DPCU_SUBBAND_SHIFT 5u 1295 #define D11_REV80_PHY_TXC_DYNBW_PRESENT 0x2000u 1296 #define D11_REV80_PHY_TXC_DYNBW_MODE 0x4000u 1297 #define D11_REV80_PHY_TXC_MU 0x8000u 1298 #define D11_REV80_PHY_TXC_BW_MASK 0x0003u 1299 #define D11_REV80_PHY_TXC_BW_20MHZ 0x0000u 1300 #define D11_REV80_PHY_TXC_BW_40MHZ 0x0001u 1301 #define D11_REV80_PHY_TXC_BW_80MHZ 0x0002u 1302 #define D11_REV80_PHY_TXC_BW_160MHZ 0x0003u 1303 /* PhyTxCtl Word 2 (Bytes 4 -5) */ 1304 /* Though the width antennacfg, coremask fields are 8-bits, 1305 * only 4 bits is valid for 4369a0, hence masking only 4 bits 1306 */ 1307 #define D11_REV80_PHY_TXC_ANT_CONFIG_MASK 0x00F0u 1308 #define D11_REV80_PHY_TXC_CORE_MASK 0x000Fu 1309 #define D11_REV80_PHY_TXC_ANT_CONFIG_SHIFT 4u 1310 /* upper byte- Ant. cfg, lower byte - Core */ 1311 #define D11_REV80_PHY_TXC_ANT_CORE_MASK 0x0F0Fu 1312 1313 /* PhyTxCtl BFM field */ 1314 #define D11_REV80_PHY_TXC_BFM 0x80u 1315 1316 /* PhyTxCtl power offsets */ 1317 #define D11_REV80_PHY_TXC_PWROFS0_BYTE_POS 6u 1318 1319 /* Phytx Ctl Sub band location */ 1320 #define D11_REV80_PHY_TXC_SB_SHIFT 2u 1321 #define D11_REV80_PHY_TXC_SB_MASK 0x001Cu 1322 1323 /* 11n phy rate */ 1324 #define D11_REV80_PHY_TXC_11N_MCS_MASK 0x003Fu 1325 #define D11_REV80_PHY_TXC_11N_PROP_MCS 0x0040u /* this represents bit mcs[6] */ 1326 1327 /* 11ac phy rate */ 1328 #define D11_REV80_PHY_TXC_11AC_NSS_SHIFT 4u 1329 1330 /* PhyTxCtl Word0 */ 1331 #define D11_REV80_PHY_TXC_MCS_NSS_MASK 0x7F00u 1332 #define D11_REV80_PHY_TXC_MCS_MASK 0xF00u 1333 #define D11_REV80_PHY_TXC_MCS_NSS_SHIFT 8u 1334 1335 /* 11ax phy rate */ 1336 #define D11_REV80_PHY_TXC_11AX_NSS_SHIFT 4u 1337 1338 #define D11_PHY_TXC_FT_MASK(corerev) ((D11REV_GE(corerev, 80)) ? D11_REV80_PHY_TXC_FT_MASK : \ 1339 D11AC_PHY_TXC_FT_MASK) 1340 1341 /* PhyTxCtl Word 4 */ 1342 #define D11_REV80_PHY_TXC_HEHL_ENABLE 0x2000u 1343 1344 /* PhyTxCtl Word 5 */ 1345 #define D11_REV80_PHY_TXC_CORE0_PWR_OFFSET_SHIFT 8u 1346 #define D11_REV80_PHY_TXC_CORE0_PWR_OFFSET_MASK 0xFF00u 1347 /* PhyTxCtl Word 6 */ 1348 #define D11_REV80_PHY_TXC_CORE1_PWR_OFFSET_MASK 0x00FFu 1349 /* Number of RU assigned */ 1350 #define D11_REV80_PHY_TXC_NRU 0x0100u 1351 1352 /* A wrapper structure for all versions of TxD/d11txh structures */ 1353 typedef union d11txhdr { 1354 d11txh_pre40_t pre40; 1355 d11actxh_t rev40; 1356 d11txh_rev80_t rev80; 1357 } d11txhdr_t; 1358 1359 /** 1360 * Generic tx status packet for software use. This is independent of hardware 1361 * structure for a particular core. Hardware structure should be read and converted 1362 * to this structure before being sent for the sofware consumption. 1363 */ 1364 typedef struct tx_status tx_status_t; 1365 typedef struct tx_status_macinfo tx_status_macinfo_t; 1366 1367 BWL_PRE_PACKED_STRUCT struct tx_status_macinfo { 1368 int8 pad0; 1369 int8 is_intermediate; 1370 int8 pm_indicated; 1371 int8 pad1; 1372 uint8 suppr_ind; 1373 int8 was_acked; 1374 uint16 rts_tx_cnt; 1375 uint16 frag_tx_cnt; 1376 uint16 cts_rx_cnt; 1377 uint16 raw_bits; 1378 uint32 s3; 1379 uint32 s4; 1380 uint32 s5; 1381 uint32 s8; 1382 uint32 s9; 1383 uint32 s10; 1384 uint32 s11; 1385 uint32 s12; 1386 uint32 s13; 1387 uint32 s14; 1388 /* 128BA support */ 1389 uint16 ncons_ext; 1390 uint16 s15; 1391 uint32 ack_map[8]; 1392 /* pktlat */ 1393 uint16 pkt_fetch_ts; /* PSM Packet Fetch Time */ 1394 uint16 med_acc_dly; /* Medium Access Delay */ 1395 uint16 rx_dur; /* Rx duration */ 1396 uint16 mac_susp_dur; /* Mac Suspend Duration */ 1397 uint16 txstatus_ts; /* TxStatus Time */ 1398 uint16 tx_en_cnt; /* Number of times Tx was enabled */ 1399 uint16 oac_txs_cnt; /* Other AC TxStatus count */ 1400 uint16 data_retx_cnt; /* DataRetry count */ 1401 uint16 pktlat_rsvd; /* reserved */ 1402 } BWL_POST_PACKED_STRUCT; 1403 1404 BWL_PRE_PACKED_STRUCT struct tx_status { 1405 uint16 framelen; 1406 uint16 frameid; 1407 uint16 sequence; 1408 uint16 phyerr; 1409 uint32 lasttxtime; 1410 uint16 ackphyrxsh; 1411 uint16 procflags; /* tx status processing flags */ 1412 uint32 dequeuetime; 1413 tx_status_macinfo_t status; 1414 } BWL_POST_PACKED_STRUCT; 1415 1416 /* Bits in struct tx_status procflags */ 1417 #define TXS_PROCFLAG_AMPDU_BA_PKG2_READ_REQD 0x1 /* AMPDU BA txs pkg2 read required */ 1418 1419 /* status field bit definitions */ 1420 #define TX_STATUS_FRM_RTX_MASK 0xF000 1421 #define TX_STATUS_FRM_RTX_SHIFT 12 1422 #define TX_STATUS_RTS_RTX_MASK 0x0F00 1423 #define TX_STATUS_RTS_RTX_SHIFT 8 1424 #define TX_STATUS_MASK 0x00FE 1425 #define TX_STATUS_PMINDCTD (1 << 7) /**< PM mode indicated to AP */ 1426 #define TX_STATUS_INTERMEDIATE (1 << 6) /**< intermediate or 1st ampdu pkg */ 1427 #define TX_STATUS_AMPDU (1 << 5) /**< AMPDU status */ 1428 #define TX_STATUS_SUPR_MASK 0x1C /**< suppress status bits (4:2) */ 1429 #define TX_STATUS_SUPR_SHIFT 2 1430 #define TX_STATUS_ACK_RCV (1 << 1) /**< ACK received */ 1431 #define TX_STATUS_VALID (1 << 0) /**< Tx status valid (corerev >= 5) */ 1432 #define TX_STATUS_NO_ACK 0 1433 #define TX_STATUS_BE (TX_STATUS_ACK_RCV | TX_STATUS_PMINDCTD) 1434 1435 /* TX_STATUS for fw initiated pktfree event */ 1436 #define TX_STATUS_SW_Q_FLUSH 0x10000 1437 1438 /* status field bit definitions phy rev > 40 */ 1439 #define TX_STATUS40_FIRST 0x0002 1440 #define TX_STATUS40_INTERMEDIATE 0x0004 1441 #define TX_STATUS40_PMINDCTD 0x0008 1442 1443 #define TX_STATUS40_SUPR 0x00f0 1444 #define TX_STATUS40_SUPR_SHIFT 4 1445 1446 #define TX_STATUS40_NCONS 0x7f00 1447 1448 #define TX_STATUS40_NCONS_SHIFT 8 1449 1450 #define TX_STATUS40_ACK_RCV 0x8000 1451 1452 /* tx status bytes 8-16 */ 1453 #define TX_STATUS40_TXCNT_RATE0_MASK 0x000000ff 1454 #define TX_STATUS40_TXCNT_RATE0_SHIFT 0 1455 1456 #define TX_STATUS40_TXCNT_RATE1_MASK 0x00ff0000 1457 #define TX_STATUS40_TXCNT_RATE1_SHIFT 16 1458 1459 #define TX_STATUS40_MEDIUM_DELAY_MASK 0xFFFF 1460 1461 #define TX_STATUS40_TXCNT(s3, s4) \ 1462 (((s3 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT) + \ 1463 ((s3 & TX_STATUS40_TXCNT_RATE1_MASK) >> TX_STATUS40_TXCNT_RATE1_SHIFT) + \ 1464 ((s4 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT) + \ 1465 ((s4 & TX_STATUS40_TXCNT_RATE1_MASK) >> TX_STATUS40_TXCNT_RATE1_SHIFT)) 1466 1467 #define TX_STATUS40_TXCNT_RT0(s3) \ 1468 ((s3 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT) 1469 1470 #define TX_STATUS_EXTBA_TXCNT_BITS 0x3u 1471 #define TX_STATUS_EXTBA_TXSUCCNT_BITS 0x1u 1472 #define TX_STATUS_EXTBA_TXSIZE_RT 0x4u 1473 1474 #define TX_STATUS_EXTBA_TXCNT_RATE_MASK 0x7u 1475 #define TX_STATUS_EXTBA_TXSUCCNT_RATE_MASK 0x8u 1476 1477 #define TX_STATUS_EXTBA_TXCNT_RATE_SHIFT 0x8u 1478 #define TX_STATUS_EXTBA_TXSUCCNT_RATE_SHIFT 0x8u 1479 1480 #define TX_STATUS_EXTBA_TXCNT_RT(s15, rt) \ 1481 ((((s15) & (TX_STATUS_EXTBA_TXCNT_RATE_MASK << ((rt) * TX_STATUS_EXTBA_TXSIZE_RT))) >> \ 1482 ((rt) * TX_STATUS_EXTBA_TXSIZE_RT)) << TX_STATUS_EXTBA_TXCNT_RATE_SHIFT) 1483 1484 #define TX_STATUS_EXTBA_TXSUCCNT_RT(s15, rt) \ 1485 ((((s15) & (TX_STATUS_EXTBA_TXSUCCNT_RATE_MASK << ((rt) * TX_STATUS_EXTBA_TXSIZE_RT))) >> \ 1486 (((rt) * TX_STATUS_EXTBA_TXSIZE_RT))) << TX_STATUS_EXTBA_TXSUCCNT_RATE_SHIFT) 1487 1488 #define TX_STATUS40_TX_MEDIUM_DELAY(txs) ((txs)->status.s8 & TX_STATUS40_MEDIUM_DELAY_MASK) 1489 1490 /* chip rev 40 pkg 2 fields */ 1491 #define TX_STATUS40_IMPBF_MASK 0x0000000Cu /* implicit bf applied */ 1492 #define TX_STATUS40_IMPBF_BAD_MASK 0x00000010u /* impl bf applied but ack frm has no bfm */ 1493 #define TX_STATUS40_IMPBF_LOW_MASK 0x00000020u /* ack received with low rssi */ 1494 #define TX_STATUS40_BFTX 0x00000040u /* Beamformed pkt TXed */ 1495 /* pkt two status field bit definitions mac rev > 64 */ 1496 #define TX_STATUS64_MUTX 0x00000080u /* Not used in STA-dongle chips */ 1497 1498 /* pkt two status field bit definitions mac rev > 80 */ 1499 1500 /* TXS rate cookie contains 1501 * mac rev 81/82 : RIT idx in bit[4:0] of RIB CtrlStat[0] 1502 * mac rev >= 83 : RIB version in bit[4:0] of RIB CtrlStat[1] 1503 */ 1504 #define TX_STATUS80_RATE_COOKIE_MASK 0x00003E00u 1505 #define TX_STATUS80_RATE_COOKIE_SHIFT 9u 1506 #define TX_STATUS80_NAV_HDR 0x00004000u /* NAV Overriden */ 1507 1508 #define TX_STATUS80_TBPPDU_MASK 0x00000040u /* Indicates TBPPDU TX */ 1509 #define TX_STATUS80_TBPPDU_SHIFT 6u 1510 #define TX_STATUS40_RTS_RTX_MASK 0x00ff0000u 1511 #define TX_STATUS40_RTS_RTX_SHIFT 16u 1512 #define TX_STATUS40_CTS_RRX_MASK 0xff000000u 1513 #define TX_STATUS40_CTS_RRX_SHIFT 24u 1514 1515 /* 1516 * Intermediate status for TBPPDU (for stats purposes) 1517 * First uint16 word (word0 - status): VALID, !FIRST, INTERMEDIATE 1518 * Remaining word0 bits (3 - 15) are unasisgned 1519 */ 1520 #define TX_ITBSTATUS(status) \ 1521 (((status) & (TX_STATUS40_FIRST | TX_STATUS40_INTERMEDIATE)) == TX_STATUS40_INTERMEDIATE) 1522 /* Remainder of first uint32 (words 0 and 1) */ 1523 #define TX_ITBSTATUS_LSIG_MASK 0x0000fff0u 1524 #define TX_ITBSTATUS_LSIG_SHIFT 4u 1525 #define TX_ITBSTATUS_TXPOWER_MASK 0xffff0000u 1526 #define TX_ITBSTATUS_TXPOWER_SHIFT 16u 1527 /* Second uint32 (words 2 and 3) */ 1528 #define TX_ITBSTATUS_NULL_DELIMS_MASK 0x0007ffffu /* 19 bits * 4B => ~2M bytes */ 1529 #define TX_ITBSTATUS_NULL_DELIMS_SHIFT 0u 1530 #define TX_ITBSTATUS_ACKED_MPDUS_MASK 0x3ff80000u /* 11 bits: 0-2047 */ 1531 #define TX_ITBSTATUS_ACKED_MPDUS_SHIFT 19u 1532 /* Third uint32 (words 4 and 5) */ 1533 #define TX_ITBSTATUS_SENT_MPDUS_MASK 0x0000ffe0u /* 11 bits: 0-2047 */ 1534 #define TX_ITBSTATUS_SENT_MPDUS_SHIFT 5u 1535 #define TX_ITBSTATUS_APTXPWR_MASK 0x003f0000u /* 0-60 => -20 - 40 */ 1536 #define TX_ITBSTATUS_APTXPWR_SHIFT 16u 1537 #define TX_ITBSTATUS_ULPKTEXT_MASK 0x01c00000u 1538 #define TX_ITBSTATUS_ULPKTEXT_SHIFT 22u 1539 #define TX_ITBSTATUS_MORETF_MASK 0x02000000u 1540 #define TX_ITBSTATUS_MORETF_SHIFT 25u 1541 #define TX_ITBSTATUS_CSREQ_MASK 0x04000000u 1542 #define TX_ITBSTATUS_CSREQ_SHIFT 26u 1543 #define TX_ITBSTATUS_ULBW_MASK 0x18000000u 1544 #define TX_ITBSTATUS_ULBW_SHIFT 27u 1545 #define TX_ITBSTATUS_GI_LTF_MASK 0x60000000u 1546 #define TX_ITBSTATUS_GI_LTF_SHIFT 29u 1547 #define TX_ITBSTATUS_MUMIMO_LTF_MASK 0x80000000u 1548 #define TX_ITBSTATUS_MUMIMO_LTF_SHIFT 30u 1549 /* Fourth uint32 (words 6 and 7) */ 1550 #define TX_ITBSTATUS_CODING_TYPE_MASK 0x00000001u 1551 #define TX_ITBSTATUS_CODING_TYPE_SHIFT 0u 1552 #define TX_ITBSTATUS_MCS_MASK 0x0000001eu 1553 #define TX_ITBSTATUS_MCS_SHIFT 1u 1554 #define TX_ITBSTATUS_DCM_MASK 0x00000020u 1555 #define TX_ITBSTATUS_DCM_SHIFT 5u 1556 #define TX_ITBSTATUS_RU_ALLOC_MASK 0x00003fc0u 1557 #define TX_ITBSTATUS_RU_ALLOC_SHIFT 6u 1558 /* Bits 14 and 15 unassigned */ 1559 #define TX_ITBSTATUS_NSS_MASK 0x00030000u 1560 #define TX_ITBSTATUS_NSS_SHIFT 16u 1561 #define TX_ITBSTATUS_TARGET_RSSI_MASK 0x03fc0000u 1562 #define TX_ITBSTATUS_TARGET_RSSI_SHIFT 18u 1563 #define TX_ITBSTATUS_RA_RU_MASK 0x04000000u 1564 #define TX_ITBSTATUS_RA_RU_SHIFT 26u 1565 /* Bits 27 through 31 unassigned */ 1566 /* End of intermediate TBPPDU txstatus definitions */ 1567 1568 /* MU group info txstatus field (s3 b[31:16]) */ 1569 #define TX_STATUS64_MU_GID_MASK 0x003f0000u 1570 #define TX_STATUS64_MU_GID_SHIFT 16u 1571 #define TX_STATUS64_MU_BW_MASK 0x00c00000u 1572 #define TX_STATUS64_MU_BW_SHIFT 22u 1573 #define TX_STATUS64_MU_TXPWR_MASK 0x7f000000u 1574 #define TX_STATUS64_MU_TXPWR_SHIFT 24u 1575 #define TX_STATUS64_MU_SGI_MASK 0x80000080u 1576 #define TX_STATUS64_MU_SGI_SHIFT 31u 1577 #define TX_STATUS64_INTERM_MUTXCNT(s3) \ 1578 ((s3 & TX_STATUS40_TXCNT_RATE0_MASK) >> TX_STATUS40_TXCNT_RATE0_SHIFT) 1579 1580 #define TX_STATUS64_MU_GID(s3) ((s3 & TX_STATUS64_MU_GID_MASK) >> TX_STATUS64_MU_GID_SHIFT) 1581 #define TX_STATUS64_MU_BW(s3) ((s3 & TX_STATUS64_MU_BW_MASK) >> TX_STATUS64_MU_BW_SHIFT) 1582 #define TX_STATUS64_MU_TXPWR(s3) ((s3 & TX_STATUS64_MU_TXPWR_MASK) >> TX_STATUS64_MU_TXPWR_SHIFT) 1583 #define TX_STATUS64_MU_SGI(s3) ((s3 & TX_STATUS64_MU_SGI_MASK) >> TX_STATUS64_MU_SGI_SHIFT) 1584 1585 /* MU user info0 txstatus field (s4 b[15:0]) */ 1586 #define TX_STATUS64_MU_MCS_MASK 0x0000000f 1587 #define TX_STATUS64_MU_MCS_SHIFT 0 1588 #define TX_STATUS64_MU_NSS_MASK 0x00000070 1589 #define TX_STATUS64_MU_NSS_SHIFT 4 1590 #define TX_STATUS64_MU_SNR_MASK 0x0000ff00 1591 #define TX_STATUS64_MU_SNR_SHIFT 8 1592 1593 #define TX_STATUS64_MU_MCS(s4) ((s4 & TX_STATUS64_MU_MCS_MASK) >> TX_STATUS64_MU_MCS_SHIFT) 1594 #define TX_STATUS64_MU_NSS(s4) ((s4 & TX_STATUS64_MU_NSS_MASK) >> TX_STATUS64_MU_NSS_SHIFT) 1595 #define TX_STATUS64_MU_SNR(s4) ((s4 & TX_STATUS64_MU_SNR_MASK) >> TX_STATUS64_MU_SNR_SHIFT) 1596 1597 /* MU txstatus rspec field (NSS | MCS) */ 1598 #define TX_STATUS64_MU_RSPEC_MASK (TX_STATUS64_MU_NSS_MASK | TX_STATUS64_MU_MCS_MASK) 1599 #define TX_STATUS64_MU_RSPEC_SHIFT 0 1600 1601 #define TX_STATUS64_MU_RSPEC(s4) ((s4 & TX_STATUS64_MU_RSPEC_MASK) >> TX_STATUS64_MU_RSPEC_SHIFT) 1602 1603 /* MU user info0 txstatus field (s4 b[31:16]) */ 1604 #define TX_STATUS64_MU_GBMP_MASK 0x000f0000 1605 #define TX_STATUS64_MU_GBMP_SHIFT 16 1606 #define TX_STATUS64_MU_GPOS_MASK 0x00300000 1607 #define TX_STATUS64_MU_GPOS_SHIFT 20 1608 #define TX_STATUS64_MU_TXCNT_MASK 0x0fc00000 1609 #define TX_STATUS64_MU_TXCNT_SHIFT 22 1610 1611 #define TX_STATUS64_MU_GBMP(s4) ((s4 & TX_STATUS64_MU_GBMP_MASK) >> TX_STATUS64_MU_GBMP_SHIFT) 1612 #define TX_STATUS64_MU_GPOS(s4) ((s4 & TX_STATUS64_MU_GPOS_MASK) >> TX_STATUS64_MU_GPOS_SHIFT) 1613 #define TX_STATUS64_MU_TXCNT(s4) ((s4 & TX_STATUS64_MU_TXCNT_MASK) >> TX_STATUS64_MU_TXCNT_SHIFT) 1614 1615 #define HE_MU_APTX_PWR_MAX 60u 1616 #define HE_TXS_MU_APTX_PWR_DBM(aptx_pwr) ((aptx_pwr) - 20u) 1617 1618 #define HE_TXS_MU_TARGET_RSSI_RANG 90 1619 #define HE_TXS_MU_TARGET_RSSI_MAX_PWR 127 1620 #define HE_TXS_MU_TARGET_RSSI_DBM(rssi) ((rssi) - 110) 1621 1622 #define HE_TXS_W4_MU_GET_RU_INDEX(index) ((index <= HE_MAX_26_TONE_RU_INDX) ? 0u : \ 1623 ((index) <= HE_MAX_52_TONE_RU_INDX) ? 1u : \ 1624 ((index) <= HE_MAX_106_TONE_RU_INDX) ? 2u : \ 1625 ((index) <= HE_MAX_242_TONE_RU_INDX) ? 3u : \ 1626 ((index) <= HE_MAX_484_TONE_RU_INDX) ? 4u :\ 1627 ((index) <= HE_MAX_996_TONE_RU_INDX) ? 5u : 6u) 1628 1629 /* Bit 8 indicates upper 80 MHz */ 1630 #define HE_TXS_W4_MU_RU_INDEX_RU_INDEX_MASK 0x7Fu 1631 #define HE_TXS_W4_MU_RU_INDEX_TONE(index) HE_TXS_W4_MU_GET_RU_INDEX(((index) & \ 1632 HE_TXS_W4_MU_RU_INDEX_RU_INDEX_MASK)) 1633 1634 #define HE_TXS_W3_MU_APTX_PWR_MASK 0x003F0000u 1635 #define HE_TXS_W3_MU_APTX_PWR_SHIFT 16u 1636 #define HE_TXS_W3_MU_PKT_EXT_MASK 0x01C00000u 1637 #define HE_TXS_W3_MU_PKT_EXT_SHIFT 22u 1638 #define HE_TXS_W3_MU_MORE_TF_MASK 0x02000000u 1639 #define HE_TXS_W3_MU_MORE_TF_SHIFT 25u 1640 #define HE_TXS_W3_MU_CS_REQ_MASK 0x04000000u 1641 #define HE_TXS_W3_MU_CS_REQ_SHIFT 26u 1642 #define HE_TXS_W3_MU_UL_BW_MASK 0x18000000u 1643 #define HE_TXS_W3_MU_UL_BW_SHIFT 27u 1644 #define HE_TXS_W3_MU_GI_LTF_MASK 0x60000000u 1645 #define HE_TXS_W3_MU_GI_LTF_SHIFT 29u 1646 #define HE_TXS_W3_MU_MIMO_LTF_MASK 0x80000000u 1647 #define HE_TXS_W3_MU_MIMO_LTF_SHIFT 31u 1648 1649 #define HE_TXS_W3_MU_APTX_PWR(s3) (((s3) & HE_TXS_W3_MU_APTX_PWR_MASK) >> \ 1650 HE_TXS_W3_MU_APTX_PWR_SHIFT) 1651 #define HE_TXS_W3_MU_PKT_EXT(s3) (((s3) & HE_TXS_W3_MU_PKT_EXT_MASK) >> \ 1652 HE_TXS_W3_MU_PKT_EXT_SHIFT) 1653 #define HE_TXS_W3_MU_MORE_TF(s3) (((s3) & HE_TXS_W3_MU_MORE_TF_MASK) >> \ 1654 HE_TXS_W3_MU_MORE_TF_SHIFT) 1655 #define HE_TXS_W3_MU_CS_REQ(s3) (((s3) & HE_TXS_W3_MU_CS_REQ_MASK) >> \ 1656 HE_TXS_W3_MU_CS_REQ_SHIFT) 1657 #define HE_TXS_W3_MU_UL_BW(s3) (((s3) & HE_TXS_W3_MU_UL_BW_MASK) >> \ 1658 HE_TXS_W3_MU_UL_BW_SHIFT) 1659 #define HE_TXS_W3_MU_GI_LTF(s3) (((s3) & HE_TXS_W3_MU_GI_LTF_MASK) >> \ 1660 HE_TXS_W3_MU_GI_LTF_SHIFT) 1661 #define HE_TXS_W3_MU_MIMO_LT(s3) (((s3) & HE_TXS_W3_MU_MIMO_LTF_MASK) >> \ 1662 HE_TXS_W3_MU_MIMO_LTF_SHIFT) 1663 1664 #define HE_TXS_W4_MU_CODINF_TYPE_MASK 0x00000001u 1665 #define HE_TXS_W4_MU_CODINF_TYPE_SHIFT 0u 1666 #define HE_TXS_W4_MU_MCS_MASK 0x0000001Eu 1667 #define HE_TXS_W4_MU_MCS_SHIFT 1u 1668 #define HE_TXS_W4_MU_DCM_MASK 0x00000020u 1669 #define HE_TXS_W4_MU_DCM_SHIFT 5u 1670 #define HE_TXS_W4_RU_ALLOCATION_MASK 0x00003FC0u 1671 #define HE_TXS_W4_RU_ALLOCATION_SHIFT 6u 1672 1673 #define HE_TXS_W4_MU_CODINF_TYPE(s4) (((s4) & HE_TXS_W4_MU_CODINF_TYPE_MASK) >> \ 1674 HE_TXS_W4_MU_CODINF_TYPE_SHIFT) 1675 #define HE_TXS_W4_MU_MCS(s4) (((s4) & HE_TXS_W4_MU_MCS_MASK) >> \ 1676 HE_TXS_W4_MU_MCS_SHIFT) 1677 #define HE_TXS_W4_MU_DCM(s4) (((s4) & HE_TXS_W4_MU_DCM_MASK) >> \ 1678 HE_TXS_W4_MU_DCM_SHIFT) 1679 #define HE_TXS_W4_RU_ALLOCATION(s4) (((s4) & HE_TXS_W4_RU_ALLOCATION_MASK) >> \ 1680 HE_TXS_W4_RU_ALLOCATION_SHIFT) 1681 1682 #define HE_TXS_W4_MU_NSS_MASK 0x00030000u 1683 #define HE_TXS_W4_MU_NSS_SHIFT 16u 1684 #define HE_TXS_W4_MU_TARGET_RSSI_MASK 0x03FC0000u 1685 #define HE_TXS_W4_MU_TARGET_RSSI_SHIFT 18u 1686 1687 #define HE_TXS_W4_MU_NSS(s4) (((s4) & HE_TXS_W4_MU_NSS_MASK) >> \ 1688 HE_TXS_W4_MU_NSS_SHIFT) 1689 #define HE_TXS_W4_MU_TARGET_RSSI(s4) (((s4) & HE_TXS_W4_MU_TARGET_RSSI_MASK) >> \ 1690 HE_TXS_W4_MU_TARGET_RSSI_SHIFT) 1691 1692 /* WARNING: Modifying suppress reason codes? 1693 * Update wlc_tx_status_t and TX_STS_REASON_STRINGS and 1694 * wlc_tx_status_map_hw_to_sw_supr_code() also 1695 */ 1696 /* status field bit definitions */ 1697 /** suppress status reason codes */ 1698 enum { 1699 TX_STATUS_SUPR_NONE = 0, 1700 TX_STATUS_SUPR_PMQ = 1, /**< PMQ entry */ 1701 TX_STATUS_SUPR_FLUSH = 2, /**< flush request */ 1702 TX_STATUS_SUPR_FRAG = 3, /**< previous frag failure */ 1703 TX_STATUS_SUPR_TBTT = 3, /**< SHARED: Probe response supr for TBTT */ 1704 TX_STATUS_SUPR_BADCH = 4, /**< channel mismatch */ 1705 TX_STATUS_SUPR_EXPTIME = 5, /**< lifetime expiry */ 1706 TX_STATUS_SUPR_UF = 6, /**< underflow */ 1707 #ifdef WLP2P_UCODE 1708 TX_STATUS_SUPR_NACK_ABS = 7, /**< BSS entered ABSENCE period */ 1709 #endif 1710 TX_STATUS_SUPR_PPS = 8, /**< Pretend PS */ 1711 TX_STATUS_SUPR_PHASE1_KEY = 9, /**< Request new TKIP phase-1 key */ 1712 TX_STATUS_UNUSED = 10, /**< Unused in trunk */ 1713 TX_STATUS_INT_XFER_ERR = 11, /**< Internal DMA xfer error */ 1714 TX_STATUS_SUPR_TWT_SP_OUT = 12, /**< Suppress Tx outside TWTSP */ 1715 NUM_TX_STATUS_SUPR 1716 }; 1717 1718 /** Unexpected tx status for rate update */ 1719 #define TX_STATUS_UNEXP(status) \ 1720 ((((status.is_intermediate))) && \ 1721 TX_STATUS_UNEXP_AMPDU(status)) 1722 1723 /** Unexpected tx status for A-MPDU rate update */ 1724 #ifdef WLP2P_UCODE 1725 #define TX_STATUS_UNEXP_AMPDU(status) \ 1726 ((((status.suppr_ind)) != TX_STATUS_SUPR_NONE) && \ 1727 (((status.suppr_ind)) != TX_STATUS_SUPR_EXPTIME) && \ 1728 (((status.suppr_ind)) != TX_STATUS_SUPR_NACK_ABS)) 1729 #else 1730 #define TX_STATUS_UNEXP_AMPDU(status) \ 1731 ((((status.suppr_ind)) != TX_STATUS_SUPR_NONE) && \ 1732 (((status.suppr_ind)) != TX_STATUS_SUPR_EXPTIME)) 1733 #endif 1734 1735 /** 1736 * This defines the collection of supp reasons (including none) 1737 * for which mac has done its (re-)transmission in any of ucode retx schemes 1738 * which include ucode/hw/aqm agg 1739 */ 1740 #define TXS_SUPR_MAGG_DONE_MASK ((1 << TX_STATUS_SUPR_NONE) | \ 1741 (1 << TX_STATUS_SUPR_UF) | \ 1742 (1 << TX_STATUS_SUPR_FRAG) | \ 1743 (1 << TX_STATUS_SUPR_EXPTIME)) 1744 #define TXS_SUPR_MAGG_DONE(suppr_ind) \ 1745 ((1 << (suppr_ind)) & TXS_SUPR_MAGG_DONE_MASK) 1746 1747 #define TX_STATUS_BA_BMAP03_MASK 0xF000 /**< ba bitmap 0:3 in 1st pkg */ 1748 #define TX_STATUS_BA_BMAP03_SHIFT 12 /**< ba bitmap 0:3 in 1st pkg */ 1749 #define TX_STATUS_BA_BMAP47_MASK 0x001E /**< ba bitmap 4:7 in 2nd pkg */ 1750 #define TX_STATUS_BA_BMAP47_SHIFT 3 /**< ba bitmap 4:7 in 2nd pkg */ 1751 1752 /* RXE (Receive Engine) */ 1753 1754 /* RCM_CTL */ 1755 #define RCM_INC_MASK_H 0x0080 1756 #define RCM_INC_MASK_L 0x0040 1757 #define RCM_INC_DATA 0x0020 1758 #define RCM_INDEX_MASK 0x001F 1759 #define RCM_SIZE 15 1760 1761 #define RCM_MAC_OFFSET 0 /**< current MAC address */ 1762 #define RCM_BSSID_OFFSET 3 /**< current BSSID address */ 1763 #define RCM_F_BSSID_0_OFFSET 6 /**< foreign BSS CFP tracking */ 1764 #define RCM_F_BSSID_1_OFFSET 9 /**< foreign BSS CFP tracking */ 1765 #define RCM_F_BSSID_2_OFFSET 12 /**< foreign BSS CFP tracking */ 1766 1767 #define RCM_WEP_TA0_OFFSET 16 1768 #define RCM_WEP_TA1_OFFSET 19 1769 #define RCM_WEP_TA2_OFFSET 22 1770 #define RCM_WEP_TA3_OFFSET 25 1771 1772 /* AMT - Address Match Table */ 1773 1774 /* AMT Attribute bits */ 1775 #define AMT_ATTR_VALID 0x8000 /**< Mark the table entry valid */ 1776 #define AMT_ATTR_A1 0x0008 /**< Match for A1 */ 1777 #define AMT_ATTR_A2 0x0004 /**< Match for A2 */ 1778 #define AMT_ATTR_A3 0x0002 /**< Match for A3 */ 1779 1780 /* AMT Index defines */ 1781 #define AMT_SIZE_64 64 /* number of AMT entries */ 1782 #define AMT_SIZE_128 128 /* number of AMT entries for corerev >= 64 */ 1783 #define AMT_IDX_MAC 63 /**< device MAC */ 1784 #define AMT_IDX_BSSID 62 /**< BSSID match */ 1785 #define AMT_IDX_TRANSMITTED_BSSID 60 /**< transmitted BSSID in multiple BSSID set */ 1786 #define AMT_WORD_CNT 2 /* Number of word count per AMT entry */ 1787 1788 #define AMT_SIZE(_corerev) (D11REV_GE(_corerev, 64) ? \ 1789 (D11REV_GE(_corerev, 80) ? AMT_SIZE_64 : AMT_SIZE_128) : \ 1790 AMT_SIZE_64) 1791 1792 /* RMC entries */ 1793 #define AMT_IDX_MCAST_ADDR 61 /**< MCAST address for Reliable Mcast feature */ 1794 #define AMT_IDX_MCAST_ADDR1 59 /**< MCAST address for Reliable Mcast feature */ 1795 #define AMT_IDX_MCAST_ADDR2 58 /**< MCAST address for Reliable Mcast feature */ 1796 #define AMT_IDX_MCAST_ADDR3 57 /**< MCAST address for Reliable Mcast feature */ 1797 1798 #ifdef WLMESH 1799 /* note: this is max supported by ucode. But ARM-driver can 1800 * only mesh_info->mesh_max_peers which should be <= this value. 1801 */ 1802 1803 #define AMT_MAX_MESH_PEER 10 1804 #define AMT_MAXIDX_MESH_PEER 60 1805 #define AMT_MAXIDX_P2P_USE \ 1806 (AMT_MAXIDX_MESH_PEER - AMT_MAX_MESH_PEER) 1807 #else 1808 #define AMT_MAXIDX_P2P_USE 60 /**< Max P2P entry to use */ 1809 #endif /* WL_STA_MONITOR */ 1810 #define AMT_MAX_TXBF_ENTRIES 7 /**< Max tx beamforming entry */ 1811 /* PSTA AWARE AP: Max PSTA Tx beamforming entry */ 1812 #define AMT_MAX_TXBF_PSTA_ENTRIES 20 1813 1814 /* M_AMT_INFO SHM bit field definition */ 1815 #define AMTINFO_BMP_IBSS (1u << 0u) /* IBSS Station */ 1816 #define AMTINFO_BMP_MESH (1u << 1u) /* MESH Station */ 1817 #define AMTINFO_BMP_BSSID (1u << 2u) /* BSSID-only */ 1818 #define AMTINFO_BMP_IS_WAPI (1u << 3u) /* For WAPI keyid extraction */ 1819 #define AMTINFO_BMP_IS_HE (1u << 13u) /* For HE peer indication */ 1820 1821 #define AUXPMQ_ENTRIES 64 /* number of AUX PMQ entries */ 1822 #define AUXPMQ_ENTRY_SIZE 8 1823 1824 /* PSM Block */ 1825 1826 /* psm_phy_hdr_param bits */ 1827 #define MAC_PHY_RESET 1 1828 #define MAC_PHY_CLOCK_EN 2 1829 #define MAC_PHY_FORCE_CLK 4 1830 #define MAC_IHRP_CLOCK_EN 15 1831 1832 /* PSMCoreControlStatus (IHR Address 0x078) bit definitions */ 1833 #define PSM_CORE_CTL_AR (1 << 0) 1834 #define PSM_CORE_CTL_HR (1 << 1) 1835 #define PSM_CORE_CTL_IR (1 << 2) 1836 #define PSM_CORE_CTL_AAR (1 << 3) 1837 #define PSM_CORE_CTL_HAR (1 << 4) 1838 #define PSM_CORE_CTL_PPAR (1 << 5) 1839 #define PSM_CORE_CTL_SS (1 << 6) 1840 #define PSM_CORE_CTL_REHE (1 << 7) 1841 #define PSM_CORE_CTL_PPAS (1 << 13) 1842 #define PSM_CORE_CTL_AAS (1 << 14) 1843 #define PSM_CORE_CTL_HAS (1 << 15) 1844 1845 #define PSM_CORE_CTL_LTR_BIT 9 1846 #define PSM_CORE_CTL_LTR_MASK 0x3 1847 1848 #define PSM_SBACCESS_FIFO_MODE (1 << 1) 1849 #define PSM_SBACCESS_EXT_ERR (1 << 11) 1850 1851 /* WEP Block */ 1852 1853 /* WEP_WKEY */ 1854 #define WKEY_START (1 << 8) 1855 #define WKEY_SEL_MASK 0x1F 1856 1857 /* WEP data formats */ 1858 1859 /* the number of RCMTA entries */ 1860 #define RCMTA_SIZE 50 1861 1862 /* max keys in M_TKMICKEYS_BLK - 96 * sizeof(uint16) */ 1863 #define WSEC_MAX_TKMIC_ENGINE_KEYS(_corerev) ((D11REV_GE(_corerev, 64)) ? \ 1864 AMT_SIZE(_corerev) : 12) /* 8 + 4 default - 2 mic keys 8 bytes each */ 1865 1866 /* max keys in M_WAPIMICKEYS_BLK - 64 * sizeof(uint16) */ 1867 #define WSEC_MAX_SMS4MIC_ENGINE_KEYS(_corerev) ((D11REV_GE(_corerev, 64)) ? \ 1868 AMT_SIZE(_corerev) : 8) /* 4 + 4 default - 16 bytes each */ 1869 1870 /* max RXE match registers */ 1871 #define WSEC_MAX_RXE_KEYS 4 1872 1873 /* SECKINDXALGO (Security Key Index & Algorithm Block) word format */ 1874 /* SKL (Security Key Lookup) */ 1875 #define SKL_POST80_ALGO_MASK 0x000F 1876 #define SKL_PRE80_ALGO_MASK 0x0007 1877 #define SKL_ALGO_SHIFT 0 1878 1879 #define SKL_ALGO_MASK(_corerev) (D11REV_GE(_corerev, 80) ? SKL_POST80_ALGO_MASK : \ 1880 SKL_PRE80_ALGO_MASK) 1881 1882 #define SKL_WAPI_KEYID_MASK 0x8000 1883 #define SKL_WAPI_KEYID_SHIFT 15 1884 #define SKL_INDEX_SHIFT 4 1885 1886 #define SKL_PRE80_WAPI_KEYID_MASK 0x0008 1887 #define SKL_PRE80_WAPI_KEYID_SHIFT 3 1888 1889 #define SKL_INDEX_MASK(_corerev) ((D11REV_GE(_corerev, 64)) ? \ 1890 (0x0FF0) : (0x03F0)) 1891 #define SKL_GRP_ALGO_MASK(_corerev) ((D11REV_GE(_corerev, 64)) ? \ 1892 ((D11REV_GE(_corerev, 80)) ? (0xE000) : (0x7000)) : (0x1c00)) 1893 #define SKL_GRP_ALGO_SHIFT(_corerev) ((D11REV_GE(_corerev, 64)) ? \ 1894 ((D11REV_GE(_corerev, 80)) ? (13) : (12)) : (10)) 1895 1896 #define SKL_STAMON_NBIT 0x8000 /* STA monitor bit */ 1897 1898 /* additional bits defined for IBSS group key support */ 1899 #define SKL_IBSS_INDEX_MASK 0x01F0 1900 #define SKL_IBSS_INDEX_SHIFT 4 1901 #define SKL_IBSS_KEYID1_MASK 0x0600 1902 #define SKL_IBSS_KEYID1_SHIFT 9 1903 #define SKL_IBSS_KEYID2_MASK 0x1800 1904 #define SKL_IBSS_KEYID2_SHIFT 11 1905 #define SKL_IBSS_KEYALGO_MASK 0xE000 1906 #define SKL_IBSS_KEYALGO_SHIFT 13 1907 1908 #define WSEC_MODE_OFF 0 1909 #define WSEC_MODE_HW 1 1910 #define WSEC_MODE_SW 2 1911 1912 /* Mapped as per HW_ALGO */ 1913 #define WSEC_ALGO_OFF 0 1914 #define WSEC_ALGO_WEP1 1 1915 #define WSEC_ALGO_TKIP 2 1916 #define WSEC_ALGO_WEP128 3 1917 #define WSEC_ALGO_AES_LEGACY 4 1918 #define WSEC_ALGO_AES 5 1919 #define WSEC_ALGO_SMS4 6 1920 #define WSEC_ALGO_SMS4_DFT_2005_09_07 7 /**< Not used right now */ 1921 #define WSEC_ALGO_NALG 8 1922 1923 /* For CORE_REV 80 */ 1924 #define WSEC_ALGO_AES_GCM 8 1925 #define WSEC_ALGO_AES_GCM256 9 1926 1927 /* For CORE_REV Less than 80 and */ 1928 #define WSEC_ALGO_AES_PRE80_GCM 6 1929 #define WSEC_ALGO_AES_PRE80_GCM256 8 1930 1931 /* D11 MAX TTAK INDEX */ 1932 #define TSC_TTAK_PRE80_MAX_INDEX 50 1933 #define TSC_TTAK_MAX_INDEX 8 1934 /* D11 COREREV 80 TTAK KEY INDEX SHIFT */ 1935 #define SKL_TTAK_INDEX_SHIFT 13 1936 #define SKL_TTAK_INDEX_MASK 0xE000 1937 1938 /* D11 PRECOREREV 40 Hw algos...changed from corerev 40 */ 1939 #define D11_PRE40_WSEC_ALGO_AES 3 1940 #define D11_PRE40_WSEC_ALGO_WEP128 4 1941 #define D11_PRE40_WSEC_ALGO_AES_LEGACY 5 1942 #define D11_PRE40_WSEC_ALGO_SMS4 6 1943 #define D11_PRE40_WSEC_ALGO_NALG 7 1944 1945 #define D11_WSEC_ALGO_AES(_corerev) WSEC_ALGO_AES 1946 1947 #define AES_MODE_NONE 0 1948 #define AES_MODE_CCM 1 1949 #define AES_MODE_OCB_MSDU 2 1950 #define AES_MODE_OCB_MPDU 3 1951 #define AES_MODE_CMAC 4 1952 #define AES_MODE_GCM 5 1953 #define AES_MODE_GMAC 6 1954 1955 /* WEP_CTL (Rev 0) */ 1956 #define WECR0_KEYREG_SHIFT 0 1957 #define WECR0_KEYREG_MASK 0x7 1958 #define WECR0_DECRYPT (1 << 3) 1959 #define WECR0_IVINLINE (1 << 4) 1960 #define WECR0_WEPALG_SHIFT 5 1961 #define WECR0_WEPALG_MASK (0x7 << 5) 1962 #define WECR0_WKEYSEL_SHIFT 8 1963 #define WECR0_WKEYSEL_MASK (0x7 << 8) 1964 #define WECR0_WKEYSTART (1 << 11) 1965 #define WECR0_WEPINIT (1 << 14) 1966 #define WECR0_ICVERR (1 << 15) 1967 1968 /* Frame template map byte offsets */ 1969 #define T_ACTS_TPL_BASE (0) 1970 #define T_NULL_TPL_BASE (0xc * 2) 1971 #define T_QNULL_TPL_BASE (0x1c * 2) 1972 #define T_RR_TPL_BASE (0x2c * 2) 1973 #define T_BCN0_TPL_BASE (0x34 * 2) 1974 #define T_PRS_TPL_BASE (0x134 * 2) 1975 #define T_BCN1_TPL_BASE (0x234 * 2) 1976 #define T_P2P_NULL_TPL_BASE (0x340 * 2) 1977 #define T_P2P_NULL_TPL_SIZE (32) 1978 #define T_TRIG_TPL_BASE (0x90 * 2) 1979 1980 /* FCBS base addresses and sizes in BM */ 1981 1982 #define FCBS_DS0_BM_CMD_SZ_CORE0 0x0200 /* 512 bytes */ 1983 #define FCBS_DS0_BM_DAT_SZ_CORE0 0x0200 /* 512 bytes */ 1984 1985 #ifndef FCBS_DS0_BM_CMDPTR_BASE_CORE0 1986 #define FCBS_DS0_BM_CMDPTR_BASE_CORE0 0x3000 1987 #endif 1988 #define FCBS_DS0_BM_DATPTR_BASE_CORE0 (FCBS_DS0_BM_CMDPTR_BASE_CORE0 + FCBS_DS0_BM_CMD_SZ_CORE0) 1989 1990 #define FCBS_DS0_BM_CMD_SZ_CORE1 0x0200 /* 512 bytes */ 1991 #define FCBS_DS0_BM_DAT_SZ_CORE1 0x0200 /* 512 bytes */ 1992 1993 #ifndef FCBS_DS0_BM_CMDPTR_BASE_CORE1 1994 #define FCBS_DS0_BM_CMDPTR_BASE_CORE1 0x2400 1995 #endif 1996 #define FCBS_DS0_BM_DATPTR_BASE_CORE1 (FCBS_DS0_BM_CMDPTR_BASE_CORE1 + FCBS_DS0_BM_CMD_SZ_CORE1) 1997 1998 #define FCBS_DS0_BM_CMD_SZ_CORE2 0x0200 /* 512 bytes */ 1999 #define FCBS_DS0_BM_DAT_SZ_CORE2 0x0200 /* 512 bytes */ 2000 2001 #define FCBS_DS1_BM_CMD_SZ_CORE0 0x2000 /* Not used */ 2002 #define FCBS_DS1_BM_DAT_SZ_CORE0 0x2000 /* Not used */ 2003 2004 #define FCBS_DS1_BM_CMDPTR_BASE_CORE0 0x17B4 2005 #define FCBS_DS1_BM_DATPTR_BASE_CORE0 (FCBS_DS1_BM_CMDPTR_BASE_CORE0 + FCBS_DS1_BM_CMD_SZ_CORE0) 2006 2007 #define FCBS_DS1_BM_CMD_SZ_CORE1 0x2000 /* Not used */ 2008 #define FCBS_DS1_BM_DAT_SZ_CORE1 0x2000 /* Not used */ 2009 2010 #define FCBS_DS1_BM_CMDPTR_BASE_CORE1 0x17B4 2011 #define FCBS_DS1_BM_DATPTR_BASE_CORE1 (FCBS_DS1_BM_CMDPTR_BASE_CORE1 + FCBS_DS1_BM_CMD_SZ_CORE1) 2012 2013 #define T_BA_TPL_BASE T_QNULL_TPL_BASE /**< template area for BA */ 2014 2015 #define T_RAM_ACCESS_SZ 4 /**< template ram is 4 byte access only */ 2016 2017 #define TPLBLKS_PER_BCN_NUM 2 2018 #define TPLBLKS_AC_PER_BCN_NUM 1 2019 2020 #if defined(WLLPRS) && defined(MBSS) 2021 #define TPLBLKS_PER_PRS_NUM 4 2022 #define TPLBLKS_AC_PER_PRS_NUM 2 2023 #else 2024 #define TPLBLKS_PER_PRS_NUM 2 2025 #define TPLBLKS_AC_PER_PRS_NUM 1 2026 #endif /* WLLPRS && MBSS */ 2027 2028 /* MAC Sample Collect Params */ 2029 2030 /* SampleCapture set-up options in 2031 * different registers based on CoreRev 2032 */ 2033 /* CoreRev >= 50, use SMP_CTRL in TXE_IHR */ 2034 #define SC_SRC_MAC 2 /* MAC as Sample Collect Src */ 2035 #define SC_SRC_SHIFT 3 /* SC_SRC bits [3:4] */ 2036 #define SC_TRIG_SHIFT 5 2037 #define SC_TRANS_SHIFT 6 2038 #define SC_MATCH_SHIFT 7 2039 #define SC_STORE_SHIFT 8 2040 2041 #define SC_STRT 1 2042 #define SC_TRIG_EN (1 << SC_TRIG_SHIFT) 2043 #define SC_TRANS_EN (1 << SC_TRANS_SHIFT) 2044 #define SC_MATCH_EN (1 << SC_MATCH_SHIFT) 2045 #define SC_STORE_EN (1 << SC_STORE_SHIFT) 2046 2047 /* CoreRev < 50, use PHY_CTL in PSM_IHR */ 2048 #define PHYCTL_PHYCLKEN (1 << 1) 2049 #define PHYCTL_FORCE_GATED_CLK_ON (1 << 2) 2050 #define PHYCTL_SC_STRT (1 << 4) 2051 #define PHYCTL_SC_SRC_LB (1 << 7) 2052 #define PHYCTL_SC_TRIG_EN (1 << 8) 2053 #define PHYCTL_SC_TRANS_EN (1 << 9) 2054 #define PHYCTL_SC_STR_EN (1 << 10) 2055 #define PHYCTL_IHRP_CLK_EN (1 << 15) 2056 /* End MAC Sample Collect Params */ 2057 2058 #define ANTSEL_CLKDIV_4MHZ 6 2059 #define MIMO_ANTSEL_BUSY 0x4000 /**< bit 14 (busy) */ 2060 #define MIMO_ANTSEL_SEL 0x8000 /**< bit 15 write the value */ 2061 #define MIMO_ANTSEL_WAIT 50 /**< 50us wait */ 2062 #define MIMO_ANTSEL_OVERRIDE 0x8000 /**< flag */ 2063 2064 typedef struct shm_acparams shm_acparams_t; 2065 BWL_PRE_PACKED_STRUCT struct shm_acparams { 2066 uint16 txop; 2067 uint16 cwmin; 2068 uint16 cwmax; 2069 uint16 cwcur; 2070 uint16 aifs; 2071 uint16 bslots; 2072 uint16 reggap; 2073 uint16 status; 2074 uint16 txcnt; 2075 uint16 rsvd[7]; 2076 } BWL_POST_PACKED_STRUCT; 2077 2078 #define WME_STATUS_NEWAC (1 << 8) 2079 2080 /* M_HOST_FLAGS */ 2081 #define MHFMAX 5 /* Number of valid hostflag half-word (uint16) */ 2082 #define MHF1 0 /* Hostflag 1 index */ 2083 #define MHF2 1 /* Hostflag 2 index */ 2084 #define MHF3 2 /* Hostflag 3 index */ 2085 #define MHF4 3 /* Hostflag 4 index */ 2086 #define MHF5 4 /* Hostflag 5 index */ 2087 2088 #define MXHFMAX 1 /* Number of valid PSMx hostflag half-word (uint16) */ 2089 #define MXHF0 64 /* PSMx Hostflag 0 index */ 2090 2091 /* Flags in M_HOST_FLAGS */ 2092 #define MHF1_D11AC_DYNBW 0x0001 /**< dynamic bw */ 2093 #define MHF1_WLAN_CRITICAL 0x0002 /**< WLAN is in critical state */ 2094 #define MHF1_MBSS_EN 0x0004 /**< Enable MBSS: RXPUWAR deprecated for rev >= 9 */ 2095 #define MHF1_BTCOEXIST 0x0010 /**< Enable Bluetooth / WLAN coexistence */ 2096 #define MHF1_P2P_SKIP_TIME_UPD 0x0020 /**< Skip P2P SHM updates and P2P event generations */ 2097 #define MHF1_TXMUTE_WAR 0x0040 /**< ucode based Tx mute */ 2098 #define MHF1_RXFIFO1 0x0080 /**< Switch data reception from RX fifo 0 to fifo 1 */ 2099 #define MHF1_EDCF 0x0100 /**< Enable EDCF access control */ 2100 #define MHF1_ULP 0x0200 /**< Force Ucode to put chip in low power state */ 2101 #define MHF1_FORCE_SEND_BCN 0x0800 /**< Force send bcn, even if rcvd from peer STA (IBSS) */ 2102 #define MHF1_TIMBC_EN 0x1000 /**< Enable Target TIM Transmission Time function */ 2103 #define MHF1_RADARWAR 0x2000 /**< Enable Radar Detect WAR PR 16559 */ 2104 #define MHF1_DEFKEYVALID 0x4000 /**< Enable use of the default keys */ 2105 #define MHF1_CTS2SELF 0x8000 /**< Enable CTS to self full phy bw protection */ 2106 2107 /* Flags in M_HOST_FLAGS2 */ 2108 #define MHF2_DISABLE_PRB_RESP 0x0001 /**< disable Probe Response in ucode */ 2109 #define MHF2_HIB_FEATURE_ENABLE 0x0008 /* Enable HIB feature in ucode (60<=rev<80) */ 2110 #define MHF2_SKIP_ADJTSF 0x0010 /**< skip TSF update when receiving bcn/probeRsp */ 2111 #define MHF2_RSPBW20 0x0020 /**< Uses bw20 for response frames ack/ba/cts */ 2112 #define MHF2_TXBCMC_NOW 0x0040 /**< Flush BCMC FIFO immediately */ 2113 #define MHF2_PPR_HWPWRCTL 0x0080 /**< TSSI_DIV WAR (rev<80) */ 2114 #define MHF2_BTC2WIRE_ALTGPIO 0x0100 /**< BTC 2wire in alternate pins */ 2115 #define MHF2_BTCPREMPT 0x0200 /**< BTC enable bluetooth check during tx */ 2116 #define MHF2_SKIP_CFP_UPDATE 0x0400 /**< Skip CFP update ; for d11 rev <= 80 */ 2117 #define MHF2_TX_TMSTMP 0x0800 /**< Enable passing tx-timestamps in tx-status */ 2118 #define MHF2_UFC_GE84 0x2000 /**< Enable UFC in CT mode */ 2119 #define MHF2_NAV_NORST_WAR 0x4000 /**< WAR to use rogue NAV duration */ 2120 #define MHF2_BTCANTMODE 0x4000 // OBSOLETE (TO BE REMOVED) 2121 2122 /* Flags in M_HOST_FLAGS3 */ 2123 #define MHF3_ANTSEL_EN 0x0001 /**< enabled mimo antenna selection (REV<80) */ 2124 #define MHF3_TKIP_FRAG_WAR 0x0001 /**< TKIP fragment corrupt WAR (REV>=80) */ 2125 #define MHF3_TXSHAPER_EN 0x0002 /** enable tx shaper for non-OFDM-A frames */ 2126 #define MHF3_ANTSEL_MODE 0x0002 /**< antenna selection mode: 0: 2x3, 1: 2x4 (REV<80) */ 2127 #define MHF3_BTCX_DEF_BT 0x0004 /**< corerev >= 13 BT Coex. */ 2128 #define MHF3_BTCX_ACTIVE_PROT 0x0008 /**< corerev >= 13 BT Coex. */ 2129 #define MHF3_PKTENG_PROMISC 0x0010 /**< pass frames to driver in packet engine Rx mode */ 2130 #define MHF3_SCANCORE_PM_EN 0x0040 /**< enable ScanCore PM from ucode */ 2131 #define MHF3_PM_BCNRX 0x0080 /**< PM single core beacon RX for power reduction */ 2132 #define MHF3_BTCX_SIM_RSP 0x0100 /**< allow limited lwo power tx when BT is active */ 2133 #define MHF3_BTCX_PS_PROTECT 0x0200 /**< use PS mode to protect BT activity */ 2134 #define MHF3_BTCX_SIM_TX_LP 0x0400 /**< use low power for simultaneous tx responses */ 2135 #define MHF3_SELECT_RXF1 0x0800 /**< enable frame classification in pcie FD */ 2136 #define MHF3_BTCX_ECI 0x1000 /**< Enable BTCX ECI interface */ 2137 #define MHF3_NOISECAL_ENHANCE 0x2000 2138 2139 /* Flags in M_HOST_FLAGS4 */ 2140 #define MHF4_RCMTA_BSSID_EN 0x0002 /**< BTAMP: multiSta BSSIDs matching in RCMTA area */ 2141 #define MHF4_SC_MIX_EN 0x0002 /**< set to enable 4389a0 specific changes */ 2142 #define MHF4_BCN_ROT_RR 0x0004 /**< MBSSID: beacon rotate in round-robin fashion */ 2143 #define MHF4_OPT_SLEEP 0x0008 /**< enable opportunistic sleep (REV<80) */ 2144 #define MHF4_PM_OFFLOAD 0x0008 /**< enable PM offload */ 2145 #define MHF4_PROXY_STA 0x0010 /**< enable proxy-STA feature */ 2146 #define MHF4_AGING 0x0020 /**< Enable aging threshold for RF awareness */ 2147 #define MHF4_STOP_BA_ON_NDP 0x0080 /**< Stop BlockAck to AP to get chance to send NULL data */ 2148 #define MHF4_NOPHYHANGWAR 0x0100 /**< disable ucode WAR for idletssi cal (rev=61) */ 2149 #define MHF4_WMAC_ACKTMOUT 0x0200 /**< reserved for WMAC testing */ 2150 #define MHF4_NAPPING_ENABLE 0x0400 /**< Napping enable (REV<80) */ 2151 #define MHF4_IBSS_SEC 0x0800 /**< IBSS WPA2-PSK operating mode */ 2152 #define MHF4_SISO_BCMC_RX 0x1000 /* Disable switch to MIMO on recving multicast TIM */ 2153 #define MHF4_RSDB_CR1_MINIPMU_CAL_EN 0x8000 /* for 4349B0. JIRA:SW4349-1469 */ 2154 2155 /* Flags in M_HOST_FLAGS5 */ 2156 #define MHF5_BTCX_LIGHT 0x0002 /**< light coex mode, off txpu only for critical BT */ 2157 #define MHF5_BTCX_PARALLEL 0x0004 /**< BT and WLAN run in parallel. */ 2158 #define MHF5_BTCX_DEFANT 0x0008 /**< default position for shared antenna */ 2159 #define MHF5_P2P_MODE 0x0010 /**< Enable P2P mode */ 2160 #define MHF5_LEGACY_PRS 0x0020 /**< Enable legacy probe resp support */ 2161 #define MHF5_HWRSSI_EN 0x0800 /**< Enable HW RSSI (ac) */ 2162 #define MHF5_HIBERNATE 0x1000 /**< Force ucode to power save until wake-bit */ 2163 #define MHF5_BTCX_GPIO_DEBUG 0x4000 /**< Enable gpio pins for btcoex ECI signals */ 2164 #define MHF5_SUPPRESS_PRB_REQ 0x8000 /**< Suppress probe requests at ucode level */ 2165 2166 /* Flags in M_HOST_FLAGS6 */ 2167 #define MHF6_TXPWRCAP_RST_EN 0x0001 /** < Ucode clear phyreg after each tx */ 2168 #define MHF6_TXPWRCAP_EN 0x0002 /** < Enable TX power capping in ucode */ 2169 #define MHF6_TSYNC_AVB 0x0004 /** Enable AVB for timestamping */ 2170 #define MHF6_TSYNC_3PKG 0x0020 /** < Enable 3rd txstatus package */ 2171 #define MHF6_TDMTX 0x0040 /** < Enable SDB TDM in ucode */ 2172 #define MHF6_TSYNC_NODEEPSLP 0x0080 /** < Disable deep sleep to keep AVB clock */ 2173 #define MHF6_TSYNC_CAL 0x0100 /** < Enable Tsync cal in ucode */ 2174 #define MHF6_TXPWRCAP_IOS_NBIT 0x0200 /** < Enable IOS mode of operation for Txpwrcap (REV>=80) */ 2175 #define MHF6_MULBSSID_NBIT 0x0400 /** < associated to AP belonging to a multiple BSSID set */ 2176 #define MHF6_HEBCN_TX_NBIT 0x0800 /** < HE BCN-TX */ 2177 #define MHF6_LATENCY_EN 0x2000 /** < Enable Latency instrumentation in ucode */ 2178 #define MHF6_PTMSTS_EN 0x4000 /** < Enable PTM Status */ 2179 2180 /* MX_HOST_FLAGS */ 2181 /* Flags for MX_HOST_FLAGS0 */ 2182 #define MXHF0_RSV0 0x0001 /* ucode internal, not exposed yet */ 2183 #define MXHF0_TXDRATE 0x0002 /* mu txrate to use rate from txd */ 2184 #define MXHF0_CHKFID 0x0004 /* check if frameid->fifo matches hw txfifo idx */ 2185 #define MXHF0_DISWAR 0x0008 /* disable some WAR. */ 2186 2187 /* M_AXC_HOST_FLAGS0 */ 2188 #define MAXCHF0_WAIT_TRIG 0x0001 /* Hold frames till trigger frame is rxed */ 2189 #define MAXCHF0_HTC_SUPPORT 0x0002 /* 11AX HTC field support */ 2190 #define MAXCHF0_AX_ASSOC_SHIFT 0x0003 /* 11AX association indicator */ 2191 #define MAXCHF0_HEB_CONFIG 0x0004 /* HEB configuration */ 2192 #define MAXCHF0_ACI_DET 0x0008 /* ACI detect soft enable */ 2193 #define MAXCHF0_TRIGRES_LP 0x0010 /* Lite-Point testing */ 2194 #define MAXCHF0_HDRCONV_SHIFT 5u /* Enable header conversion */ 2195 #define MAXCHF0_HDRCONV (1 << MAXCHF0_HDRCONV_SHIFT) 2196 #define MAXCHF0_FORCE_ZERO_PPR_SHIFT 6u /* Force PPR value to 0 for ULTPC */ 2197 #define MAXCHF0_FORCE_ZERO_PPR (1 << MAXCHF0_FORCE_ZERO_PPR_SHIFT) 2198 #define MAXCHF0_DISABLE_PYLDECWAR_SHIFT 7u /* Disable WAR for Paydecode issue */ 2199 #define MAXCHF0_DISABLE_PYLDECWAR (1 << MAXCHF0_DISABLE_PYLDECWAR_SHIFT) 2200 #define MAXCHF0_BSR_SUPPORT_SHIFT 8u /* BSR is supported */ 2201 #define MAXCHF0_BSR_SUPPORT (1 << MAXCHF0_BSR_SUPPORT_SHIFT) 2202 #define MAXCHF0_MUEDCA_VALID_SHIFT 9u /* MUEDCA information is valid */ 2203 #define MAXCHF0_MUEDCA_VALID (1 << MAXCHF0_MUEDCA_VALID_SHIFT) 2204 /* Bit 10 definition missing? */ 2205 #define MAXCHF0_TWT_PKTSUPP_SHIFT 11u /* Enable pkt suppress outside TWT SP */ 2206 #define MAXCHF0_TWT_PKTSUPP_EN (1 << MAXCHF0_TWT_PKTSUPP_SHIFT) 2207 #define MAXCHF0_TBPPDU_STATUS_SHIFT 12u 2208 #define MAXCHF0_TBPPDU_STATUS_EN (1 << MAXCHF0_TBPPDU_STATUS_SHIFT) 2209 #define MAXCHF0_11AX_TXSTATUS_EXT_SHIFT 13u /* Enable 128 BA pkg in TX status */ 2210 #define MAXCHF0_11AX_TXSTATUS_EXT_EN (1u << MAXCHF0_11AX_TXSTATUS_EXT_SHIFT) 2211 #define MAXCHF1_11AX_TXSTATUS_EXT_SHIFT 0u /* Enable 256 BA pkg in TX status */ 2212 #define MAXCHF1_11AX_TXSTATUS_EXT_EN (1u << MAXCHF1_11AX_TXSTATUS_EXT_SHIFT) 2213 /* Bit 14 for UORA_EN */ 2214 #define MAXCHF0_11AX_UORA_SHIFT 14u /* Enable UORA support */ 2215 #define MAXCHF0_11AX_UORA_EN (1u << MAXCHF0_11AX_UORA_SHIFT) 2216 2217 /* M_AXC_HOST_FLAGS1 */ 2218 #define MAXCHF1_ITXSTATUS_EN 0x0004u /* Enable intermediate txs for TB PPDU */ 2219 #define MAXCHF1_OBSSHWSTATS_EN 0x0008u /* Enable ucode OBSS stats monitoring */ 2220 2221 /* M_SC_HOST_FLAGS */ 2222 #define C_SCCX_STATS_EN 0x0001u /* Enable SC stats */ 2223 #define C_SC_BTMC_COEX_EN 0x0002u /* Enable WLSC-BTMC coex */ 2224 2225 /** Short version of receive frame status. Only used for non-last MSDU of AMSDU - rev61.1 */ 2226 typedef struct d11rxhdrshort_rev61_1 d11rxhdrshort_rev61_1_t; 2227 BWL_PRE_PACKED_STRUCT struct d11rxhdrshort_rev61_1 { 2228 uint16 RxFrameSize; /**< Actual byte length of the frame data received */ 2229 2230 /* These two 8-bit fields remain in the same order regardless of 2231 * processor byte order. 2232 */ 2233 uint8 dma_flags; /**< bit 0 indicates short or long rx status. 1 == short. */ 2234 uint8 fifo; /**< rx fifo number */ 2235 uint16 mrxs; /**< MAC Rx Status */ 2236 uint16 RxFrameSize0; /**< rxframesize for fifo-0 (in bytes). */ 2237 uint16 HdrConvSt; /**< hdr conversion status. Copy of ihr(RCV_HDR_CTLSTS). */ 2238 uint16 RxTSFTimeL; /**< RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */ 2239 uint16 RxTSFTimeH; /**< RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */ 2240 uint16 aux_status; /**< DMA writes into this field. ucode treats as reserved. */ 2241 } BWL_POST_PACKED_STRUCT; 2242 2243 /** Short version of receive frame status. Only used for non-last MSDU of AMSDU - pre80 */ 2244 typedef struct d11rxhdrshort_lt80 d11rxhdrshort_lt80_t; 2245 BWL_PRE_PACKED_STRUCT struct d11rxhdrshort_lt80 { 2246 uint16 RxFrameSize; /**< Actual byte length of the frame data received */ 2247 2248 /* These two 8-bit fields remain in the same order regardless of 2249 * processor byte order. 2250 */ 2251 uint8 dma_flags; /**< bit 0 indicates short or long rx status. 1 == short. */ 2252 uint8 fifo; /**< rx fifo number */ 2253 uint16 mrxs; /**< MAC Rx Status */ 2254 uint16 RxTSFTime; /**< RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY */ 2255 uint16 HdrConvSt; /**< hdr conversion status. Copy of ihr(RCV_HDR_CTLSTS). */ 2256 uint16 aux_status; /**< DMA writes into this field. ucode treats as reserved. */ 2257 } BWL_POST_PACKED_STRUCT; 2258 2259 /* Errflag bits for ge80 */ 2260 #define ERRFLAGS_ERR_STATE 0x0003u 2261 #define ERRFLAGS_GREATER_MSDU_LEN 0x0001u 2262 #define ERRFLAGS_AMSDU_TRUNCATED 0x0002u 2263 #define ERRFLAGS_HDRCONV_MASK 0x00F0u 2264 #define ERRFLAGS_HDRCONV_SHIFT 4u 2265 #define ERRFLAGS_CSI_LEN_64K 0x0100u 2266 #define ERRFLAGS_MESH_FMT_ERR 0x0200u 2267 2268 /* Register 'D11_RXE_ERRVAL' bits for ge80 */ 2269 #define RXEERR_GREATER_MSDU_LEN (1u << 6) 2270 2271 /* 128 BA configuration */ 2272 /* Register D11_TXBA_DataSel bits for ge80 */ 2273 #define TXBA_DATASEL_WSIZE_BITMAP_LEN_ENC_SEL (1u << 0u) 2274 2275 /* Register D11_TXBA_Data bits (ge80) */ 2276 #define TXBA_DATA_WSIZE_256 (0x100u) 2277 #define TXBA_DATA_WSIZE_128 (0x80u) 2278 #define TXBA_DATA_WSIZE_64 (0x40u) 2279 2280 /* HW optimisation to generate bitmap based on start SSN & max SSN */ 2281 #define TXBA_DATA_HW_CONST (0xfu << 12) 2282 2283 /* Register D11_RXE_BA_LEN bits (ge80) */ 2284 #define RXE_BA_LEN_RXBA_64 (0x0u) 2285 #define RXE_BA_LEN_RXBA_128 (0x1u) 2286 #define RXE_BA_LEN_RXBA_256 (0x2u) 2287 #define RXE_BA_LEN_TID0_SHIFT (0u) 2288 #define RXE_BA_LEN_TID1_SHIFT (2u) 2289 #define RXE_BA_LEN_TID2_SHIFT (4u) 2290 #define RXE_BA_LEN_TID3_SHIFT (6u) 2291 #define RXE_BA_LEN_TID4_SHIFT (8u) 2292 #define RXE_BA_LEN_TID5_SHIFT (10u) 2293 #define RXE_BA_LEN_TID6_SHIFT (12u) 2294 #define RXE_BA_LEN_TID7_SHIFT (14u) 2295 2296 /* Register D11_RXE_BA_LEN_ENC bits (ge80) */ 2297 #define RXE_BA_LEN_ENC_BA32_VAL (0x3u << 0u) 2298 #define RXE_BA_LEN_ENC_BA64_VAL (0x0u << 2u) 2299 #define RXE_BA_LEN_ENC_BA128_VAL (0x1u << 4u) 2300 #define RXE_BA_LEN_ENC_BA256_VAL (0x2u << 6u) 2301 2302 /* Register D11_RXE_TXBA_CTL2 (ge80) */ 2303 #define RXE_TXBA_CTL2_CONIG_SINGLE_TID (0x0u << 0u) 2304 #define RXE_TXBA_CTL2_CONIG_ALL_TID (0x1u << 0u) 2305 #define RXE_TXBA_CTL2_SEL_TID0 (0x0u << 12u) 2306 #define RXE_TXBA_CTL2_SEL_TID1 (0x1u << 12u) 2307 #define RXE_TXBA_CTL2_SEL_TID2 (0x2u << 12u) 2308 #define RXE_TXBA_CTL2_SEL_TID3 (0x3u << 12u) 2309 #define RXE_TXBA_CTL2_SEL_TID4 (0x4u << 12u) 2310 #define RXE_TXBA_CTL2_SEL_TID5 (0x5u << 12u) 2311 #define RXE_TXBA_CTL2_SEL_TID6 (0x6u << 12u) 2312 #define RXE_TXBA_CTL2_SEL_TID7 (0x7u << 12u) 2313 2314 /** 2315 * Special Notes 2316 * #1: dma_flags, fifo 2317 * These two 8-bit fields remain in the same order regardless of 2318 * processor byte order. 2319 * #2: pktclass 2320 * 16 bit bitmap is a result of Packet (or Flow ) Classification. 2321 * 2322 * 0 : Flow ID Different 2323 * 1,2,3 : A1, A2, A3 Different 2324 * 4 : TID Different 2325 * 5, 6 : DA, SA from AMSDU SubFrame Different 2326 * 7 : FC Different 2327 * 8 : AMPDU boundary 2328 * 9 - 15 : Reserved 2329 * #3: errflags 2330 * These bits indicate specific errors detected by the HW on the Rx Path. 2331 * However, these will be relevant for Last MSDU Status only. 2332 * 2333 * Whenever there is an error at any MSDU, HW treats it as last 2334 * MSDU and send out last MSDU status. 2335 */ 2336 2337 #define D11RXHDR_HW_STATUS_GE80 \ 2338 uint16 RxFrameSize; /**< Actual byte length of the frame data received */ \ 2339 /* For comments see special note #1 above */\ 2340 uint8 dma_flags; /**< bit 0 indicates short or long rx status. 1 == short. */ \ 2341 uint8 fifo; /**< rx fifo number */ \ 2342 \ 2343 uint16 mrxs; /**< MAC Rx Status */ \ 2344 uint16 RxFrameSize0; /**< rxframesize for fifo-0 (in bytes). */ \ 2345 uint16 HdrConvSt; /**< hdr conversion status. Copy of ihr(RCV_HDR_CTLSTS). */ \ 2346 uint16 pktclass; \ 2347 uint32 filtermap; /**< 32 bit bitmap indicates which "Filters" have matched. */ \ 2348 /* For comments see special note #2 above */ \ 2349 uint16 flowid; /**< result of Flow ID Look Up performed by the HW. */ \ 2350 /* For comments see special note #3 above */\ 2351 uint16 errflags; 2352 2353 #define D11RXHDR_UCODE_STATUS_GE80 \ 2354 /**< Ucode Generated Status (16 Bytes) */ \ 2355 uint16 RxStatus1; /**< MAC Rx Status */ \ 2356 uint16 RxStatus2; /**< extended MAC Rx status */ \ 2357 uint16 RxChan; /**< Rx channel info or chanspec */ \ 2358 uint16 AvbRxTimeL; /**< AVB RX timestamp low16 */ \ 2359 uint16 AvbRxTimeH; /**< AVB RX timestamp high16 */ \ 2360 uint16 RxTSFTime; /**< Lower 16 bits of Rx timestamp */ \ 2361 uint16 RxTsfTimeH; /**< Higher 16 bits of Rx timestamp */ \ 2362 uint16 MuRate; /**< MU rate info (bit3:0 MCS, bit6:4 NSTS) */ 2363 2364 #define D11RXHDR_HW_STATUS_GE87_1 /**< HW Generated 24 bytes RX Status */ \ 2365 D11RXHDR_HW_STATUS_GE80 /**< First 20 bytes are same as mac rev >= 80 */ \ 2366 uint16 roe_hw_sts; /**< ROE HW status */ \ 2367 uint16 roe_err_flags; /**< ROE error flags */ 2368 2369 #define D11RXHDR_UCODE_STATUS_GE87_1 /**< Ucode Generated Status (22 Bytes) */ \ 2370 uint16 RxStatus1; /**< MAC Rx Status */ \ 2371 uint16 RxStatus2; /**< extended MAC Rx status */ \ 2372 uint16 RxChan; /**< Rx channel info or chanspec */ \ 2373 uint16 MuRate; /**< MU rate info (bit3:0 MCS, bit6:4 NSTS) */ \ 2374 uint32 AVBRxTime; /**< 32 bit AVB timestamp */ \ 2375 uint32 TSFRxTime; /**< 32 bit TSF timestamp */ \ 2376 uint64 PTMRxTime; /**< 64 bit PTM timestamp */ 2377 2378 /**< HW Generated Status (20 Bytes) */ 2379 /** Short version of receive frame status. Only used for non-last MSDU of AMSDU - rev80 */ 2380 typedef struct d11rxhdrshort_ge87_1 d11rxhdrshort_ge87_1_t; 2381 BWL_PRE_PACKED_STRUCT struct d11rxhdrshort_ge87_1 { 2382 2383 D11RXHDR_HW_STATUS_GE87_1 2384 2385 } BWL_POST_PACKED_STRUCT; 2386 2387 /** Mid version of receive frame status. Only used for MPDU of AMPDU - rev80 */ 2388 typedef struct d11rxhdrmid_ge87_1 d11rxhdrmid_ge87_1_t; 2389 BWL_PRE_PACKED_STRUCT struct d11rxhdrmid_ge87_1 { 2390 2391 D11RXHDR_HW_STATUS_GE87_1 2392 D11RXHDR_UCODE_STATUS_GE87_1 2393 } BWL_POST_PACKED_STRUCT; 2394 2395 /** Short version of receive frame status. Only used for non-last MSDU of AMSDU - rev80 */ 2396 typedef struct d11rxhdrshort_ge80 d11rxhdrshort_ge80_t; 2397 BWL_PRE_PACKED_STRUCT struct d11rxhdrshort_ge80 { 2398 2399 D11RXHDR_HW_STATUS_GE80 2400 2401 } BWL_POST_PACKED_STRUCT; 2402 2403 /** Mid version of receive frame status. Only used for MPDU of AMPDU - rev80 */ 2404 typedef struct d11rxhdrmid_ge80 d11rxhdrmid_ge80_t; 2405 BWL_PRE_PACKED_STRUCT struct d11rxhdrmid_ge80 { 2406 2407 D11RXHDR_HW_STATUS_GE80 2408 D11RXHDR_UCODE_STATUS_GE80 2409 2410 } BWL_POST_PACKED_STRUCT; 2411 2412 /** Receive Frame Data Header - pre80 */ 2413 typedef struct d11rxhdr_lt80 d11rxhdr_lt80_t; 2414 BWL_PRE_PACKED_STRUCT struct d11rxhdr_lt80 { 2415 uint16 RxFrameSize; /**< Actual byte length of the frame data received */ 2416 2417 /** 2418 * These two 8-bit fields remain in the same order regardless of 2419 * processor byte order. 2420 */ 2421 uint8 dma_flags; /* bit 0 indicates short or long rx status. 1 == short. */ 2422 uint8 fifo; /* rx fifo number */ 2423 2424 uint16 PhyRxStatus_0; /**< PhyRxStatus 15:0 */ 2425 uint16 PhyRxStatus_1; /**< PhyRxStatus 31:16 */ 2426 uint16 PhyRxStatus_2; /**< PhyRxStatus 47:32 */ 2427 uint16 PhyRxStatus_3; /**< PhyRxStatus 63:48 */ 2428 uint16 PhyRxStatus_4; /**< PhyRxStatus 79:64 */ 2429 uint16 PhyRxStatus_5; /**< PhyRxStatus 95:80 */ 2430 uint16 RxStatus1; /**< MAC Rx Status */ 2431 uint16 RxStatus2; /**< extended MAC Rx status */ 2432 2433 /** 2434 * - RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY 2435 */ 2436 uint16 RxTSFTime; 2437 2438 uint16 RxChan; /**< Rx channel info or chanspec */ 2439 uint16 RxFrameSize0; /**< size of rx-frame in fifo-0 in case frame is copied to fifo-1 */ 2440 uint16 HdrConvSt; /**< hdr conversion status. Copy of ihr(RCV_HDR_CTLSTS). */ 2441 uint16 AvbRxTimeL; /**< AVB RX timestamp low16 */ 2442 uint16 AvbRxTimeH; /**< AVB RX timestamp high16 */ 2443 uint16 MuRate; /**< MU rate info (bit3:0 MCS, bit6:4 NSTS) */ 2444 /** 2445 * These bits indicate specific errors detected by the HW on the Rx Path. 2446 * However, these will be relevant for Last MSDU Status only. 2447 * 2448 * Whenever there is an error at any MSDU, HW treats it as last 2449 * MSDU and send out last MSDU status. 2450 */ 2451 uint16 errflags; 2452 } BWL_POST_PACKED_STRUCT; 2453 2454 #define N_PRXS_GE80 16 /* Total number of PhyRx status words for corerev >= 80 */ 2455 #define N_PRXS_LT80 6 /* Total number of PhyRx status words for corerev < 80 */ 2456 2457 /* number of PhyRx status words newly added for (corerev >= 80) */ 2458 #define N_PRXS_REM_GE80 (N_PRXS_GE80 - N_PRXS_LT80) 2459 2460 /** RX Hdr definition - rev80 */ 2461 typedef struct d11rxhdr_ge80 d11rxhdr_ge80_t; 2462 BWL_PRE_PACKED_STRUCT struct d11rxhdr_ge80 { 2463 /** 2464 * Even though rxhdr can be in short or long format, always declare it here 2465 * to be in long format. So the offsets for the other fields are always the same. 2466 */ 2467 2468 /**< HW Generated Status (20 Bytes) */ 2469 D11RXHDR_HW_STATUS_GE80 2470 D11RXHDR_UCODE_STATUS_GE80 2471 2472 /**< PHY Generated Status (32 Bytes) */ 2473 uint16 PhyRxStatus_0; /**< PhyRxStatus 15:0 */ 2474 uint16 PhyRxStatus_1; /**< PhyRxStatus 31:16 */ 2475 uint16 PhyRxStatus_2; /**< PhyRxStatus 47:32 */ 2476 uint16 PhyRxStatus_3; /**< PhyRxStatus 63:48 */ 2477 uint16 PhyRxStatus_4; /**< PhyRxStatus 79:64 */ 2478 uint16 PhyRxStatus_5; /**< PhyRxStatus 95:80 */ 2479 uint16 phyrxs_rem[N_PRXS_REM_GE80]; /**< 20 bytes of remaining prxs (corerev >= 80) */ 2480 /* Currently only 6 words are being pushed out of uCode: 6, 9, 16, 17, 21, 23 */ 2481 } BWL_POST_PACKED_STRUCT; 2482 2483 #define N_PRXS_GE85 32u // total number of PhyRxStatus BYTEs for rev >= 85 2484 2485 typedef struct d11rxhdr_ge87_1 d11rxhdr_ge87_1_t; 2486 BWL_PRE_PACKED_STRUCT struct d11rxhdr_ge87_1 { 2487 /** 2488 * Even though rxhdr can be in short or long format, always declare it here 2489 * to be in long format. So the offsets for the other fields are always the same. 2490 */ 2491 2492 D11RXHDR_HW_STATUS_GE87_1 /**< HW Generated Status (24 Bytes) */ 2493 D11RXHDR_UCODE_STATUS_GE87_1 /**< uCode Generated Status (24 Bytes) */ 2494 uint8 PHYRXSTATUS[N_PRXS_GE85]; /**< PHY Generated Status (32 Bytes) */ 2495 } BWL_POST_PACKED_STRUCT; 2496 2497 /* A wrapper structure for all versions of d11rxh short structures */ 2498 typedef struct d11rxhdr_ge85 d11rxhdr_ge85_t; 2499 BWL_PRE_PACKED_STRUCT struct d11rxhdr_ge85 { 2500 /** 2501 * Even though rxhdr can be in short or long format, always declare it here 2502 * to be in long format. So the offsets for the other fields are always the same. 2503 */ 2504 2505 /**< HW Generated Status (20 Bytes) */ 2506 D11RXHDR_HW_STATUS_GE80 2507 D11RXHDR_UCODE_STATUS_GE80 2508 2509 /**< PHY Generated Status (32 Bytes) */ 2510 uint8 PHYRXSTATUS[N_PRXS_GE85]; 2511 } BWL_POST_PACKED_STRUCT; 2512 2513 /* A wrapper structure for all versions of d11rxh short structures */ 2514 typedef union d11rxhdrshort { 2515 d11rxhdrshort_rev61_1_t rev61_1; 2516 d11rxhdrshort_lt80_t lt80; 2517 d11rxhdrshort_ge80_t ge80; 2518 d11rxhdrshort_ge87_1_t ge87_1; 2519 } d11rxhdrshort_t; 2520 2521 /* A wrapper structure for all versions of d11rxh mid structures */ 2522 typedef union d11rxhdrmid { 2523 d11rxhdrmid_ge80_t ge80; 2524 d11rxhdrmid_ge87_1_t ge87_1; 2525 } d11rxhdrmid_t; 2526 2527 /* A wrapper structure for all versions of d11rxh structures */ 2528 typedef union d11rxhdr { 2529 d11rxhdr_lt80_t lt80; 2530 d11rxhdr_ge80_t ge80; 2531 d11rxhdr_ge85_t ge85; 2532 d11rxhdr_ge87_1_t ge87_1; 2533 } d11rxhdr_t; 2534 2535 #define D11RXHDRSHORT_GE87_1_ACCESS_REF(srxh, member) \ 2536 (&((((d11rxhdrshort_t *)(srxh))->ge87_1).member)) 2537 2538 #define D11RXHDRMID_GE87_1_ACCESS_REF(mrxh, member) \ 2539 (&((((d11rxhdrmid_t *)(mrxh))->ge87_1).member)) 2540 2541 #define D11RXHDRSHORT_GE87_1_ACCESS_VAL(srxh, member) \ 2542 ((((d11rxhdrshort_t *)(srxh))->ge87_1).member) 2543 2544 #define D11RXHDRMID_GE87_1_ACCESS_VAL(mrxh, member) \ 2545 ((((d11rxhdrmid_t *)(mrxh))->ge87_1).member) 2546 2547 #define D11RXHDR_GE87_1_ACCESS_REF(rxh, member) \ 2548 (&((rxh)->ge87_1).member) 2549 2550 #define D11RXHDR_GE87_1_ACCESS_VAL(rxh, member) \ 2551 (((rxh)->ge87_1).member) 2552 2553 #define D11RXHDR_GE87_1_SET_VAL(rxh, member, value) \ 2554 (((rxh)->ge87_1).member = value) 2555 2556 #define D11RXHDRSHORT_GE80_ACCESS_REF(srxh, member) \ 2557 (&((((d11rxhdrshort_t *)(srxh))->ge80).member)) 2558 2559 #define D11RXHDRMID_GE80_ACCESS_REF(mrxh, member) \ 2560 (&((((d11rxhdrmid_t *)(mrxh))->ge80).member)) 2561 2562 #define D11RXHDRSHORT_LT80_ACCESS_REF(srxh, member) \ 2563 (&((((d11rxhdrshort_t *)(srxh))->lt80).member)) 2564 2565 #define D11RXHDRSHORT_GE80_ACCESS_VAL(srxh, member) \ 2566 ((((d11rxhdrshort_t *)(srxh))->ge80).member) 2567 2568 #define D11RXHDRMID_GE80_ACCESS_VAL(mrxh, member) \ 2569 ((((d11rxhdrmid_t *)(mrxh))->ge80).member) 2570 2571 #define D11RXHDRSHORT_LT80_ACCESS_VAL(srxh, member) \ 2572 ((((d11rxhdrshort_t *)(srxh))->lt80).member) 2573 2574 #define D11RXHDR_GE80_ACCESS_REF(rxh, member) \ 2575 (&((rxh)->ge80).member) 2576 2577 #define D11RXHDR_LT80_ACCESS_REF(rxh, member) \ 2578 (&((rxh)->lt80).member) 2579 2580 #define D11RXHDR_GE80_ACCESS_VAL(rxh, member) \ 2581 (((rxh)->ge80).member) 2582 2583 #define D11RXHDR_GE80_SET_VAL(rxh, member, value) \ 2584 (((rxh)->ge80).member = value) 2585 2586 #define D11RXHDR_LT80_ACCESS_VAL(rxh, member) \ 2587 (((rxh)->lt80).member) 2588 2589 #define D11RXHDR_LT80_SET_VAL(rxh, member, value) \ 2590 (((rxh)->lt80).member = value) 2591 2592 /** For accessing members of d11rxhdrshort_t by reference (address of members) */ 2593 #define D11RXHDRSHORT_ACCESS_REF(srxh, corerev, corerev_minor, member) \ 2594 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2595 D11RXHDRSHORT_GE87_1_ACCESS_REF(srxh, member) : \ 2596 D11REV_GE(corerev, 80) ? D11RXHDRSHORT_GE80_ACCESS_REF(srxh, member) : \ 2597 D11RXHDRSHORT_LT80_ACCESS_REF(srxh, member)) 2598 2599 /** For accessing members of d11rxhdrshort_t by value (only value stored inside members accessed) */ 2600 #define D11RXHDRSHORT_ACCESS_VAL(srxh, corerev, corerev_minor, member) \ 2601 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2602 D11RXHDRSHORT_GE87_1_ACCESS_VAL(srxh, member) : \ 2603 D11REV_GE(corerev, 80) ? D11RXHDRSHORT_GE80_ACCESS_VAL(srxh, member) : \ 2604 D11RXHDRSHORT_LT80_ACCESS_VAL(srxh, member)) 2605 2606 /** For accessing members of d11rxhdrmid_t by reference (address of members) */ 2607 #define D11RXHDRMID_ACCESS_REF(mrxh, corerev, corerev_minor, member) \ 2608 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2609 D11RXHDRMID_GE87_1_ACCESS_REF(mrxh, member) : \ 2610 D11REV_GE(corerev, 80) ? D11RXHDRMID_GE80_ACCESS_REF(mrxh, member) : NULL) 2611 2612 /** For accessing members of d11rxhdrmid_t by value (only value stored inside members accessed) */ 2613 #define D11RXHDRMID_ACCESS_VAL(mrxh, corerev, corerev_minor, member) \ 2614 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2615 D11RXHDRMID_GE87_1_ACCESS_VAL(mrxh, member) : \ 2616 D11REV_GE(corerev, 80) ? D11RXHDRMID_GE80_ACCESS_VAL(mrxh, member) : NULL) 2617 2618 /** For accessing members of d11rxhdr_t by reference (address of members) */ 2619 #define D11RXHDR_ACCESS_REF(rxh, corerev, corerev_minor, member) \ 2620 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2621 D11RXHDR_GE87_1_ACCESS_REF(rxh, member) : \ 2622 D11REV_GE(corerev, 80) ? D11RXHDR_GE80_ACCESS_REF(rxh, member) : \ 2623 D11RXHDR_LT80_ACCESS_REF(rxh, member)) 2624 2625 /** For accessing members of d11rxhdr_t by value (only value stored inside members accessed) */ 2626 #define D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, member) \ 2627 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2628 D11RXHDR_GE87_1_ACCESS_VAL(rxh, member) : \ 2629 D11REV_GE(corerev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, member) : \ 2630 D11RXHDR_LT80_ACCESS_VAL(rxh, member)) 2631 2632 /** For accessing members of d11rxhdr_t by value (only value stored inside members accessed) */ 2633 #define D11RXHDR_SET_VAL(rxh, corerev, corerev_minor, member, value) \ 2634 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2635 D11RXHDR_GE87_1_SET_VAL(rxh, member, value) : \ 2636 D11REV_GE(corerev, 80) ? D11RXHDR_GE80_SET_VAL(rxh, member, value) : \ 2637 D11RXHDR_LT80_SET_VAL(rxh, member, value)) 2638 2639 #define D11RXHDR_PTM(rxh, corerev, corerev_minor) \ 2640 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2641 D11RXHDR_GE87_1_ACCESS_VAL(rxh, PTMRxTime) : 0) 2642 2643 #define D11RXHDR_AVB(rxh, corerev, corerev_minor) \ 2644 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2645 (uint32)D11RXHDR_GE87_1_ACCESS_VAL(rxh, AVBRxTime) : \ 2646 D11REV_GE(corerev, 80) ? ((uint32)D11RXHDR_GE80_ACCESS_VAL(rxh, AvbRxTimeL) | \ 2647 ((uint32)D11RXHDR_GE80_ACCESS_VAL(rxh, AvbRxTimeH) << 16u)) : \ 2648 ((uint32)D11RXHDR_LT80_ACCESS_VAL(rxh, AvbRxTimeL) | \ 2649 ((uint32)D11RXHDR_LT80_ACCESS_VAL(rxh, AvbRxTimeH) << 16u))) 2650 2651 #define D11RXHDR_TSF_REF(rxh, corerev, corerev_minor) \ 2652 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2653 D11RXHDR_GE87_1_ACCESS_REF(rxh, TSFRxTime) : \ 2654 D11REV_GE(corerev, 80) ? (uint32*)D11RXHDR_GE80_ACCESS_REF(rxh, RxTSFTime) : \ 2655 (uint32*)D11RXHDR_LT80_ACCESS_REF(rxh, RxTSFTime)) 2656 2657 #define D11RXHDR_TSF(rxh, corerev, corerev_minor) \ 2658 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2659 D11RXHDR_GE87_1_ACCESS_VAL(rxh, TSFRxTime) : \ 2660 D11REV_GE(corerev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, RxTSFTime) : \ 2661 D11RXHDR_LT80_ACCESS_VAL(rxh, RxTSFTime)) 2662 2663 #define RXS_SHORT_ENAB(rev) (D11REV_GE(rev, 64) || \ 2664 D11REV_IS(rev, 60) || \ 2665 D11REV_IS(rev, 62)) 2666 2667 #define RXS_MID_ENAB(rev) (D11REV_GE(rev, 80)) 2668 #define RXS_LONG_ENAB(rev) (D11REV_GE(rev, 80)) 2669 2670 #define IS_D11RXHDRSHORT(rxh, rev, rev_min) ((RXS_SHORT_ENAB(rev) && \ 2671 ((D11RXHDR_ACCESS_VAL((rxh), (rev), (rev_min), dma_flags)) & RXS_SHORT_MASK)) != 0) 2672 2673 #define IS_D11RXHDRMID(rxh, rev, rev_min) ((RXS_MID_ENAB(rev) && \ 2674 ((D11RXHDR_ACCESS_VAL((rxh), (rev), (rev_min), dma_flags)) == 0))) 2675 2676 #define IS_D11RXHDRLONG(rxh, rev, rev_min) \ 2677 ((!(IS_D11RXHDRSHORT((rxh), (rev), (rev_min)))) && \ 2678 (!(IS_D11RXHDRMID((rxh), (rev), (rev_min))))) 2679 2680 #define D11RXHDR_HAS_UCODE_STATUS(rxhdr, corerev, corerev_minor) \ 2681 ((!IS_D11RXHDRSHORT((rxhdr), (corerev), (corerev_minor))) || \ 2682 (IS_D11RXHDRMID((rxhdr), (corerev), (corerev_minor)))) 2683 2684 #define IS_PHYRXHDR_VALID(rxh, corerev, corerev_minor) \ 2685 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2686 (D11RXHDR_GE87_1_ACCESS_VAL(rxh, dma_flags) == RXS_PHYRXST_VALID_REV_GE80) : \ 2687 D11REV_GE(corerev, 80) ? \ 2688 (D11RXHDR_GE80_ACCESS_VAL(rxh, dma_flags) == RXS_PHYRXST_VALID_REV_GE80) : \ 2689 (D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus2) & RXS_PHYRXST_VALID)) 2690 2691 #define RXHDR_GET_PAD_LEN(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \ 2692 ((((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2693 D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \ 2694 D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_PBPRES) != 0) ? HDRCONV_PAD : 0) : \ 2695 (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \ 2696 (((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, mrxs) & \ 2697 RXSS_PBPRES) != 0) ? HDRCONV_PAD : 0) : \ 2698 (((D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus1) & RXS_PBPRES) != 0) ? HDRCONV_PAD : 0))) 2699 2700 #define RXHDR_GET_PAD_PRES(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \ 2701 (((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2702 D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \ 2703 D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_PBPRES) != 0) : \ 2704 (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \ 2705 ((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, mrxs) & \ 2706 RXSS_PBPRES) != 0) : \ 2707 (((D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus1) & RXS_PBPRES) != 0)))) 2708 2709 #define RXHDR_GET_CONV_TYPE(rxh, corerev, corerev_minor) \ 2710 (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \ 2711 ((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, \ 2712 HdrConvSt) & HDRCONV_ETH_FRAME) != 0) : ((D11RXHDR_ACCESS_VAL(rxh, \ 2713 corerev, corerev_minor, HdrConvSt) & HDRCONV_ETH_FRAME) != 0)) 2714 2715 #define RXHDR_GET_ROE_ERR_STS(rxh, corerev, corerev_minor) \ 2716 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2717 ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_err_flags))) : 0) 2718 2719 #define RXHDR_GET_ROE_L3_TYPE(rxh, corerev, corerev_minor) \ 2720 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2721 ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_hw_sts)) & ROE_L3_PROT_TYPE_MASK) : 0) 2722 2723 #define RXHDR_GET_ROE_L4_TYPE(rxh, corerev, corerev_minor) \ 2724 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2725 ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_hw_sts)) & ROE_L4_PROT_TYPE_MASK) : 0) 2726 2727 #define RXHDR_GET_ROE_L3_STATUS(rxh, corerev, corerev_minor) \ 2728 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2729 ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_hw_sts)) & ROE_L3_CHKSUM_STATUS_MASK) : 0) 2730 2731 #define RXHDR_GET_ROE_L4_STATUS(rxh, corerev, corerev_minor) \ 2732 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2733 ((D11RXHDR_GE87_1_ACCESS_VAL(rxh, roe_hw_sts)) & ROE_L4_CHKSUM_STATUS_MASK) : 0) 2734 2735 #define RXHDR_GET_AGG_TYPE(rxh, corerev, corerev_minor) \ 2736 (D11REV_GE(corerev, 80) ? \ 2737 (((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2738 D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \ 2739 D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_AGGTYPE_MASK) >> RXSS_AGGTYPE_SHIFT) : \ 2740 (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \ 2741 ((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, mrxs) \ 2742 & RXSS_AGGTYPE_MASK) >> RXSS_AGGTYPE_SHIFT) : \ 2743 ((D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus2) & RXS_AGGTYPE_MASK) >> RXS_AGGTYPE_SHIFT))) 2744 2745 #define RXHDR_GET_PBPRS_REF(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \ 2746 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2747 D11RXHDR_GE87_1_ACCESS_REF(rxh, mrxs) : \ 2748 D11RXHDR_GE80_ACCESS_REF(rxh, mrxs)) : \ 2749 (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \ 2750 ((D11RXHDRSHORT_ACCESS_REF(rxh, corerev, corerev_minor, mrxs))) : \ 2751 (D11RXHDR_LT80_ACCESS_REF(rxh, RxStatus1)))) 2752 2753 #define RXHDR_GET_IS_DEFRAG(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \ 2754 (D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, RxStatus1) & RXS_IS_DEFRAG) : 0) 2755 2756 #define SET_RXHDR_PBPRS_REF_VAL(rxh, corerev, corerev_minor, val) \ 2757 (D11REV_GE(corerev, 80) ? \ 2758 (*val |= RXSS_PBPRES) : \ 2759 (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? (*val |= RXSS_PBPRES) : \ 2760 (*val |= RXS_PBPRES))) 2761 2762 #define CLEAR_RXHDR_PBPRS_REF_VAL(rxh, corerev, corerev_minor, val) \ 2763 (D11REV_GE(corerev, 80) ? \ 2764 (*val &= ~RXSS_PBPRES) : \ 2765 (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? (*val &= ~RXSS_PBPRES) : \ 2766 (*val &= ~RXS_PBPRES))) 2767 2768 #define RXHDR_GET_AMSDU(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \ 2769 (((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2770 D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \ 2771 D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_AMSDU_MASK) != 0) : \ 2772 (IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \ 2773 ((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, \ 2774 mrxs) & RXSS_AMSDU_MASK) != 0) : \ 2775 ((D11RXHDR_LT80_ACCESS_VAL(rxh, RxStatus2) & RXS_AMSDU_MASK) != 0))) 2776 2777 #ifdef BCMDBG 2778 #define RXHDR_GET_MSDU_COUNT(rxh, corerev, corerev_minor) (D11REV_GE(corerev, 80) ? \ 2779 (((D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? \ 2780 D11RXHDR_GE87_1_ACCESS_VAL(rxh, mrxs) : \ 2781 D11RXHDR_GE80_ACCESS_VAL(rxh, mrxs)) & RXSS_MSDU_CNT_MASK) >> RXSS_MSDU_CNT_SHIFT) : \ 2782 IS_D11RXHDRSHORT(rxh, corerev, corerev_minor) ? \ 2783 (((D11RXHDRSHORT_ACCESS_VAL(rxh, corerev, corerev_minor, mrxs)) & \ 2784 RXSS_MSDU_CNT_MASK) >> RXSS_MSDU_CNT_SHIFT) : 0) 2785 2786 #endif /* BCMDBG */ 2787 2788 /** Length of HW RX status in RxStatus */ 2789 #define HW_RXHDR_LEN_REV_GE87_1 (sizeof(d11rxhdrshort_ge87_1_t)) /* 24 bytes */ 2790 #define HW_RXHDR_LEN_REV_GE80 (sizeof(d11rxhdrshort_ge80_t)) /* 20 bytes */ 2791 #define HW_RXHDR_LEN_REV_LT80 (sizeof(d11rxhdrshort_lt80_t)) /* 12 bytes */ 2792 #define HW_RXHDR_LEN_REV_61_1 (sizeof(d11rxhdrshort_rev61_1_t)) /* 16 bytes */ 2793 2794 /** Length of HW RX status + ucode Rx status in RxStatus */ 2795 #define MID_RXHDR_LEN_REV_GE87_1 (sizeof(d11rxhdrmid_ge87_1_t)) /* 48 bytes */ 2796 #define MID_RXHDR_LEN_REV_GE80 (sizeof(d11rxhdrmid_ge80_t)) /* 36 bytes */ 2797 2798 /** Length of HW RX status + ucode RX status + PHY RX status + padding(if need align) */ 2799 #define D11_RXHDR_LEN_REV_GE87_1 (sizeof(d11rxhdr_ge87_1_t)) /* 80 bytes */ 2800 #define D11_RXHDR_LEN_REV_GE80 (sizeof(d11rxhdr_ge80_t)) /* 68 bytes */ 2801 #define D11_RXHDR_LEN_REV_LT80 (sizeof(d11rxhdr_lt80_t)) /* 36 bytes */ 2802 2803 #define HW_RXHDR_LEN(corerev, corerev_minor) \ 2804 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? HW_RXHDR_LEN_REV_GE87_1 : \ 2805 D11REV_GE(corerev, 80) ? HW_RXHDR_LEN_REV_GE80 : HW_RXHDR_LEN_REV_LT80) 2806 2807 #define MID_RXHDR_LEN(corerev, corerev_minor) \ 2808 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? MID_RXHDR_LEN_REV_GE87_1 : \ 2809 D11REV_GE(corerev, 80) ? \ 2810 MID_RXHDR_LEN_REV_GE80 : NULL) 2811 2812 #define D11_RXHDR_LEN(corerev, corerev_minor) \ 2813 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? D11_RXHDR_LEN_REV_GE87_1 : \ 2814 D11REV_GE(corerev, 80) ? D11_RXHDR_LEN_REV_GE80 : \ 2815 D11_RXHDR_LEN_REV_LT80) 2816 2817 #define FRAMELEN(corerev, corerev_minor, rxh) \ 2818 D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, RxFrameSize) 2819 2820 #define RXS_SHORT_MASK 0x01 /**< Short vs full rx status in dma_flags field of d11rxhdr */ 2821 2822 /** validate chip specific phychain info for MCSSQ snr. 2823 * should sync with uCode reporting. 2824 * please add a condition with decending order to avoid any wrong skip 2825 * Note: this macro can be removed once NEWT no longer needs 4368a0. 2826 */ 2827 #define IS_MCSSQ_ANT3_VALID_GE80(corerev, corerev_minor) \ 2828 (D11REV_IS(corerev, 83) && (D11MINORREV_IS(corerev_minor, 1))) 2829 2830 /* Header conversion status register bit fields */ 2831 #define HDRCONV_USR_ENAB 0x0001 2832 #define HDRCONV_ENAB 0x0100 2833 #define HDRCONV_ETH_FRAME 0x0200 2834 #define HDRCONV_STATUS_VALID 0x8000 2835 2836 #define ROE_L3_PROT_TYPE_IPV4 (0x10u) 2837 #define ROE_L3_PROT_TYPE_IPV6 (0x20u) 2838 #define ROE_L3_PROT_TYPE_MASK (0x30u) 2839 #define ROE_L3_PROT_TYPE_SHIFT (4u) 2840 2841 #define ROE_L4_PROT_TYPE_TCP (0x40u) 2842 #define ROE_L4_PROT_TYPE_UDP (0x80u) 2843 #define ROE_L4_PROT_TYPE_MASK (0xC0u) 2844 #define ROE_L4_PROT_TYPE_SHIFT (6u) 2845 2846 #define ROE_L3_CHKSUM_STATUS_FAIL (0x100u) 2847 #define ROE_L3_CHKSUM_STATUS_SUCCESS (0x200u) 2848 #define ROE_L3_CHKSUM_STATUS_MASK (0x300u) 2849 #define ROE_L3_CHKSUM_STATUS_SHIFT (8u) 2850 2851 #define ROE_L4_CHKSUM_STATUS_FAIL (0x400u) 2852 #define ROE_L4_CHKSUM_STATUS_SUCCESS (0x800u) 2853 #define ROE_L4_CHKSUM_STATUS_MASK (0xC00u) 2854 #define ROE_L4_CHKSUM_STATUS_SHIFT (10u) 2855 2856 /** NOTE: Due to precommit issue, _d11_autophyrxsts_ will be moved 2857 * to a separated file when 4387 trunk build is stable 2858 */ 2859 #ifndef _d11_autophyrxsts_ 2860 #define _d11_autophyrxsts_ 2861 2862 #define APRXS_WD0_L_EN_GE85 1u 2863 #define APRXS_WD0_H_EN_GE85 1u 2864 #define APRXS_WD1_L_EN_GE85 1u 2865 #define APRXS_WD1_H_EN_GE85 1u 2866 #define APRXS_WD2_L_EN_GE85 1u 2867 #define APRXS_WD2_H_EN_GE85 1u 2868 #define APRXS_WD3_L_EN_GE85 1u 2869 #define APRXS_WD3_H_EN_GE85 0u // DO NOT ENABLE WD3_H 2870 #define APRXS_WD4_L_EN_GE85 1u 2871 #define APRXS_WD4_H_EN_GE85 1u 2872 #define APRXS_WD5_L_EN_GE85 1u 2873 #define APRXS_WD5_H_EN_GE85 1u 2874 #define APRXS_WD6_L_EN_GE85 0u 2875 #define APRXS_WD6_H_EN_GE85 0u 2876 #define APRXS_WD7_L_EN_GE85 0u 2877 #define APRXS_WD7_H_EN_GE85 0u 2878 #define APRXS_WD8_L_EN_GE85 0u 2879 #define APRXS_WD8_H_EN_GE85 1u 2880 #define APRXS_WD9_L_EN_GE85 0u 2881 #define APRXS_WD9_H_EN_GE85 0u 2882 #define APRXS_WD10_L_EN_GE85 0u 2883 #define APRXS_WD10_H_EN_GE85 0u 2884 #define APRXS_WD11_L_EN_GE85 0u 2885 #define APRXS_WD11_H_EN_GE85 0u 2886 #define APRXS_WD12_L_EN_GE85 0u 2887 #define APRXS_WD12_H_EN_GE85 0u 2888 #define APRXS_WD13_L_EN_GE85 0u 2889 #define APRXS_WD13_H_EN_GE85 0u 2890 #define APRXS_WD14_L_EN_GE85 0u 2891 #define APRXS_WD14_H_EN_GE85 0u 2892 #define APRXS_WD15_L_EN_GE85 0u 2893 #define APRXS_WD15_H_EN_GE85 0u 2894 #define APRXS_WD16_L_EN_GE85 1u 2895 #define APRXS_WD16_H_EN_GE85 0u 2896 #define APRXS_WD17_L_EN_GE85 0u 2897 #define APRXS_WD17_H_EN_GE85 0u 2898 #define APRXS_WD18_L_EN_GE85 1u 2899 #define APRXS_WD18_H_EN_GE85 0u 2900 #define APRXS_WD19_L_EN_GE85 0u 2901 #define APRXS_WD19_H_EN_GE85 0u 2902 #define APRXS_WD20_L_EN_GE85 1u 2903 #define APRXS_WD20_H_EN_GE85 1u 2904 #define APRXS_WD21_L_EN_GE85 0u 2905 #define APRXS_WD21_H_EN_GE85 1u 2906 #define APRXS_WD22_L_EN_GE85 1u 2907 #define APRXS_WD22_H_EN_GE85 1u 2908 #define APRXS_WD23_L_EN_GE85 1u 2909 #define APRXS_WD23_H_EN_GE85 1u 2910 #define APRXS_WD24_L_EN_GE85 0u 2911 #define APRXS_WD24_H_EN_GE85 0u 2912 #define APRXS_WD25_L_EN_GE85 0u 2913 #define APRXS_WD25_H_EN_GE85 0u 2914 2915 enum { 2916 APRXS_WD0_L_SHIFT = 0, // frameType, unsupportedRate, band, lostCRS, shortPreamble 2917 APRXS_WD0_H_SHIFT, // PLCPViolation, MFCRSFired, ACCRSFired, MUPPDU, OBSSStat 2918 APRXS_WD1_L_SHIFT, // coremask, antcfg, 2919 APRXS_WD1_H_SHIFT, // BWclassification 2920 APRXS_WD2_L_SHIFT, // RxPwrAnt0 2921 APRXS_WD2_H_SHIFT, // RxPwrAnt1 2922 APRXS_WD3_L_SHIFT, // RxPwrAnt2 2923 APRXS_WD3_H_SHIFT, // RxPwrAnt3, OCL 2924 APRXS_WD4_L_SHIFT, // RSSI factional bit 2925 APRXS_WD4_H_SHIFT, // AGC type, ACI mitigation state, ClipCount, DynBWInNonHT 2926 APRXS_WD5_L_SHIFT, // MCSSQSNRCore0 2927 APRXS_WD5_H_SHIFT, // MCSSQSNRCore1 2928 APRXS_WD6_L_SHIFT, // MCSSQSNRCore2 2929 APRXS_WD6_H_SHIFT, // MCSSQSNRCore3, OCL 1 2930 APRXS_WD7_L_SHIFT, // MUIntProcessType, 2931 APRXS_WD7_H_SHIFT, // coarse freq_offset, packet abort 2932 APRXS_WD8_L_SHIFT = 0, // fine freq offset 2933 APRXS_WD8_H_SHIFT, // ChBWInNonHT, MLUsed, SINRBasedACIDet 2934 APRXS_WD9_L_SHIFT, // SpatialSQCnt 2935 APRXS_WD9_H_SHIFT, // packet gain 2936 APRXS_WD10_L_SHIFT, // RxPwrAntExt 2937 APRXS_WD10_H_SHIFT, // coarse freq_offset of 2nd 80mhz 2938 APRXS_WD11_L_SHIFT, // fine freq_offset of 2nd 80mhz 2939 APRXS_WD11_H_SHIFT, 2940 APRXS_WD12_L_SHIFT, 2941 APRXS_WD12_H_SHIFT, 2942 APRXS_WD13_L_SHIFT, 2943 APRXS_WD13_H_SHIFT, 2944 APRXS_WD14_L_SHIFT, 2945 APRXS_WD14_H_SHIFT, 2946 APRXS_WD15_L_SHIFT, 2947 APRXS_WD15_H_SHIFT, 2948 APRXS_WD16_L_SHIFT = 0, 2949 APRXS_WD16_H_SHIFT, 2950 APRXS_WD17_L_SHIFT, 2951 APRXS_WD17_H_SHIFT, 2952 APRXS_WD18_L_SHIFT, 2953 APRXS_WD18_H_SHIFT, 2954 APRXS_WD19_L_SHIFT, 2955 APRXS_WD19_H_SHIFT, 2956 APRXS_WD20_L_SHIFT, 2957 APRXS_WD20_H_SHIFT, 2958 APRXS_WD21_L_SHIFT, 2959 APRXS_WD21_H_SHIFT, 2960 APRXS_WD22_L_SHIFT, // STA ID 2961 APRXS_WD22_H_SHIFT, // STA ID, NSTS, TXBF, DCM 2962 APRXS_WD23_L_SHIFT, 2963 APRXS_WD23_H_SHIFT, 2964 APRXS_WD24_L_SHIFT = 0, 2965 APRXS_WD24_H_SHIFT, 2966 APRXS_WD25_L_SHIFT, 2967 APRXS_WD25_H_SHIFT 2968 }; 2969 2970 #define APRXS_WD0_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2971 APRXS_WD0_L_EN_GE85 : 0) 2972 #define APRXS_WD0_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2973 APRXS_WD0_H_EN_GE85 : 0) 2974 #define APRXS_WD1_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2975 APRXS_WD1_L_EN_GE85 : 0) 2976 #define APRXS_WD1_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2977 APRXS_WD1_H_EN_GE85 : 0) 2978 #define APRXS_WD2_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2979 APRXS_WD2_L_EN_GE85 : 0) 2980 #define APRXS_WD2_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2981 APRXS_WD2_H_EN_GE85 : 0) 2982 #define APRXS_WD3_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2983 APRXS_WD3_L_EN_GE85 : 0) 2984 #define APRXS_WD3_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2985 APRXS_WD3_H_EN_GE85 : 0) 2986 #define APRXS_WD4_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2987 APRXS_WD4_L_EN_GE85 : 0) 2988 #define APRXS_WD4_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2989 APRXS_WD4_H_EN_GE85 : 0) 2990 #define APRXS_WD5_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2991 APRXS_WD5_L_EN_GE85 : 0) 2992 #define APRXS_WD5_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2993 APRXS_WD5_H_EN_GE85 : 0) 2994 #define APRXS_WD6_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2995 APRXS_WD6_L_EN_GE85 : 0) 2996 #define APRXS_WD6_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2997 APRXS_WD6_H_EN_GE85 : 0) 2998 #define APRXS_WD7_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 2999 APRXS_WD7_L_EN_GE85 : 0) 3000 #define APRXS_WD7_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3001 APRXS_WD7_H_EN_GE85 : 0) 3002 #define APRXS_WD8_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3003 APRXS_WD8_L_EN_GE85 : 0) 3004 #define APRXS_WD8_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3005 APRXS_WD8_H_EN_GE85 : 0) 3006 #define APRXS_WD9_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3007 APRXS_WD9_L_EN_GE85 : 0) 3008 #define APRXS_WD9_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3009 APRXS_WD9_H_EN_GE85 : 0) 3010 #define APRXS_WD10_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3011 APRXS_WD10_L_EN_GE85 : 0) 3012 #define APRXS_WD10_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3013 APRXS_WD10_H_EN_GE85 : 0) 3014 #define APRXS_WD11_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3015 APRXS_WD11_L_EN_GE85 : 0) 3016 #define APRXS_WD11_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3017 APRXS_WD11_H_EN_GE85 : 0) 3018 #define APRXS_WD12_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3019 APRXS_WD12_L_EN_GE85 : 0) 3020 #define APRXS_WD12_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3021 APRXS_WD12_H_EN_GE85 : 0) 3022 #define APRXS_WD13_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3023 APRXS_WD13_L_EN_GE85 : 0) 3024 #define APRXS_WD13_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3025 APRXS_WD13_H_EN_GE85 : 0) 3026 #define APRXS_WD14_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3027 APRXS_WD14_L_EN_GE85 : 0) 3028 #define APRXS_WD14_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3029 APRXS_WD14_H_EN_GE85 : 0) 3030 #define APRXS_WD15_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3031 APRXS_WD15_L_EN_GE85 : 0) 3032 #define APRXS_WD15_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3033 APRXS_WD15_H_EN_GE85 : 0) 3034 #define APRXS_WD16_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3035 APRXS_WD16_L_EN_GE85 : 0) 3036 #define APRXS_WD16_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3037 APRXS_WD16_H_EN_GE85 : 0) 3038 #define APRXS_WD17_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3039 APRXS_WD17_L_EN_GE85 : 0) 3040 #define APRXS_WD17_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3041 APRXS_WD17_H_EN_GE85 : 0) 3042 #define APRXS_WD18_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3043 APRXS_WD18_L_EN_GE85 : 0) 3044 #define APRXS_WD18_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3045 APRXS_WD18_H_EN_GE85 : 0) 3046 #define APRXS_WD19_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3047 APRXS_WD19_L_EN_GE85 : 0) 3048 #define APRXS_WD19_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3049 APRXS_WD19_H_EN_GE85 : 0) 3050 #define APRXS_WD20_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3051 APRXS_WD20_L_EN_GE85 : 0) 3052 #define APRXS_WD20_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3053 APRXS_WD20_H_EN_GE85 : 0) 3054 #define APRXS_WD21_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3055 APRXS_WD21_L_EN_GE85 : 0) 3056 #define APRXS_WD21_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3057 APRXS_WD21_H_EN_GE85 : 0) 3058 #define APRXS_WD22_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3059 APRXS_WD22_L_EN_GE85 : 0) 3060 #define APRXS_WD22_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3061 APRXS_WD22_H_EN_GE85 : 0) 3062 #define APRXS_WD23_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3063 APRXS_WD23_L_EN_GE85 : 0) 3064 #define APRXS_WD23_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3065 APRXS_WD23_H_EN_GE85 : 0) 3066 #define APRXS_WD24_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3067 APRXS_WD24_L_EN_GE85 : 0) 3068 #define APRXS_WD24_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3069 APRXS_WD24_H_EN_GE85 : 0) 3070 #define APRXS_WD25_L_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3071 APRXS_WD25_L_EN_GE85 : 0) 3072 #define APRXS_WD25_H_EN(rev) ((D11REV_GE(rev, 85)) ? \ 3073 APRXS_WD25_H_EN_GE85 : 0) 3074 3075 #define APRXS_BMAP0(rev) ((APRXS_WD0_L_EN(rev) << APRXS_WD0_L_SHIFT) | \ 3076 (APRXS_WD0_H_EN(rev) << APRXS_WD0_H_SHIFT) |\ 3077 (APRXS_WD1_L_EN(rev) << APRXS_WD1_L_SHIFT) |\ 3078 (APRXS_WD1_H_EN(rev) << APRXS_WD1_H_SHIFT) |\ 3079 (APRXS_WD2_L_EN(rev) << APRXS_WD2_L_SHIFT) |\ 3080 (APRXS_WD2_H_EN(rev) << APRXS_WD2_H_SHIFT) |\ 3081 (APRXS_WD3_L_EN(rev) << APRXS_WD3_L_SHIFT) |\ 3082 (APRXS_WD3_H_EN(rev) << APRXS_WD3_H_SHIFT) |\ 3083 (APRXS_WD4_L_EN(rev) << APRXS_WD4_L_SHIFT) |\ 3084 (APRXS_WD4_H_EN(rev) << APRXS_WD4_H_SHIFT) |\ 3085 (APRXS_WD5_L_EN(rev) << APRXS_WD5_L_SHIFT) |\ 3086 (APRXS_WD5_H_EN(rev) << APRXS_WD5_H_SHIFT) |\ 3087 (APRXS_WD6_L_EN(rev) << APRXS_WD6_L_SHIFT) |\ 3088 (APRXS_WD6_H_EN(rev) << APRXS_WD6_H_SHIFT) |\ 3089 (APRXS_WD7_L_EN(rev) << APRXS_WD7_L_SHIFT) |\ 3090 (APRXS_WD7_H_EN(rev) << APRXS_WD7_H_SHIFT)) 3091 3092 #define APRXS_BMAP1(rev) ((APRXS_WD8_L_EN(rev) << APRXS_WD8_L_SHIFT) | \ 3093 (APRXS_WD8_H_EN(rev) << APRXS_WD8_H_SHIFT) |\ 3094 (APRXS_WD9_L_EN(rev) << APRXS_WD9_L_SHIFT) |\ 3095 (APRXS_WD9_H_EN(rev) << APRXS_WD9_H_SHIFT) |\ 3096 (APRXS_WD10_L_EN(rev) << APRXS_WD10_L_SHIFT) |\ 3097 (APRXS_WD10_H_EN(rev) << APRXS_WD10_H_SHIFT) |\ 3098 (APRXS_WD11_L_EN(rev) << APRXS_WD11_L_SHIFT) |\ 3099 (APRXS_WD11_H_EN(rev) << APRXS_WD11_H_SHIFT) |\ 3100 (APRXS_WD12_L_EN(rev) << APRXS_WD12_L_SHIFT) |\ 3101 (APRXS_WD12_H_EN(rev) << APRXS_WD12_H_SHIFT) |\ 3102 (APRXS_WD13_L_EN(rev) << APRXS_WD13_L_SHIFT) |\ 3103 (APRXS_WD13_H_EN(rev) << APRXS_WD13_H_SHIFT) |\ 3104 (APRXS_WD14_L_EN(rev) << APRXS_WD14_L_SHIFT) |\ 3105 (APRXS_WD14_H_EN(rev) << APRXS_WD14_H_SHIFT) |\ 3106 (APRXS_WD15_L_EN(rev) << APRXS_WD15_L_SHIFT) |\ 3107 (APRXS_WD15_H_EN(rev) << APRXS_WD15_H_SHIFT)) 3108 3109 #define APRXS_BMAP2(rev) ((APRXS_WD16_L_EN(rev) << APRXS_WD16_L_SHIFT) | \ 3110 (APRXS_WD16_H_EN(rev) << APRXS_WD16_H_SHIFT) |\ 3111 (APRXS_WD17_L_EN(rev) << APRXS_WD17_L_SHIFT) |\ 3112 (APRXS_WD17_H_EN(rev) << APRXS_WD17_H_SHIFT) |\ 3113 (APRXS_WD18_L_EN(rev) << APRXS_WD18_L_SHIFT) |\ 3114 (APRXS_WD18_H_EN(rev) << APRXS_WD18_H_SHIFT) |\ 3115 (APRXS_WD19_L_EN(rev) << APRXS_WD19_L_SHIFT) |\ 3116 (APRXS_WD19_H_EN(rev) << APRXS_WD19_H_SHIFT) |\ 3117 (APRXS_WD20_L_EN(rev) << APRXS_WD20_L_SHIFT) |\ 3118 (APRXS_WD20_H_EN(rev) << APRXS_WD20_H_SHIFT) |\ 3119 (APRXS_WD21_L_EN(rev) << APRXS_WD21_L_SHIFT) |\ 3120 (APRXS_WD21_H_EN(rev) << APRXS_WD21_H_SHIFT) |\ 3121 (APRXS_WD22_L_EN(rev) << APRXS_WD22_L_SHIFT) |\ 3122 (APRXS_WD22_H_EN(rev) << APRXS_WD22_H_SHIFT) |\ 3123 (APRXS_WD23_L_EN(rev) << APRXS_WD23_L_SHIFT) |\ 3124 (APRXS_WD23_H_EN(rev) << APRXS_WD23_H_SHIFT)) 3125 3126 #define APRXS_BMAP3(rev) ((APRXS_WD24_L_EN(rev) << APRXS_WD24_L_SHIFT) | \ 3127 (APRXS_WD24_H_EN(rev) << APRXS_WD24_H_SHIFT) |\ 3128 (APRXS_WD25_L_EN(rev) << APRXS_WD25_L_SHIFT) |\ 3129 (APRXS_WD25_H_EN(rev) << APRXS_WD25_H_SHIFT)) 3130 /* byte position */ 3131 #define APRXS_WD0_L_POS(rev) 0u 3132 #define APRXS_WD0_H_POS(rev) (APRXS_WD0_L_POS(rev) + APRXS_WD0_L_EN(rev)) /* 1 */ 3133 #define APRXS_WD1_L_POS(rev) (APRXS_WD0_H_POS(rev) + APRXS_WD0_H_EN(rev)) /* 2 */ 3134 #define APRXS_WD1_H_POS(rev) (APRXS_WD1_L_POS(rev) + APRXS_WD1_L_EN(rev)) /* 3 */ 3135 #define APRXS_WD2_L_POS(rev) (APRXS_WD1_H_POS(rev) + APRXS_WD1_H_EN(rev)) /* 4 */ 3136 #define APRXS_WD2_H_POS(rev) (APRXS_WD2_L_POS(rev) + APRXS_WD2_L_EN(rev)) /* 5 */ 3137 #define APRXS_WD3_L_POS(rev) (APRXS_WD2_H_POS(rev) + APRXS_WD2_H_EN(rev)) /* 6 */ 3138 #define APRXS_WD3_H_POS(rev) (APRXS_WD3_L_POS(rev) + APRXS_WD3_L_EN(rev)) /* 7 */ 3139 #define APRXS_WD4_L_POS(rev) (APRXS_WD3_H_POS(rev) + APRXS_WD3_H_EN(rev)) /* 7 */ 3140 #define APRXS_WD4_H_POS(rev) (APRXS_WD4_L_POS(rev) + APRXS_WD4_L_EN(rev)) /* 8 */ 3141 #define APRXS_WD5_L_POS(rev) (APRXS_WD4_H_POS(rev) + APRXS_WD4_H_EN(rev)) /* 9 */ 3142 #define APRXS_WD5_H_POS(rev) (APRXS_WD5_L_POS(rev) + APRXS_WD5_L_EN(rev)) /* 10 */ 3143 #define APRXS_WD6_L_POS(rev) (APRXS_WD5_H_POS(rev) + APRXS_WD5_H_EN(rev)) /* 11 */ 3144 #define APRXS_WD6_H_POS(rev) (APRXS_WD6_L_POS(rev) + APRXS_WD6_L_EN(rev)) /* 11 */ 3145 #define APRXS_WD7_L_POS(rev) (APRXS_WD6_H_POS(rev) + APRXS_WD6_H_EN(rev)) /* 11 */ 3146 #define APRXS_WD7_H_POS(rev) (APRXS_WD7_L_POS(rev) + APRXS_WD7_L_EN(rev)) /* 11 */ 3147 #define APRXS_WD8_L_POS(rev) (APRXS_WD7_H_POS(rev) + APRXS_WD7_H_EN(rev)) /* 11 */ 3148 #define APRXS_WD8_H_POS(rev) (APRXS_WD8_L_POS(rev) + APRXS_WD8_L_EN(rev)) /* 11 */ 3149 #define APRXS_WD9_L_POS(rev) (APRXS_WD8_H_POS(rev) + APRXS_WD8_H_EN(rev)) /* 12 */ 3150 #define APRXS_WD9_H_POS(rev) (APRXS_WD9_L_POS(rev) + APRXS_WD9_L_EN(rev)) /* 12 */ 3151 #define APRXS_WD10_L_POS(rev) (APRXS_WD9_H_POS(rev) + APRXS_WD9_H_EN(rev)) /* 12 */ 3152 #define APRXS_WD10_H_POS(rev) (APRXS_WD10_L_POS(rev) + APRXS_WD10_L_EN(rev)) /* 12 */ 3153 #define APRXS_WD11_L_POS(rev) (APRXS_WD10_H_POS(rev) + APRXS_WD10_H_EN(rev)) /* 12 */ 3154 #define APRXS_WD11_H_POS(rev) (APRXS_WD11_L_POS(rev) + APRXS_WD11_L_EN(rev)) /* 12 */ 3155 #define APRXS_WD12_L_POS(rev) (APRXS_WD11_H_POS(rev) + APRXS_WD11_H_EN(rev)) /* 12 */ 3156 #define APRXS_WD12_H_POS(rev) (APRXS_WD12_L_POS(rev) + APRXS_WD12_L_EN(rev)) /* 12 */ 3157 #define APRXS_WD13_L_POS(rev) (APRXS_WD12_H_POS(rev) + APRXS_WD12_H_EN(rev)) /* 12 */ 3158 #define APRXS_WD13_H_POS(rev) (APRXS_WD13_L_POS(rev) + APRXS_WD13_L_EN(rev)) /* 12 */ 3159 #define APRXS_WD14_L_POS(rev) (APRXS_WD13_H_POS(rev) + APRXS_WD13_H_EN(rev)) /* 12 */ 3160 #define APRXS_WD14_H_POS(rev) (APRXS_WD14_L_POS(rev) + APRXS_WD14_L_EN(rev)) /* 12 */ 3161 #define APRXS_WD15_L_POS(rev) (APRXS_WD14_H_POS(rev) + APRXS_WD14_H_EN(rev)) /* 12 */ 3162 #define APRXS_WD15_H_POS(rev) (APRXS_WD15_L_POS(rev) + APRXS_WD15_L_EN(rev)) /* 12 */ 3163 #define APRXS_WD16_L_POS(rev) (APRXS_WD15_H_POS(rev) + APRXS_WD15_H_EN(rev)) /* 12 */ 3164 #define APRXS_WD16_H_POS(rev) (APRXS_WD16_L_POS(rev) + APRXS_WD16_L_EN(rev)) /* 13 */ 3165 #define APRXS_WD17_L_POS(rev) (APRXS_WD16_H_POS(rev) + APRXS_WD16_H_EN(rev)) /* 13 */ 3166 #define APRXS_WD17_H_POS(rev) (APRXS_WD17_L_POS(rev) + APRXS_WD17_L_EN(rev)) /* 13 */ 3167 #define APRXS_WD18_L_POS(rev) (APRXS_WD17_H_POS(rev) + APRXS_WD17_H_EN(rev)) /* 13 */ 3168 #define APRXS_WD18_H_POS(rev) (APRXS_WD18_L_POS(rev) + APRXS_WD18_L_EN(rev)) /* 14 */ 3169 #define APRXS_WD19_L_POS(rev) (APRXS_WD18_H_POS(rev) + APRXS_WD18_H_EN(rev)) /* 14 */ 3170 #define APRXS_WD19_H_POS(rev) (APRXS_WD19_L_POS(rev) + APRXS_WD19_L_EN(rev)) /* 14 */ 3171 #define APRXS_WD20_L_POS(rev) (APRXS_WD19_H_POS(rev) + APRXS_WD19_H_EN(rev)) /* 14 */ 3172 #define APRXS_WD20_H_POS(rev) (APRXS_WD20_L_POS(rev) + APRXS_WD20_L_EN(rev)) /* 15 */ 3173 #define APRXS_WD21_L_POS(rev) (APRXS_WD20_H_POS(rev) + APRXS_WD20_H_EN(rev)) /* 16 */ 3174 #define APRXS_WD21_H_POS(rev) (APRXS_WD21_L_POS(rev) + APRXS_WD21_L_EN(rev)) /* 16 */ 3175 #define APRXS_WD22_L_POS(rev) (APRXS_WD21_H_POS(rev) + APRXS_WD21_H_EN(rev)) /* 17 */ 3176 #define APRXS_WD22_H_POS(rev) (APRXS_WD22_L_POS(rev) + APRXS_WD22_L_EN(rev)) /* 18 */ 3177 #define APRXS_WD23_L_POS(rev) (APRXS_WD22_H_POS(rev) + APRXS_WD22_H_EN(rev)) /* 19 */ 3178 #define APRXS_WD23_H_POS(rev) (APRXS_WD23_L_POS(rev) + APRXS_WD23_L_EN(rev)) /* 20 */ 3179 #define APRXS_WD24_L_POS(rev) (APRXS_WD23_H_POS(rev) + APRXS_WD23_H_EN(rev)) /* 21 */ 3180 #define APRXS_WD24_H_POS(rev) (APRXS_WD24_L_POS(rev) + APRXS_WD24_L_EN(rev)) /* 21 */ 3181 #define APRXS_WD25_L_POS(rev) (APRXS_WD24_H_POS(rev) + APRXS_WD24_H_EN(rev)) /* 22 */ 3182 #define APRXS_WD25_H_POS(rev) (APRXS_WD25_L_POS(rev) + APRXS_WD25_L_EN(rev)) /* 23 */ 3183 3184 #define APRXS_NBYTES(rev) (APRXS_WD25_H_POS(rev)) // total number of bytes enabled 3185 3186 // frame type 3187 #define APRXS_FT_POS(rev) APRXS_WD0_L_POS(rev) 3188 #define APRXS_FT_MASK 0xFu 3189 #define APRXS_FT(rxh, rev, min_rev) \ 3190 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3191 (rxh)->ge87_1.PHYRXSTATUS[APRXS_FT_POS(rev)] : \ 3192 (rxh)->ge85.PHYRXSTATUS[APRXS_FT_POS(rev)]) & \ 3193 APRXS_FT_MASK) 3194 3195 // unsupported rate 3196 #define APRXS_UNSRATE_POS(rev) APRXS_WD0_L_POS(rev) 3197 #define APRXS_UNSRATE_MASK 0x10u 3198 #define APRXS_UNSRATE_SHIFT 4u 3199 #define APRXS_UNSRATE(rxh, rev, min_rev) \ 3200 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3201 (rxh)->ge87_1.PHYRXSTATUS[APRXS_UNSRATE_POS(rev)] : \ 3202 (rxh)->ge85.PHYRXSTATUS[APRXS_UNSRATE_POS(rev)]) & \ 3203 APRXS_UNSRATE_MASK) >> APRXS_UNSRATE_SHIFT) 3204 3205 // band 3206 #define APRXS_BAND_POS(rev) APRXS_WD0_L_POS(rev) 3207 #define APRXS_BAND_MASK 0x20u 3208 #define APRXS_BAND_SHIFT 5u 3209 #define APRXS_BAND(rxh, rev, min_rev) \ 3210 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3211 (rxh)->ge87_1.PHYRXSTATUS[APRXS_BAND_POS(rev)] : \ 3212 (rxh)->ge85.PHYRXSTATUS[APRXS_BAND_POS(rev)]) & \ 3213 APRXS_BAND_MASK) >> APRXS_BAND_SHIFT) 3214 3215 // lost CRS 3216 #define APRXS_LOSTCRS_POS(rev) APRXS_WD0_L_POS(rev) 3217 #define APRXS_LOSTCRS_MASK 0x40u 3218 #define APRXS_LOSTCRS_SHIFT 6u 3219 #define APRXS_LOSTCRS(rxh, rev, min_rev) \ 3220 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3221 (rxh)->ge87_1.PHYRXSTATUS[APRXS_LOSTCRS_POS(rev)] : \ 3222 (rxh)->ge85.PHYRXSTATUS[APRXS_LOSTCRS_POS(rev)]) & \ 3223 APRXS_LOSTCRS_MASK) >> APRXS_LOSTCRS_SHIFT) 3224 3225 // short preamble 3226 #define APRXS_SHORTH_POS(rev) APRXS_WD0_L_POS(rev) 3227 #define APRXS_SHORTH_MASK 0x80u 3228 #define APRXS_SHORTH_SHIFT 7u 3229 #define APRXS_SHORTH(rxh, rev, min_rev) \ 3230 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3231 (rxh)->ge87_1.PHYRXSTATUS[APRXS_SHORTH_POS(rev)] : \ 3232 (rxh)->ge85.PHYRXSTATUS[APRXS_SHORTH_POS(rev)]) & \ 3233 APRXS_SHORTH_MASK) >> APRXS_SHORTH_SHIFT) 3234 3235 // plcp format violation 3236 #define APRXS_PLCPFV_POS(rev) APRXS_WD0_H_POS(rev) 3237 #define APRXS_PLCPFV_MASK 0x1u 3238 #define APRXS_PLCPFV(rxh, rev, min_rev) \ 3239 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3240 (rxh)->ge87_1.PHYRXSTATUS[APRXS_PLCPFV_POS(rev)] : \ 3241 (rxh)->ge85.PHYRXSTATUS[APRXS_PLCPFV_POS(rev)]) & \ 3242 APRXS_PLCPFV_MASK) 3243 3244 // plcp header CRC failed 3245 #define APRXS_PLCPHCF_POS(rev) APRXS_WD0_H_POS(rev) 3246 #define APRXS_PLCPHCF_MASK 0x2u 3247 #define APRXS_PLCPHCF_SHIFT 1u 3248 #define APRXS_PLCPHCF(rxh, rev, min_rev) \ 3249 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3250 (rxh)->ge87_1.PHYRXSTATUS[APRXS_PLCPHCF_POS(rev)] : \ 3251 (rxh)->ge85.PHYRXSTATUS[APRXS_PLCPHCF_POS(rev)]) & \ 3252 APRXS_PLCPHCF_MASK) >> APRXS_PLCPHCF_SHIFT) 3253 3254 // MFCRS fired 3255 #define APRXS_MFCRS_FIRED_POS(rev) APRXS_WD0_H_POS(rev) 3256 #define APRXS_MFCRS_FIRED_MASK 0x4u 3257 #define APRXS_MFCRS_FIRED_SHIFT 2u 3258 #define APRXS_MFCRS_FIRED(rxh, rev, min_rev) \ 3259 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3260 (rxh)->ge87_1.PHYRXSTATUS[APRXS_MFCRS_FIRED_POS(rev)] : \ 3261 (rxh)->ge85.PHYRXSTATUS[APRXS_MFCRS_FIRED_POS(rev)]) & \ 3262 APRXS_MFCRS_FIRED_MASK) >> APRXS_MFCRS_FIRED_SHIFT) 3263 3264 // ACCRS fired 3265 #define APRXS_ACCRS_FIRED_POS(rev) APRXS_WD0_H_POS(rev) 3266 #define APRXS_ACCRS_FIRED_MASK 0x8u 3267 #define APRXS_ACCRS_FIRED_SHIFT 3u 3268 #define APRXS_ACCRS_FIRED(rxh, rev, min_rev) \ 3269 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3270 (rxh)->ge87_1.PHYRXSTATUS[APRXS_ACCRS_FIRED_POS(rev)] : \ 3271 (rxh)->ge85.PHYRXSTATUS[APRXS_ACCRS_FIRED_POS(rev)]) & \ 3272 APRXS_ACCRS_FIRED_MASK) >> APRXS_ACCRS_FIRED_SHIFT) 3273 3274 // MU PPDU 3275 #define APRXS_MUPPDU_POS(rev) APRXS_WD0_H_POS(rev) 3276 #define APRXS_MUPPDU_MASK 0x10u 3277 #define APRXS_MUPPDU_SHIFT 4u 3278 #define APRXS_MUPPDU(rxh, rev, min_rev) \ 3279 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3280 (rxh)->ge87_1.PHYRXSTATUS[APRXS_MUPPDU_POS(rev)] : \ 3281 (rxh)->ge85.PHYRXSTATUS[APRXS_MUPPDU_POS(rev)]) & \ 3282 APRXS_MUPPDU_MASK) >> APRXS_MUPPDU_SHIFT) 3283 3284 // OBSS status 3285 #define APRXS_OBSS_STS_POS(rev) APRXS_WD0_H_POS(rev) 3286 #define APRXS_OBSS_STS_MASK 0xE0u 3287 #define APRXS_OBSS_STS_SHIFT 5u 3288 #define APRXS_OBSS_STS(rxh, rev, min_rev) \ 3289 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3290 (rxh)->ge87_1.PHYRXSTATUS[APRXS_OBSS_STS_POS(rev)] : \ 3291 (rxh)->ge85.PHYRXSTATUS[APRXS_OBSS_STS_POS(rev)]) & \ 3292 APRXS_OBSS_STS_MASK) >> APRXS_OBSS_STS_SHIFT) 3293 3294 // coremask 3295 #define APRXS_COREMASK_POS(rev) APRXS_WD1_L_POS(rev) 3296 #define APRXS_COREMASK_MASK 0xFu 3297 #define APRXS_COREMASK(rxh, rev, min_rev) \ 3298 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3299 (rxh)->ge87_1.PHYRXSTATUS[APRXS_COREMASK_POS(rev)] : \ 3300 (rxh)->ge85.PHYRXSTATUS[APRXS_COREMASK_POS(rev)]) & \ 3301 APRXS_COREMASK_MASK) 3302 3303 // antcfg 3304 #define APRXS_ANTCFG_POS(rev) APRXS_WD1_L_POS(rev) 3305 #define APRXS_ANTCFG_MASK 0xF0u 3306 #define APRXS_ANTCFG_SHIFT 4u 3307 #define APRXS_ANTCFG(rxh, rev, min_rev) \ 3308 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3309 (rxh)->ge87_1.PHYRXSTATUS[APRXS_ANTCFG_POS(rev)] : \ 3310 (rxh)->ge85.PHYRXSTATUS[APRXS_ANTCFG_POS(rev)]) & \ 3311 APRXS_ANTCFG_MASK) >> APRXS_ANTCFG_SHIFT) 3312 3313 // final BW classification 3314 #define APRXS_SUBBAND_POS(rev) APRXS_WD1_H_POS(rev) 3315 #define APRXS_SUBBAND_MASK 0xFFu 3316 #define APRXS_SUBBAND(rxh, rev, min_rev) \ 3317 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3318 (rxh)->ge87_1.PHYRXSTATUS[APRXS_SUBBAND_POS(rev)] : \ 3319 (rxh)->ge85.PHYRXSTATUS[APRXS_SUBBAND_POS(rev)]) & \ 3320 APRXS_SUBBAND_MASK) 3321 3322 // Rx power Antenna0 3323 #define APRXS_RXPWR_ANT0_POS(rev) APRXS_WD2_L_POS(rev) 3324 #define APRXS_RXPWR_ANT0_MASK 0xFFu 3325 #define APRXS_RXPWR_ANT0(rxh, rev, min_rev) \ 3326 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3327 (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_ANT0_POS(rev)] : \ 3328 (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_ANT0_POS(rev)]) & \ 3329 APRXS_RXPWR_ANT0_MASK) 3330 3331 // Rx power Antenna1 3332 #define APRXS_RXPWR_ANT1_POS(rev) APRXS_WD2_H_POS(rev) 3333 #define APRXS_RXPWR_ANT1_MASK 0xFFu 3334 #define APRXS_RXPWR_ANT1(rxh, rev, min_rev) \ 3335 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3336 (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_ANT1_POS(rev)] : \ 3337 (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_ANT1_POS(rev)]) & \ 3338 APRXS_RXPWR_ANT1_MASK) 3339 3340 // Rx power Antenna2 3341 #define APRXS_RXPWR_ANT2_POS(rev) APRXS_WD3_L_POS(rev) 3342 #define APRXS_RXPWR_ANT2_MASK 0xFFu 3343 #define APRXS_RXPWR_ANT2(rxh, rev, min_rev) \ 3344 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3345 (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_ANT2_POS(rev)] : \ 3346 (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_ANT2_POS(rev)]) & \ 3347 APRXS_RXPWR_ANT2_MASK) 3348 3349 // Rx power Antenna3 3350 #define APRXS_RXPWR_ANT3_POS(rev) APRXS_WD3_H_POS(rev) 3351 #define APRXS_RXPWR_ANT3_MASK 0xFFu 3352 #define APRXS_RXPWR_ANT3(rxh, rev, min_rev) \ 3353 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3354 (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_ANT3_POS(rev)] : \ 3355 (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_ANT3_POS(rev)]) & \ 3356 APRXS_RXPWR_ANT3_MASK) 3357 3358 // RX ELNA INDEX ANT0 3359 #define APRXS_ELNA_IDX_ANT0_POS(rev) APRXS_WD20_L_POS(rev) 3360 #define APRXS_ELNA_IDX_ANT0_MASK 0x2u 3361 #define APRXS_ELNA_IDX_ANT0_SHIFT 1u 3362 #define APRXS_ELNA_IDX_ANT0(rxh, rev, min_rev) \ 3363 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3364 (rxh)->ge87_1.PHYRXSTATUS[APRXS_ELNA_IDX_ANT0_POS(rev)] : \ 3365 (rxh)->ge85.PHYRXSTATUS[APRXS_ELNA_IDX_ANT0_POS(rev)]) & \ 3366 APRXS_ELNA_IDX_ANT0_MASK) >> APRXS_ELNA_IDX_ANT0_SHIFT) 3367 3368 // RX ELNA INDEX ANT1 3369 #define APRXS_ELNA_IDX_ANT1_POS(rev) APRXS_WD20_L_POS(rev) 3370 #define APRXS_ELNA_IDX_ANT1_MASK 0x20u 3371 #define APRXS_ELNA_IDX_ANT1_SHIFT 5u 3372 #define APRXS_ELNA_IDX_ANT1(rxh, rev, min_rev) \ 3373 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3374 (rxh)->ge87_1.PHYRXSTATUS[APRXS_ELNA_IDX_ANT1_POS(rev)] : \ 3375 (rxh)->ge85.PHYRXSTATUS[APRXS_ELNA_IDX_ANT1_POS(rev)]) & \ 3376 APRXS_ELNA_IDX_ANT1_MASK) >> APRXS_ELNA_IDX_ANT1_SHIFT) 3377 3378 // RX TIA INDEX ANT0 LO 3379 #define APRXS_TIA_IDX_ANT0_POS(rev) APRXS_WD16_L_POS(rev) 3380 #define APRXS_TIA_IDX_ANT0_MASK 0x1Cu 3381 #define APRXS_TIA_IDX_ANT0_SHIFT 2u 3382 #define APRXS_TIA_IDX_ANT0(rxh, rev, min_rev) \ 3383 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3384 (rxh)->ge87_1.PHYRXSTATUS[APRXS_TIA_IDX_ANT0_POS(rev)] : \ 3385 (rxh)->ge85.PHYRXSTATUS[APRXS_TIA_IDX_ANT0_POS(rev)]) & \ 3386 APRXS_TIA_IDX_ANT0_MASK) >> APRXS_TIA_IDX_ANT0_SHIFT) 3387 3388 // RX TIA INDEX ANT1 LO 3389 #define APRXS_TIA_IDX_ANT1_POS(rev) APRXS_WD18_L_POS(rev) 3390 #define APRXS_TIA_IDX_ANT1_MASK 0x1Cu 3391 #define APRXS_TIA_IDX_ANT1_SHIFT 2u 3392 #define APRXS_TIA_IDX_ANT1(rxh, rev, min_rev) \ 3393 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3394 (rxh)->ge87_1.PHYRXSTATUS[APRXS_TIA_IDX_ANT1_POS(rev)] : \ 3395 (rxh)->ge85.PHYRXSTATUS[APRXS_TIA_IDX_ANT1_POS(rev)]) & \ 3396 APRXS_TIA_IDX_ANT1_MASK) >> APRXS_TIA_IDX_ANT1_SHIFT) 3397 3398 // RX VSW INDEX ANT0 3399 #define APRXS_VSW_IDX_ANT0_POS(rev) APRXS_WD20_L_POS(rev) 3400 #define APRXS_VSW_IDX_ANT0_MASK 0x8u 3401 #define APRXS_VSW_IDX_ANT0_SHIFT 3u 3402 #define APRXS_VSW_IDX_ANT0(rxh, rev, min_rev) \ 3403 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3404 (rxh)->ge87_1.PHYRXSTATUS[APRXS_VSW_IDX_ANT0_POS(rev)] : \ 3405 (rxh)->ge85.PHYRXSTATUS[APRXS_VSW_IDX_ANT0_POS(rev)]) & \ 3406 APRXS_VSW_IDX_ANT0_MASK) >> APRXS_VSW_IDX_ANT0_SHIFT) 3407 3408 // RX VSW INDEX ANT1 3409 #define APRXS_VSW_IDX_ANT1_POS(rev) APRXS_WD20_L_POS(rev) 3410 #define APRXS_VSW_IDX_ANT1_MASK 0x80u 3411 #define APRXS_VSW_IDX_ANT1_SHIFT 7u 3412 #define APRXS_VSW_IDX_ANT1(rxh, rev, min_rev) \ 3413 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3414 (rxh)->ge87_1.PHYRXSTATUS[APRXS_VSW_IDX_ANT1_POS(rev)] : \ 3415 (rxh)->ge85.PHYRXSTATUS[APRXS_VSW_IDX_ANT1_POS(rev)]) & \ 3416 APRXS_VSW_IDX_ANT1_MASK) >> APRXS_VSW_IDX_ANT1_SHIFT) 3417 3418 // RSSI fractional bits 3419 #define APRXS_RXPWR_FRAC_POS(rev) APRXS_WD4_L_POS(rev) 3420 #define APRXS_RXPWR_FRAC_MASK 0xFFu 3421 #define APRXS_RXPWR_FRAC(rxh, rev, min_rev) \ 3422 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3423 (rxh)->ge87_1.PHYRXSTATUS[APRXS_RXPWR_FRAC_POS(rev)] : \ 3424 (rxh)->ge85.PHYRXSTATUS[APRXS_RXPWR_FRAC_POS(rev)]) & \ 3425 APRXS_RXPWR_FRAC_MASK) 3426 3427 // Ucode overwrites ClipCount with GILTF 3428 #define APRXS_GILTF_POS(rev) APRXS_WD4_H_POS(rev) 3429 #define APRXS_GILTF_MASK 0x18u 3430 #define APRXS_GILTF_SHIFT 3u 3431 #define APRXS_GILTF(rxh, rev, min_rev) \ 3432 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3433 (rxh)->ge87_1.PHYRXSTATUS[APRXS_GILTF_POS(rev)] : \ 3434 (rxh)->ge85.PHYRXSTATUS[APRXS_GILTF_POS(rev)]) & \ 3435 APRXS_GILTF_MASK) >> APRXS_GILTF_SHIFT) 3436 3437 #define APRXS_DYNBWINNONHT_POS(rev) APRXS_WD4_H_POS(rev) 3438 #define APRXS_DYNBWINNONHT_MASK 0x20u 3439 #define APRXS_DYNBWINNONHT_SHIFT 5u 3440 #define APRXS_DYNBWINNONHT(rxh, rev, min_rev) \ 3441 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3442 (rxh)->ge87_1.PHYRXSTATUS[APRXS_DYNBWINNONHT_POS(rev)] : \ 3443 (rxh)->ge85.PHYRXSTATUS[APRXS_DYNBWINNONHT_POS(rev)]) & \ 3444 APRXS_DYNBWINNONHT_MASK) >> APRXS_DYNBWINNONHT_SHIFT) 3445 3446 #define APRXS_MCSSQSNR0_POS(rev) APRXS_WD5_L_POS(rev) 3447 #define APRXS_MCSSQSNR0_MASK 0xFFu 3448 #define APRXS_MCSSQSNR0(rxh, rev, min_rev) \ 3449 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3450 (rxh)->ge87_1.PHYRXSTATUS[APRXS_MCSSQSNR0_POS(rev)] : \ 3451 (rxh)->ge85.PHYRXSTATUS[APRXS_MCSSQSNR0_POS(rev)]) & \ 3452 APRXS_MCSSQSNR0_MASK) 3453 3454 #define APRXS_MCSSQSNR1_POS(rev) APRXS_WD5_H_POS(rev) 3455 #define APRXS_MCSSQSNR1_MASK 0xFFu 3456 #define APRXS_MCSSQSNR1(rxh, rev, min_rev) \ 3457 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3458 (rxh)->ge87_1.PHYRXSTATUS[APRXS_MCSSQSNR1_POS(rev)] : \ 3459 (rxh)->ge85.PHYRXSTATUS[APRXS_MCSSQSNR1_POS(rev)]) & \ 3460 APRXS_MCSSQSNR1_MASK) 3461 3462 #define APRXS_MCSSQSNR2_POS(rev) APRXS_WD6_L_POS(rev) 3463 #define APRXS_MCSSQSNR2_MASK 0xFFu 3464 #define APRXS_MCSSQSNR2(rxh, rev, min_rev) \ 3465 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3466 (rxh)->ge87_1.PHYRXSTATUS[APRXS_MCSSQSNR2_POS(rev)] : \ 3467 (rxh)->ge85.PHYRXSTATUS[APRXS_MCSSQSNR2_POS(rev)]) & \ 3468 APRXS_MCSSQSNR2_MASK) 3469 3470 #define APRXS_CHBWINNONHT_POS(rev) APRXS_WD8_H_POS(rev) 3471 #define APRXS_CHBWINNONHT_MASK 0x3u 3472 #define APRXS_CHBWINNONHT(rxh, rev, min_rev) \ 3473 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3474 (rxh)->ge87_1.PHYRXSTATUS[APRXS_CHBWINNONHT_POS(rev)] : \ 3475 (rxh)->ge85.PHYRXSTATUS[APRXS_CHBWINNONHT_POS(rev)]) & \ 3476 APRXS_CHBWINNONHT_MASK) 3477 3478 // User type 3479 #define APRXS_USTY_POS(rev) APRXS_WD23_H_POS(rev) 3480 #define APRXS_USTY_MASK 0xE0u 3481 #define APRXS_USTY_SHIFT 0x5u 3482 #define APRXS_USTY(rxh, rev, min_rev) \ 3483 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3484 (rxh)->ge87_1.PHYRXSTATUS[APRXS_USTY_POS(rev)] : \ 3485 (rxh)->ge85.PHYRXSTATUS[APRXS_USTY_POS(rev)]) & \ 3486 APRXS_USTY_MASK) >> APRXS_USTY_SHIFT) 3487 3488 // 11ax frame format 3489 #define APRXS_AXFF_POS(rev) APRXS_WD20_H_POS(rev) 3490 #define APRXS_AXFF_MASK 0x7u 3491 #define APRXS_AXFF(rxh, rev, min_rev) \ 3492 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3493 (rxh)->ge87_1.PHYRXSTATUS[APRXS_AXFF_POS(rev)] : \ 3494 (rxh)->ge85.PHYRXSTATUS[APRXS_AXFF_POS(rev)]) & \ 3495 APRXS_AXFF_MASK) 3496 3497 // MCS 3498 #define APRXS_AXMCS_POS(rev) APRXS_WD21_H_POS(rev) 3499 #define APRXS_AXMCS_MASK 0xFu 3500 #define APRXS_AXMCS(rxh, rev, min_rev) \ 3501 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3502 (rxh)->ge87_1.PHYRXSTATUS[APRXS_AXMCS_POS(rev)] : \ 3503 (rxh)->ge85.PHYRXSTATUS[APRXS_AXMCS_POS(rev)]) & \ 3504 APRXS_AXMCS_MASK) 3505 3506 // Coding 3507 #define APRXS_CODING_POS(rev) APRXS_WD21_H_POS(rev) 3508 #define APRXS_CODING_MASK 0x10u 3509 #define APRXS_CODING_SHIFT 4u 3510 #define APRXS_CODING(rxh, rev, min_rev) \ 3511 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3512 (rxh)->ge87_1.PHYRXSTATUS[APRXS_CODING_POS(rev)] : \ 3513 (rxh)->ge85.PHYRXSTATUS[APRXS_CODING_POS(rev)]) & \ 3514 APRXS_CODING_MASK) >> APRXS_CODING_SHIFT) 3515 3516 // STAID 3517 #define APRXS_AX_STAID_L_POS(rev) APRXS_WD22_L_POS(rev) 3518 #define APRXS_AX_STAID_L_MASK 0xFFu 3519 #define APRXS_AX_STAID_L(rxh, rev, min_rev) \ 3520 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3521 (rxh)->ge87_1.PHYRXSTATUS[APRXS_AX_STAID_L_POS(rev)] : \ 3522 (rxh)->ge85.PHYRXSTATUS[APRXS_AX_STAID_L_POS(rev)]) & \ 3523 APRXS_AX_STAID_L_MASK) 3524 3525 #define APRXS_AX_STAID_H_POS(rev) APRXS_WD22_H_POS(rev) 3526 #define APRXS_AX_STAID_H_MASK 0x03u 3527 #define APRXS_AX_STAID_H(rxh, rev, min_rev) \ 3528 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3529 (rxh)->ge87_1.PHYRXSTATUS[APRXS_AX_STAID_H_POS(rev)] : \ 3530 (rxh)->ge85.PHYRXSTATUS[APRXS_AX_STAID_H_POS(rev)]) & \ 3531 APRXS_AX_STAID_H_MASK) 3532 3533 #define APRXS_AX_STAID(rxh, rev, min_rev) ((APRXS_AX_STAID_H(rxh, rev, min_rev) << 1) |\ 3534 APRXS_AX_STAID_L(rxh, rev, min_rev)) 3535 3536 // NSTS 3537 #define APRXS_NSTS_POS(rev) APRXS_WD22_H_POS(rev) 3538 #define APRXS_NSTS_MASK 0x38u 3539 #define APRXS_NSTS_SHIFT 3u 3540 #define APRXS_NSTS(rxh, rev, min_rev) \ 3541 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3542 (rxh)->ge87_1.PHYRXSTATUS[APRXS_DCM_POS(rev)] : \ 3543 (rxh)->ge85.PHYRXSTATUS[APRXS_DCM_POS(rev)]) & \ 3544 APRXS_NSTS_MASK) >> APRXS_NSTS_SHIFT) 3545 3546 // TXBF 3547 #define APRXS_TXBF_POS(rev) APRXS_WD22_H_POS(rev) 3548 #define APRXS_TXBF_MASK 0x40u 3549 #define APRXS_TXBF_SHIFT 6u 3550 #define APRXS_TXBF(rxh, rev, min_rev) \ 3551 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3552 (rxh)->ge87_1.PHYRXSTATUS[APRXS_TXBF_POS(rev)] : \ 3553 (rxh)->ge85.PHYRXSTATUS[APRXS_TXBF_POS(rev)]) & \ 3554 APRXS_TXBF_MASK) >> APRXS_TXBF_SHIFT) 3555 3556 //DCM 3557 #define APRXS_DCM_POS(rev) APRXS_WD22_H_POS(rev) 3558 #define APRXS_DCM_MASK 0x80u 3559 #define APRXS_DCM_SHIFT 7u 3560 #define APRXS_DCM(rxh, rev, min_rev) \ 3561 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3562 (rxh)->ge87_1.PHYRXSTATUS[APRXS_DCM_POS(rev)] : \ 3563 (rxh)->ge85.PHYRXSTATUS[APRXS_DCM_POS(rev)]) & \ 3564 APRXS_DCM_MASK) >> APRXS_DCM_SHIFT) 3565 3566 // RU Offset 3567 #define APRXS_AX_RUALLOC_POS(rev) APRXS_WD23_L_POS(rev) 3568 #define APRXS_AX_RUALLOC_MASK 0x7Fu 3569 #define APRXS_AX_RUALLOC_SHIFT 0u 3570 #define APRXS_AX_RUALLOC(rxh, rev, min_rev) \ 3571 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3572 (rxh)->ge87_1.PHYRXSTATUS[APRXS_AX_RUALLOC_POS(rev)] : \ 3573 (rxh)->ge85.PHYRXSTATUS[APRXS_AX_RUALLOC_POS(rev)]) & \ 3574 APRXS_AX_RUALLOC_MASK) >> APRXS_AX_RUALLOC_SHIFT) 3575 3576 #define APRXS_PE_L_POS(rev) APRXS_WD23_L_POS(rev) 3577 #define APRXS_PE_L_MASK 0x80u 3578 #define APRXS_PE_L_SHIFT 7u 3579 #define APRXS_PE_L(rxh, rev, min_rev) \ 3580 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3581 (rxh)->ge87_1.PHYRXSTATUS[APRXS_PE_L_POS(rev)] : \ 3582 (rxh)->ge85.PHYRXSTATUS[APRXS_PE_L_POS(rev)]) & \ 3583 APRXS_PE_L_MASK) >> APRXS_PE_L_SHIFT) 3584 3585 #define APRXS_PE_H_POS(rev) APRXS_WD23_H_POS(rev) 3586 #define APRXS_PE_H_MASK 0x3u 3587 #define APRXS_PE_H(rxh, rev, min_rev) \ 3588 ((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3589 (rxh)->ge87_1.PHYRXSTATUS[APRXS_PE_H_POS(rev)] : \ 3590 (rxh)->ge85.PHYRXSTATUS[APRXS_PE_H_POS(rev)]) & \ 3591 APRXS_PE_H_MASK) 3592 3593 #define APRXS_PE(rxh, rev, rev_min) \ 3594 ((APRXS_PE_H(rxh, rev, rev_min) << 1) | APRXS_PE_L(rxh, rev, rev_min)) 3595 3596 #define APRXS_RU_POS(rev) APRXS_WD23_H_POS(rev) 3597 #define APRXS_RU_MASK 0x1Cu 3598 #define APRXS_RU_SHIFT 2u 3599 #define APRXS_RU(rxh, rev, min_rev) \ 3600 (((D11REV_MAJ_MIN_GE(rev, min_rev, 87, 1) ? \ 3601 (rxh)->ge87_1.PHYRXSTATUS[APRXS_RU_POS(rev)] : \ 3602 (rxh)->ge85.PHYRXSTATUS[APRXS_RU_POS(rev)]) & \ 3603 APRXS_RU_MASK) >> APRXS_RU_SHIFT) 3604 3605 #endif /* _d11_autophyrxsts_ */ 3606 3607 #if defined(AUTO_PHYRXSTS) 3608 #define AUTO_PHYRXSTS_ENAB() 1u 3609 #else 3610 #define AUTO_PHYRXSTS_ENAB() 0u 3611 #endif /* AUTO_PHYRXSTS */ 3612 3613 /* PhyRxStatus_0: */ 3614 #define PRXS0_FT_MASK 0x0003u /**< [PRE-HE] NPHY only: CCK, OFDM, HT, VHT */ 3615 #define PRXS0_CLIP_MASK 0x000Cu /**< NPHY only: clip count adjustment steps by AGC */ 3616 #define PRXS0_CLIP_SHIFT 2u /**< SHIFT bits for clip count adjustment */ 3617 #define PRXS0_UNSRATE 0x0010u /**< PHY received a frame with unsupported rate */ 3618 #define PRXS0_UNSRATE_SHIFT 4u 3619 #define PRXS0_RXANT_UPSUBBAND 0x0020u /**< GPHY: rx ant, NPHY: upper sideband */ 3620 #define PRXS0_LCRS 0x0040u /**< CCK frame only: lost crs during cck frame reception */ 3621 #define PRXS0_SHORTH 0x0080u /**< Short Preamble */ 3622 #define PRXS0_SHORTH_SHIFT 7u 3623 #define PRXS0_PLCPFV 0x0100u /**< PLCP violation */ 3624 #define PRXS0_PLCPFV_SHIFT 8u 3625 #define PRXS0_PLCPHCF 0x0200u /**< PLCP header integrity check failed */ 3626 #define PRXS0_PLCPHCF_SHIFT 9u 3627 #define PRXS0_GAIN_CTL 0x4000u /**< legacy PHY gain control */ 3628 #define PRXS0_ANTSEL_MASK 0xF000u /**< NPHY: Antennas used for received frame, bitmask */ 3629 #define PRXS0_ANTSEL_SHIFT 12u /**< SHIFT bits for Antennas used for received frame */ 3630 #define PRXS0_PPDU_MASK 0x1000u /**< PPDU type SU/MU */ 3631 3632 /* subfield PRXS0_FT_MASK [PRXS0_PRE_HE_FT_MASK] */ 3633 #define PRXS0_CCK 0x0000u 3634 #define PRXS0_OFDM 0x0001u /**< valid only for G phy, use rxh->RxChan for A phy */ 3635 #define PRXS0_PREN 0x0002u 3636 #define PRXS0_STDN 0x0003u 3637 3638 /* subfield PRXS0_ANTSEL_MASK */ 3639 #define PRXS0_ANTSEL_0 0x0u /**< antenna 0 is used */ 3640 #define PRXS0_ANTSEL_1 0x2u /**< antenna 1 is used */ 3641 #define PRXS0_ANTSEL_2 0x4u /**< antenna 2 is used */ 3642 #define PRXS0_ANTSEL_3 0x8u /**< antenna 3 is used */ 3643 3644 /* PhyRxStatus_1: */ 3645 #define PRXS1_JSSI_MASK 0x00FFu 3646 #define PRXS1_JSSI_SHIFT 0u 3647 #define PRXS1_SQ_MASK 0xFF00u 3648 #define PRXS1_SQ_SHIFT 8u 3649 #define PRXS1_COREMAP 0x000Fu /**< core enable bits for core 0/1/2/3 */ 3650 #define PRXS1_ANTCFG 0x00F0u /**< anttenna configuration bits */ 3651 3652 #define PHY_COREMAP_LT85(rxh, rev) \ 3653 ((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_1) : \ 3654 D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_1)) & \ 3655 PRXS1_COREMAP) 3656 #define PHY_COREMAP(rev, rev_min, rxh) (AUTO_PHYRXSTS_ENAB() ? \ 3657 APRXS_COREMASK(rxh, rev, rev_min) : PHY_COREMAP_LT85(rxh, rev)) 3658 3659 #define PHY_ANTMAP_LT85(rxh, corerev) \ 3660 (((D11REV_GE(corerev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_1) : \ 3661 D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_1)) & \ 3662 PRXS1_ANTCFG) >> 4) 3663 #define PHY_ANTMAP(rev, rev_min, rxh) (AUTO_PHYRXSTS_ENAB() ? \ 3664 APRXS_ANTCFG(rxh, rev, rev_min) : PHY_ANTMAP_LT85(rxh, rev)) 3665 3666 /* nphy PhyRxStatus_1: */ 3667 #define PRXS1_nphy_PWR0_MASK 0x00FF 3668 #define PRXS1_nphy_PWR1_MASK 0xFF00 3669 3670 /* PhyRxStatus_2: */ 3671 #define PRXS2_LNAGN_MASK 0xC000 3672 #define PRXS2_LNAGN_SHIFT 14 3673 #define PRXS2_PGAGN_MASK 0x3C00 3674 #define PRXS2_PGAGN_SHIFT 10 3675 #define PRXS2_FOFF_MASK 0x03FF 3676 3677 /* nphy PhyRxStatus_2: */ 3678 #define PRXS2_nphy_SQ_ANT0 0x000F /**< nphy overall signal quality for antenna 0 */ 3679 #define PRXS2_nphy_SQ_ANT1 0x00F0 /**< nphy overall signal quality for antenna 0 */ 3680 #define PRXS2_nphy_cck_SQ 0x00FF /**< bphy signal quality(when FT field is 0) */ 3681 #define PRXS3_nphy_SSQ_MASK 0xFF00 /**< spatial conditioning of the two receive channels */ 3682 #define PRXS3_nphy_SSQ_SHIFT 8 3683 3684 /* PhyRxStatus_3: */ 3685 #define PRXS3_DIGGN_MASK 0x1800 3686 #define PRXS3_DIGGN_SHIFT 11 3687 #define PRXS3_TRSTATE 0x0400 3688 3689 /* nphy PhyRxStatus_3: */ 3690 #define PRXS3_nphy_MMPLCPLen_MASK 0x0FFF /**< Mixed-mode preamble PLCP length */ 3691 #define PRXS3_nphy_MMPLCP_RATE_MASK 0xF000 /**< Mixed-mode preamble rate field */ 3692 #define PRXS3_nphy_MMPLCP_RATE_SHIFT 12 3693 3694 /* HTPHY Rx Status defines */ 3695 /* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */ 3696 #define PRXS0_BAND 0x0400 /**< 0 = 2.4G, 1 = 5G */ 3697 #define PRXS0_RSVD 0x0800 /**< reserved; set to 0 */ 3698 #define PRXS0_UNUSED 0xF000 /**< unused and not defined; set to 0 */ 3699 3700 /* htphy PhyRxStatus_1: */ 3701 #define PRXS1_HTPHY_MMPLCPLenL_MASK 0xFF00 /**< Mixmode PLCP Length low byte mask */ 3702 3703 /* htphy PhyRxStatus_2: */ 3704 #define PRXS2_HTPHY_MMPLCPLenH_MASK 0x000F /**< Mixmode PLCP Length high byte maskw */ 3705 #define PRXS2_HTPHY_MMPLCH_RATE_MASK 0x00F0 /**< Mixmode PLCP rate mask */ 3706 #define PRXS2_HTPHY_RXPWR_ANT0 0xFF00 /**< Rx power on core 0 */ 3707 3708 /* htphy PhyRxStatus_3: */ 3709 #define PRXS3_HTPHY_RXPWR_ANT1 0x00FF /**< Rx power on core 1 */ 3710 #define PRXS3_HTPHY_RXPWR_ANT2 0xFF00 /**< Rx power on core 2 */ 3711 3712 /* htphy PhyRxStatus_4: */ 3713 #define PRXS4_HTPHY_RXPWR_ANT3 0x00FF /**< Rx power on core 3 */ 3714 #define PRXS4_HTPHY_CFO 0xFF00 /**< Coarse frequency offset */ 3715 3716 /* htphy PhyRxStatus_5: */ 3717 #define PRXS5_HTPHY_FFO 0x00FF /**< Fine frequency offset */ 3718 #define PRXS5_HTPHY_AR 0xFF00 /**< Advance Retard */ 3719 3720 /* ACPHY RxStatus defs */ 3721 3722 /* ACPHY PhyRxStatus_0: */ 3723 #define PRXS0_ACPHY_FT_MASK 0x0003 /**< CCK, OFDM, HT, VHT */ 3724 #define PRXS0_ACPHY_CLIP_MASK 0x000C /**< clip count adjustment steps by AGC */ 3725 #define PRXS0_ACPHY_CLIP_SHIFT 2 3726 #define PRXS0_ACPHY_UNSRATE 0x0010 /**< PHY received a frame with unsupported rate */ 3727 #define PRXS0_ACPHY_BAND5G 0x0020 /**< Rx Band indication: 0 -> 2G, 1 -> 5G */ 3728 #define PRXS0_ACPHY_LCRS 0x0040 /**< CCK frame only: lost crs during cck frame reception */ 3729 #define PRXS0_ACPHY_SHORTH 0x0080 /**< Short Preamble (CCK), GF preamble (HT) */ 3730 #define PRXS0_ACPHY_PLCPFV 0x0100 /**< PLCP violation */ 3731 #define PRXS0_ACPHY_PLCPHCF 0x0200 /**< PLCP header integrity check failed */ 3732 #define PRXS0_ACPHY_MFCRS 0x0400 /**< Matched Filter CRS fired */ 3733 #define PRXS0_ACPHY_ACCRS 0x0800 /**< Autocorrelation CRS fired */ 3734 #define PRXS0_ACPHY_SUBBAND_MASK 0xF000 /**< FinalBWClassification: 3735 * lower nibble Bitfield of sub-bands occupied by Rx frame 3736 */ 3737 /* ACPHY PhyRxStatus_1: */ 3738 #define PRXS1_ACPHY_ANT_CORE0 0x0001 /* Antenna Config for core 0 */ 3739 #define PRXS1_ACPHY_SUBBAND_MASK_GEN2 0xFF00 /**< FinalBWClassification: 3740 * lower byte Bitfield of sub-bands occupied by Rx frame 3741 */ 3742 #define PRXS0_ACPHY_SUBBAND_SHIFT 12 3743 #define PRXS1_ACPHY_SUBBAND_SHIFT_GEN2 8 3744 3745 /* acphy PhyRxStatus_3: */ 3746 #define PRXS2_ACPHY_RXPWR_ANT0 0xFF00 /**< Rx power on core 1 */ 3747 #define PRXS3_ACPHY_RXPWR_ANT1 0x00FF /**< Rx power on core 1 */ 3748 #define PRXS3_ACPHY_RXPWR_ANT2 0xFF00 /**< Rx power on core 2 */ 3749 #define PRXS3_ACPHY_SNR_ANT0 0xFF00 /* SNR on core 0 */ 3750 3751 /* acphy PhyRxStatus_4: */ 3752 /** FinalBWClassification:upper nibble of sub-bands occupied by Rx frame */ 3753 #define PRXS4_ACPHY_SUBBAND_MASK 0x000F 3754 #define PRXS4_ACPHY_RXPWR_ANT3 0x00FF /**< Rx power on core 3 */ 3755 #define PRXS4_ACPHY_SNR_ANT1 0xFF00 /* SNR on core 1 */ 3756 3757 #define PRXS5_ACPHY_CHBWINNONHT_MASK 0x0003 3758 #define PRXS5_ACPHY_CHBWINNONHT_20MHZ 0 3759 #define PRXS5_ACPHY_CHBWINNONHT_40MHZ 1 3760 #define PRXS5_ACPHY_CHBWINNONHT_80MHZ 2 3761 #define PRXS5_ACPHY_CHBWINNONHT_160MHZ 3 /* includes 80+80 */ 3762 #define PRXS5_ACPHY_DYNBWINNONHT_MASK 0x0004 3763 3764 /** Get Rx power on core 0 */ 3765 #define ACPHY_RXPWR_ANT0(rxs) (((rxs)->lt80.PhyRxStatus_2 & PRXS2_ACPHY_RXPWR_ANT0) >> 8) 3766 /** Get Rx power on core 1 */ 3767 #define ACPHY_RXPWR_ANT1(rxs) ((rxs)->lt80.PhyRxStatus_3 & PRXS3_ACPHY_RXPWR_ANT1) 3768 /** Get Rx power on core 2 */ 3769 #define ACPHY_RXPWR_ANT2(rxs) (((rxs)->lt80.PhyRxStatus_3 & PRXS3_ACPHY_RXPWR_ANT2) >> 8) 3770 /** Get Rx power on core 3 */ 3771 #define ACPHY_RXPWR_ANT3(rxs) ((rxs)->lt80.PhyRxStatus_4 & PRXS4_ACPHY_RXPWR_ANT3) 3772 3773 /** MCSSQSNR location access. MCSSQ usage is limited by chip specific impl, 3774 * and there is no way to commonize these status location yet. 3775 * TODO: When the storage locations are settled we need to revisit 3776 * this defs controls. 3777 */ 3778 3779 /* exception handling */ 3780 #ifdef PHY_CORE_MAX 3781 #if PHY_CORE_MAX > 4 3782 #error "PHY_CORE_MAX is exceeded more than MCSSQSNR defs (4)" 3783 #endif 3784 #endif /* PHY_CORE_MAX */ 3785 3786 /* rev 48/55/59 are obsoleted for SNR in trunk */ 3787 #define D11_PRXS_MCSSQ_SNR_SUPPORT(corerev) (D11REV_GE((corerev), 80)) 3788 3789 #define ACPHY_SNR_MASK (0xFF) 3790 #define ACPHY_SNR_SHIFT (8) 3791 3792 #define PRXS5_ACPHY_DYNBWINNONHT(rxs) ((rxs)->lt80.PhyRxStatus_5 & PRXS5_ACPHY_DYNBWINNONHT_MASK) 3793 #define PRXS5_ACPHY_CHBWINNONHT(rxs) ((rxs)->lt80.PhyRxStatus_5 & PRXS5_ACPHY_CHBWINNONHT_MASK) 3794 3795 #define D11N_MMPLCPLen(rxs) ((rxs)->lt80.PhyRxStatus_3 & PRXS3_nphy_MMPLCPLen_MASK) 3796 #define D11HT_MMPLCPLen(rxs) ((((rxs)->lt80.PhyRxStatus_1 & PRXS1_HTPHY_MMPLCPLenL_MASK) >> 8) | \ 3797 (((rxs)->lt80.PhyRxStatus_2 & PRXS2_HTPHY_MMPLCPLenH_MASK) << 8)) 3798 3799 /* REV80 Defintions (corerev >= 80) */ 3800 3801 /** Dma_flags Masks */ 3802 #define RXS_PHYRXST_VALID_REV_GE80 0x02 3803 3804 /** Get RxStatus1 */ 3805 #define RXSTATUS1_REV_GE87_1(rxs) ((rxs)->ge87_1.RxStatus1) 3806 #define RXSTATUS1_REV_GE80(rxs) ((rxs)->ge80.RxStatus1) 3807 #define RXSTATUS1_REV_LT80(rxs) ((rxs)->lt80.RxStatus1) 3808 3809 #define PHY_RXSTATUS1(corerev, corerev_minor, rxs) \ 3810 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? RXSTATUS1_REV_GE87_1(rxs) : \ 3811 D11REV_GE(corerev, 80) ? RXSTATUS1_REV_GE80(rxs) : \ 3812 RXSTATUS1_REV_LT80(rxs)) 3813 3814 /* (FT Mask) PhyRxStatus_0: */ 3815 #define PRXS0_FT_MASK_REV_LT80 PRXS0_FT_MASK /**< (corerev < 80) frame type field mask */ 3816 3817 #define PRXS0_FT_SHIFT_REV_GE80 8 3818 #define PRXS0_FT_MASK_REV_GE80 0x0700 /** 3819 * (corerev >= 80) frame type field mask. 3820 * 3821 * 0 = CCK, 1 = 11a/g legacy OFDM, 3822 * 2 = HT, 3 = VHT, 4 = 11ah, 5 = HE, 3823 * 6-15 Rsvd. 3824 */ 3825 3826 /* * 3827 * Macro to find Frame type from RX Hdr based on corerev. 3828 * 3829 * Note: From rev80 onwards frame type is indicated only 3830 * in the phyrxstatus, which is valid only for the last 3831 * MPDU of an AMPDU. Since FT is required for every MPDU, 3832 * frametype for core-revs >= 80, shall be 3833 * provided in bits (8:10) of MuRate field in RXH. 3834 * 3835 */ 3836 #define D11PPDU_FT(rxh, rev) (\ 3837 (D11REV_GE(rev, 80) ? \ 3838 ((D11RXHDR_ACCESS_VAL(rxh, rev, 0, MuRate) & PRXS_FT_MASK(rev)) >> \ 3839 (PRXS0_FT_SHIFT_REV_GE80)) : \ 3840 (D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0) & PRXS_FT_MASK(rev)))) 3841 3842 #define PRXS_UNSRATE_LT85(rxh, rev) \ 3843 (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_0) : \ 3844 D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0)) & \ 3845 PRXS0_UNSRATE) >> PRXS0_UNSRATE_SHIFT) 3846 3847 #define PRXS_UNSRATE(rxh, rev, min_rev) (AUTO_PHYRXSTS_ENAB() ? \ 3848 APRXS_UNSRATE(rxh, rev, min_rev) : PRXS_UNSRATE_LT85(rxh, rev)) 3849 3850 // 1: short (or GF) preamble, 0: long (or MM) preamble 3851 #define PRXS_SHORTH_LT85(rxh, rev) \ 3852 (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_0) : \ 3853 D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0)) & \ 3854 PRXS0_SHORTH) >> PRXS0_SHORTH_SHIFT) 3855 #define PRXS_SHORTH(rxh, rev, min_rev) \ 3856 (AUTO_PHYRXSTS_ENAB() ? APRXS_SHORTH(rxh, rev, min_rev) : \ 3857 PRXS_SHORTH_LT85(rxh, rev)) 3858 3859 #define PRXS_PLCPFV_LT85(rxh, rev) \ 3860 (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_0) : \ 3861 D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0)) & \ 3862 PRXS0_PLCPFV) >> PRXS0_PLCPFV_SHIFT) 3863 #define PRXS_PLCPFV(rxh, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \ 3864 APRXS_PLCPFV(rxh, rev, rev_min) : PRXS_PLCPFV_LT85(rxh, rev)) 3865 3866 #define PRXS_PLCPHCF_LT85(rxh, rev) \ 3867 (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_0) : \ 3868 D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0)) & \ 3869 PRXS0_PLCPHCF) >> PRXS0_PLCPHCF_SHIFT) 3870 #define PRXS_PLCPHCF(rxh, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \ 3871 APRXS_PLCPHCF(rxh, rev, rev_min) : PRXS_PLCPHCF_LT85(rxh, rev)) 3872 3873 // final BW classification 3874 #define PRXS_SUBBAND_ACPHY(rxh, rev, rev_min) \ 3875 (((D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_0) & \ 3876 PRXS0_ACPHY_SUBBAND_MASK) >> PRXS0_ACPHY_SUBBAND_SHIFT) | \ 3877 ((D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_4) & \ 3878 PRXS4_ACPHY_SUBBAND_MASK) << 4)) 3879 #define PRXS_SUBBAND_ACPHY2(rxh, rev, rev_min) \ 3880 (((D11REV_GE(rev, 80) ? D11RXHDR_GE80_ACCESS_VAL(rxh, PhyRxStatus_1) : \ 3881 D11RXHDR_LT80_ACCESS_VAL(rxh, PhyRxStatus_1)) & PRXS1_ACPHY2_SUBBAND_MASK) >> \ 3882 PRXS1_ACPHY2_SUBBAND_SHIFT) 3883 3884 #define PRXS_SUBBAND(rxh, rev, rev_min, phyrev) (AUTO_PHYRXSTS_ENAB() ? \ 3885 APRXS_SUBBAND(rxh, rev, rev_min) : (ACREV_GE(phyrev, 32) ? \ 3886 PRXS_SUBBAND_ACPHY2(rxh, rev, rev_min) : \ 3887 PRXS_SUBBAND_ACPHY(rxh, rev, rev_min))) 3888 3889 /* Macros to access MCS, NSTS and MU valididity from MuRate field in corerev > 80 RXH */ 3890 #define RXS_MU_VALID_MASK_REV80 0x0080 3891 #define RXS_MU_VALID_SHIFT_REV80 7 3892 #define RXS_MCS_MASK_REV80 0x000F 3893 #define RXS_MCS_SHIFT_REV80 0 3894 #define RXS_NSTS_MASK_REV80 0x0070 3895 #define RXS_NSTS_SHIFT_REV80 4 3896 3897 #define D11PPDU_ISMU_REV80(rxh, corerev, corerev_minor) \ 3898 ((D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, MuRate) & \ 3899 (RXS_MU_VALID_MASK_REV80)) >> RXS_MU_VALID_SHIFT_REV80) 3900 #define D11RXHDR_GE80_GET_MCS(rxh, corerev, corerev_minor) \ 3901 ((D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, MuRate) & \ 3902 (RXS_MCS_MASK_REV80)) >> RXS_MCS_SHIFT_REV80) 3903 #define D11RXHDR_GE80_GET_NSTS(rxh, corerev, corerev_minor) \ 3904 ((D11RXHDR_ACCESS_VAL(rxh, corerev, corerev_minor, MuRate) & \ 3905 (RXS_NSTS_MASK_REV80)) >> RXS_NSTS_SHIFT_REV80) 3906 3907 /* subfield PRXS0_FT_MASK_REV_GE80 */ 3908 #define PRXS0_HE 0x0004 /**< HE frame type */ 3909 3910 /* (Corerev >= 80) PhyRxStatus_2: */ 3911 #define PRXS2_RXPWR_ANT0_REV_GE80 0x00FF /**< (corerev >= 80) Rx power on first antenna */ 3912 #define PRXS2_RXPWR_ANT1_REV_GE80 0xFF00 /**< (corerev >= 80) Rx power on second antenna */ 3913 3914 /* (Corerev >= 80) PhyRxStatus_3: */ 3915 #define PRXS3_RXPWR_ANT2_REV_GE80 0x00FF /**< (corerev >= 80) Rx power on third antenna */ 3916 #define PRXS3_RXPWR_ANT3_REV_GE80 0xFF00 /** 3917 * (corerev >= 80) Rx power on fourth antenna. 3918 * 3919 * Note: For PHY revs 3 and > 4, OCL Status 3920 * byte 0 will be reported if PHY register 3921 * OCL_RxStatus_Ctrl is set to 0x2 or 0x6. 3922 */ 3923 #define PRXS3_RXPWR_FRAC_REV_GE80 0xFFu 3924 3925 /** Get Rx power on ANT 0 */ 3926 #define RXPWR_ANT0_REV_GE80(rxs) ((rxs)->ge80.PhyRxStatus_2 & \ 3927 (PRXS2_RXPWR_ANT0_REV_GE80)) 3928 3929 #define PHY_RXPWR_ANT0(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \ 3930 APRXS_RXPWR_ANT0(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \ 3931 RXPWR_ANT0_REV_GE80(rxs) : ACPHY_RXPWR_ANT0(rxs))) 3932 3933 /** Get Rx power on ANT 1 */ 3934 #define RXPWR_ANT1_REV_GE80(rxs) (((rxs)->ge80.PhyRxStatus_2 & \ 3935 (PRXS2_RXPWR_ANT1_REV_GE80)) >> 8) 3936 3937 #define PHY_RXPWR_ANT1(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \ 3938 APRXS_RXPWR_ANT1(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \ 3939 RXPWR_ANT1_REV_GE80(rxs) : ACPHY_RXPWR_ANT1(rxs))) 3940 3941 /** Get Rx power on ANT 2 */ 3942 #define RXPWR_ANT2_REV_GE80(rxs) ((rxs)->ge80.PhyRxStatus_3 & \ 3943 (PRXS3_RXPWR_ANT2_REV_GE80)) 3944 3945 #define PHY_RXPWR_ANT2(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \ 3946 APRXS_RXPWR_ANT2(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \ 3947 RXPWR_ANT2_REV_GE80(rxs) : ACPHY_RXPWR_ANT2(rxs))) 3948 3949 /** Get Rx power on ANT 3 */ 3950 #define RXPWR_ANT3_REV_GE80(rxs) (((rxs)->ge80.PhyRxStatus_3 & \ 3951 (PRXS3_RXPWR_ANT3_REV_GE80)) >> 8) 3952 3953 #define PHY_RXPWR_ANT3(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \ 3954 APRXS_RXPWR_ANT3(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \ 3955 RXPWR_ANT3_REV_GE80(rxs) : ACPHY_RXPWR_ANT3(rxs))) 3956 3957 /* Get the following entries from RXStatus bytes 3958 * for RSSI compensation 3959 * based on factory calibration 3960 * TIA Index 3961 * eLNA Index 3962 * V_path Switch 3963 */ 3964 #define PHY_ELNA_IDX_ANT0_REV_GE85(corerev, corerev_min, rxs) \ 3965 APRXS_ELNA_IDX_ANT0(rxs, corerev, corerev_min) 3966 #define PHY_ELNA_IDX_ANT1_REV_GE85(corerev, corerev_min, rxs) \ 3967 APRXS_ELNA_IDX_ANT1(rxs, corerev, corerev_min) 3968 #define PHY_TIA_IDX_ANT0_REV_GE85(corerev, corerev_min, rxs) \ 3969 APRXS_TIA_IDX_ANT0(rxs, corerev, corerev_min) 3970 #define PHY_TIA_IDX_ANT1_REV_GE85(corerev, corerev_min, rxs) \ 3971 APRXS_TIA_IDX_ANT1(rxs, corerev, corerev_min) 3972 #define PHY_VSW_IDX_ANT0_REV_GE85(corerev, corerev_min, rxs) \ 3973 APRXS_VSW_IDX_ANT0(rxs, corerev, corerev_min) 3974 #define PHY_VSW_IDX_ANT1_REV_GE85(corerev, corerev_min, rxs) \ 3975 APRXS_VSW_IDX_ANT1(rxs, corerev, corerev_min) 3976 3977 /** Get RSSI fractional bits */ 3978 #define RXPWR_FRAC_REV_GE80(rxs) ((rxs)->ge80.PhyRxStatus_4 & \ 3979 (PRXS3_RXPWR_FRAC_REV_GE80)) 3980 3981 #define RXPWR_FRAC(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \ 3982 APRXS_RXPWR_FRAC(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \ 3983 RXPWR_FRAC_REV_GE80(rxs) : 0)) 3984 3985 /* HECAPPHY PhyRxStatus_4: */ 3986 #define PRXS4_DYNBWINNONHT_MASK_REV_GE80 0x1000 3987 #define PRXS4_DYNBWINNONHT_REV_GE80(rxs) ((rxs)->ge80.PhyRxStatus_4 & \ 3988 PRXS4_DYNBWINNONHT_MASK_REV_GE80) 3989 3990 #define PRXS_PHY_DYNBWINNONHT(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \ 3991 APRXS_DYNBWINNONHT(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \ 3992 PRXS4_DYNBWINNONHT_REV_GE80(rxs) : PRXS5_ACPHY_DYNBWINNONHT(rxs))) 3993 3994 /** (corerev >= 80) PhyRxStatus_5: MCSSQ SNR for core 0 and 1 */ 3995 #define PRXS5_MCSSQ_SHIFT (8u) 3996 #define PRXS5_MCSSQ_CORE0_REV_GE80 (0x00FF) 3997 #define PRXS5_MCSSQ_CORE1_REV_GE80 (0xFF00) 3998 3999 #define MCSSQ_SNR_ANT0_GE80(rxs) ((rxs)->ge80.PhyRxStatus_5 & PRXS5_MCSSQ_CORE0_REV_GE80) 4000 #define MCSSQ_SNR_ANT0(rxs, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \ 4001 APRXS_MCSSQSNR0(rxs, rev, rev_min) : \ 4002 ((rxs)->ge80.PhyRxStatus_5 & PRXS5_MCSSQ_CORE0_REV_GE80)) 4003 4004 #define MCSSQ_SNR_ANT1_GE80(rxs) (((rxs)->ge80.PhyRxStatus_5 & PRXS5_MCSSQ_CORE1_REV_GE80) \ 4005 >> PRXS5_MCSSQ_SHIFT) 4006 #define MCSSQ_SNR_ANT1(rxs, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \ 4007 APRXS_MCSSQSNR1(rxs, rev, rev_min) : \ 4008 (((rxs)->ge80.PhyRxStatus_5 & PRXS5_MCSSQ_CORE1_REV_GE80) \ 4009 >> PRXS5_MCSSQ_SHIFT)) 4010 4011 /** (corerev >= 80) PhyRxStatus_6: MCSSQ SNR for core 2 and 3 */ 4012 #define PRXS6_MCSSQ_SHIFT (8u) 4013 #define PRXS6_MCSSQ_CORE2_REV_GE80 (0x00FF) 4014 #define PRXS6_MCSSQ_CORE3_REV_GE80 (0xFF00) 4015 4016 #define MCSSQ_SNR_ANT2_GE80(rxs) (((rxs)->ge80.phyrxs_rem[0] & \ 4017 PRXS6_MCSSQ_CORE2_REV_GE80)) 4018 #define MCSSQ_SNR_ANT2(rxs, rev, rev_min) (AUTO_PHYRXSTS_ENAB() ? \ 4019 APRXS_MCSSQSNR2(rxs, rev, rev_min) : \ 4020 (((rxs)->ge80.phyrxs_rem[0] & PRXS6_MCSSQ_CORE2_REV_GE80))) 4021 4022 /* HECAPPHY PhyRxStatus_8 (part of phyrxs_rem[2]) : */ 4023 #define PRXS8_CHBWINNONHT_MASK_REV_GE80 0x0100 4024 #define PRXS8_CHBWINNONHT_REV_GE80(rxs) ((rxs)->ge80.phyrxs_rem[2] & \ 4025 PRXS8_CHBWINNONHT_MASK_REV_GE80) 4026 4027 #define PRXS_PHY_CHBWINNONHT(corerev, corerev_minor, rxs) (AUTO_PHYRXSTS_ENAB() ? \ 4028 APRXS_CHBWINNONHT(rxs, corerev, corerev_minor) : (D11REV_GE(corerev, 80) ? \ 4029 PRXS8_CHBWINNONHT_REV_GE80(rxs) : PRXS5_ACPHY_CHBWINNONHT(rxs))) 4030 4031 /* HE phyrxs_rem[4] */ 4032 #define PRXS_REM4_PE_MASK_REV80 0x0380 4033 #define PRXS_REM4_PE_SHIFT_REV80 7u 4034 #define PRXS_REM4_RU_TYPE_MASK_REV80 0x1c00 4035 #define PRXS_REM4_RU_TYPE_SHIFT_REV80 10u 4036 #define PRXS_REM4_NUM_USER_SHIFT_REV80 13u 4037 #define PRXS_REM4_NUM_USER_BIT_MASK_REV80 0xe000 4038 4039 /* HE phyrxs_rem[5] */ 4040 #define PRXS_REM5_GI_LTF_MASK_REV80 0x0003 4041 #define PRXS_REM5_GI_LTF_SHIFT_REV80 0u 4042 #define PRXS_REM5_11AX_FF_MASK_REV80 0x0700 4043 #define PRXS_REM5_11AX_FF_SHIFT_REV80 8u 4044 4045 /* HE phyrxs_rem[6] */ 4046 #define PRXS_REM6_MCS_MASK_REV80 0x0f00 4047 #define PRXS_REM6_MCS_SHIFT_REV80 8u 4048 #define PRXS_REM6_CODING_MASK_REV80 0x1000 4049 #define PRXS_REM6_CODING_SHIFT_REV80 12u 4050 4051 /* HE phyrxs_rem[7] */ 4052 #define PRXS_REM7_DCM_MASK_REV80 0x8000 4053 #define PRXS_REM7_DCM_SHIFT_REV80 15u 4054 #define PRXS_REM7_TXBF_MASK_REV80 0x4000 4055 #define PRXS_REM7_TXBF_SHIFT_REV80 14u 4056 #define PRXS_REM7_NSTS_MASK_REV80 0x3800 4057 #define PRXS_REM7_NSTS_SHIFT_REV80 11u 4058 #define PRXS_REM7_RU_ALLOC_MASK_REV80 0x007f 4059 #define PRXS_REM7_RU_ALLOC_SHIFT_REV80 0u 4060 4061 #define PRXS_STAID_MASK 0x07ff 4062 #define PRXS_STAID_SHIFT 0u 4063 4064 enum { 4065 HE_RU_TYPE_26T = 0, /* 26 tone RU, 0 - 36 */ 4066 HE_RU_TYPE_52T = 1, /* 52 tone RU, 37 - 52 */ 4067 HE_RU_TYPE_106T = 2, /* 106 tone RU, 53 - 60 */ 4068 HE_RU_TYPE_242T = 3, /* 242 tone RU, 61 - 64 */ 4069 HE_RU_TYPE_484T = 4, /* 484 tone RU, 65 - 66 */ 4070 HE_RU_TYPE_996T = 5, /* 996 tone RU, 67 - 68 */ 4071 HE_RU_TYPE_2x996T = 6, /* 2x996 tone RU, 69 */ 4072 HE_RU_TYPE_LAST = 7 /* Reserved, Invalid */ 4073 }; 4074 4075 #define HE_RU_TYPE_MAX 6 4076 4077 /* received PE duration is present in phyrxs_rem[4] bit position [7-9] */ 4078 #define D11PPDU_PE_GE80(rxh, corerev) ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[4]) & \ 4079 (PRXS_REM4_PE_MASK_REV80)) >> PRXS_REM4_PE_SHIFT_REV80) 4080 4081 #define D11PPDU_PE(rxh, corerev, corerev_minor) (AUTO_PHYRXSTS_ENAB() ? \ 4082 APRXS_PE(rxh, corerev, corerev_minor) : D11PPDU_PE_GE80(rxh, corerev)) 4083 4084 /* received RU type is present in phyrxs_rem[4] bit position [10-11] */ 4085 #define D11PPDU_RU_TYPE(rxh, corerev, corerev_minor) \ 4086 (AUTO_PHYRXSTS_ENAB() ? APRXS_RU(rxh, corerev, corerev_minor) : \ 4087 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[4]) & \ 4088 (PRXS_REM4_RU_TYPE_MASK_REV80)) >> PRXS_REM4_RU_TYPE_SHIFT_REV80) : 0)) 4089 4090 /* received he num of user type is present in phyrxs_rem[4] bit position [13-15] */ 4091 #define D11PPDU_HE_NUM_USER_TYPE(rxh, corerev, corerev_min) \ 4092 (AUTO_PHYRXSTS_ENAB() ? APRXS_USTY(rxh, corerev, corerev_min) : \ 4093 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[4]) & \ 4094 (PRXS_REM4_NUM_USER_BIT_MASK_REV80)) >> PRXS_REM4_NUM_USER_SHIFT_REV80) : 0)) 4095 4096 #define D11PPDU_FF_TYPE(rxh, corerev, corerev_minor) \ 4097 (AUTO_PHYRXSTS_ENAB() ? APRXS_AXFF(rxh, corerev, corerev_minor) : \ 4098 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[5]) & \ 4099 (PRXS_REM5_11AX_FF_MASK_REV80)) >> PRXS_REM5_11AX_FF_SHIFT_REV80) : 0)) 4100 4101 /* DCM is present in phyrxs_rem[7] byte 27, bit position [7] */ 4102 #define D11PPDU_DCM(rxh, corerev, corerev_minor) \ 4103 (AUTO_PHYRXSTS_ENAB() ? APRXS_DCM(rxh, corerev, corerev_minor) : \ 4104 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \ 4105 (PRXS_REM7_DCM_MASK_REV80)) >> PRXS_REM7_DCM_SHIFT_REV80) : 0)) 4106 4107 /* coding used is present in phyrxs_rem[6] byte:25, bit position [12] */ 4108 #define D11PPDU_CODING(rxh, corerev, corerev_minor) \ 4109 (AUTO_PHYRXSTS_ENAB() ? APRXS_CODING(rxh, corerev, corerev_minor) : \ 4110 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[6]) & \ 4111 (PRXS_REM6_CODING_MASK_REV80)) >> PRXS_REM6_CODING_SHIFT_REV80) : 0)) 4112 4113 /* spatial reuse 2 / STA-ID */ 4114 #define D11PPDU_STAID(rxh, corerev, corerev_minor) \ 4115 (AUTO_PHYRXSTS_ENAB() ? APRXS_AX_STAID(rxh, corerev, corerev_minor) : \ 4116 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \ 4117 (PRXS_STAID_MASK)) >> PRXS_STAID_SHIFT) : 0)) 4118 4119 #define D11PPDU_TXBF(rxh, corerev, corerev_minor) \ 4120 (AUTO_PHYRXSTS_ENAB() ? APRXS_TXBF(rxh, corerev, corerev_minor) : \ 4121 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \ 4122 (PRXS_REM7_TXBF_MASK_REV80)) >> PRXS_REM7_TXBF_SHIFT_REV80) : 0)) 4123 4124 /* GI_LTF is present in phyrxs_rem[5] bit position [0-1] */ 4125 #define D11PPDU_GI_LTF(rxh, corerev, corerev_minor) \ 4126 (AUTO_PHYRXSTS_ENAB() ? APRXS_GILTF(rxh, corerev, corerev_minor) : \ 4127 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[5]) & \ 4128 (PRXS_REM5_GI_LTF_MASK_REV80)) >> PRXS_REM5_GI_LTF_SHIFT_REV80) : 0)) 4129 4130 /* MCS is present in phyrxs_rem[6] - byte 25, bit position [8-11] */ 4131 #define D11PPDU_MCS(rxh, corerev, corerev_minor) \ 4132 (AUTO_PHYRXSTS_ENAB() ? APRXS_AXMCS(rxh, corerev, corerev_minor) : \ 4133 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[6]) & \ 4134 (PRXS_REM6_MCS_MASK_REV80)) >> PRXS_REM6_MCS_SHIFT_REV80) : 0)) 4135 4136 /* NSTS present in phyrxs_rem[7] bit position [11-13] */ 4137 #define D11PPDU_NSTS(rxh, corerev, corerev_minor) \ 4138 (AUTO_PHYRXSTS_ENAB() ? APRXS_NSTS(rxh, corerev, corerev_minor) : \ 4139 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \ 4140 (PRXS_REM7_NSTS_MASK_REV80)) >> PRXS_REM7_NSTS_SHIFT_REV80) : 0)) 4141 4142 /* RU ALLOC present in phyrxs_rem[7]- byte 26; bit position [6:0] */ 4143 #define D11PPDU_RU_ALLOC(rxh, corerev, corerev_minor) \ 4144 (AUTO_PHYRXSTS_ENAB() ? APRXS_AX_RUALLOC(rxh, corerev, corerev_minor) : \ 4145 (D11REV_GE(corerev, 80) ? ((D11RXHDR_GE80_ACCESS_VAL(rxh, phyrxs_rem[7]) & \ 4146 (PRXS_REM7_RU_ALLOC_MASK_REV80)) >> PRXS_REM7_RU_ALLOC_SHIFT_REV80) : 0) 4147 4148 /* PHY RX status "Frame Type" field mask. */ 4149 #define PRXS_FT_MASK(corerev) \ 4150 (D11REV_GE(corerev, 80) ? (PRXS0_FT_MASK_REV_GE80) : \ 4151 (PRXS0_FT_MASK_REV_LT80)) 4152 4153 /** 4154 * ACPHY PhyRxStatus0 SubBand (FinalBWClassification) bit defs 4155 * FinalBWClassification is a 4 bit field, each bit representing one 20MHz sub-band 4156 * of a channel. 4157 */ 4158 enum prxs_subband { 4159 PRXS_SUBBAND_20LL = 0x0001, 4160 PRXS_SUBBAND_20LU = 0x0002, 4161 PRXS_SUBBAND_20UL = 0x0004, 4162 PRXS_SUBBAND_20UU = 0x0008, 4163 PRXS_SUBBAND_40L = 0x0003, 4164 PRXS_SUBBAND_40U = 0x000C, 4165 PRXS_SUBBAND_80 = 0x000F, 4166 PRXS_SUBBAND_20LLL = 0x0001, 4167 PRXS_SUBBAND_20LLU = 0x0002, 4168 PRXS_SUBBAND_20LUL = 0x0004, 4169 PRXS_SUBBAND_20LUU = 0x0008, 4170 PRXS_SUBBAND_20ULL = 0x0010, 4171 PRXS_SUBBAND_20ULU = 0x0020, 4172 PRXS_SUBBAND_20UUL = 0x0040, 4173 PRXS_SUBBAND_20UUU = 0x0080, 4174 PRXS_SUBBAND_40LL = 0x0003, 4175 PRXS_SUBBAND_40LU = 0x000c, 4176 PRXS_SUBBAND_40UL = 0x0030, 4177 PRXS_SUBBAND_40UU = 0x00c0, 4178 PRXS_SUBBAND_80L = 0x000f, 4179 PRXS_SUBBAND_80U = 0x00f0, 4180 PRXS_SUBBAND_160 = 0x00ff 4181 }; 4182 4183 enum prxs_subband_bphy { 4184 PRXS_SUBBAND_BPHY_20L = 0x0000, 4185 PRXS_SUBBAND_BPHY_20U = 0x0001 4186 }; 4187 4188 /* ACPHY Gen2 RxStatus defs */ 4189 4190 /* ACPHY Gen2 PhyRxStatus_0: */ 4191 #define PRXS0_ACPHY2_MUPPDU 0x1000 /**< 0: SU PPDU; 1: MU PPDU */ 4192 #define PRXS0_ACPHY2_OBSS 0xE000 /**< OBSS mitigation state */ 4193 4194 /* ACPHY Gen2 PhyRxStatus_1: */ 4195 #define PRXS1_ACPHY2_SUBBAND_MASK 0xFF00 /**< FinalBWClassification: 4196 * 8-bit bitfield of sub-bands occupied by Rx frame 4197 */ 4198 #define PRXS1_ACPHY2_SUBBAND_SHIFT 8 4199 4200 /* ACPHY Gen2 PhyRxStatus_2: */ 4201 #define PRXS2_ACPHY2_MU_INT 0x003F /**< MU interference processing type */ 4202 4203 /* ACPHY Gen2 PhyRxStatus_5: */ 4204 #define PRXS5_ACPHY2_RSSI_FRAC 0xFF00 /**< RSSI fractional bits */ 4205 4206 /* ucode RxStatus1: */ 4207 #define RXS_BCNSENT 0x8000 4208 #define RXS_TOFINFO 0x4000 /**< Rxed measurement frame processed by ucode */ 4209 #define RXS_GRANTBT 0x2000 /* Indicate medium given to BT */ 4210 #define RXS_SECKINDX_MASK_GE64 0x1fe0 4211 #define RXS_SECKINDX_MASK 0x07e0 4212 #define RXS_IS_DEFRAG 0x4 4213 #define RXS_DEFRAG_SHIFT 2 4214 #define RXS_SECKINDX_SHIFT 5 4215 #define RXS_DECERR (1 << 4) 4216 #define RXS_DECATMPT (1 << 3) 4217 #define RXS_PBPRES (1 << 2) /**< PAD bytes to make IP data 4 bytes aligned */ 4218 #define RXS_RESPFRAMETX (1 << 1) 4219 #define RXS_FCSERR (1 << 0) 4220 4221 /* ucode RxStatus2: */ 4222 #define RXS_AMSDU_MASK 1 4223 #define RXS_AGGTYPE_MASK 0x6 4224 #define RXS_AGGTYPE_SHIFT 1 4225 #define RXS_AMSDU_FIRST 1 4226 #define RXS_AMSDU_INTERMEDIATE 0 4227 #define RXS_AMSDU_LAST 2 4228 #define RXS_AMSDU_N_ONE 3 4229 #define RXS_TKMICATMPT (1 << 3) 4230 #define RXS_TKMICERR (1 << 4) 4231 #define RXS_PHYRXST_PRISEL_CLR (1 << 5) /**< PR113291: When '1', Indicates that the Rx */ 4232 /* packet was received while the antenna */ 4233 /* (prisel) had been granted to BT. */ 4234 #define RXS_PHYRXST_VALID (1 << 8) 4235 #define RXS_BCNCLSG (1 << 9) /**< Coleasced beacon packet */ 4236 #define RXS_RXANT_MASK 0x3 4237 #define RXS_RXANT_SHIFT_LT80 12 4238 #define RXS_RXANT_SHIFT_GE80 5 4239 #define RXS_LOOPBACK_MODE 4 4240 4241 /* Bit definitions for MRXS word for short rx status. */ 4242 /* RXSS = RX Status Short */ 4243 #define RXSS_AMSDU_MASK 1 /**< 1: AMSDU */ 4244 #define RXSS_AGGTYPE_MASK 0x6 /**< 0 intermed, 1 first, 2 last, 3 single/non-AMSDU */ 4245 #define RXSS_AGGTYPE_SHIFT 1 4246 #define RXSS_PBPRES (1 << 3) /**< two-byte PAD prior to plcp */ 4247 #define RXSS_HDRSTS (1 << 4) /**< header conversion status. 1 enabled, 0 disabled */ 4248 #define RXSS_RES_MASK 0xE0 /**< reserved */ 4249 #define RXSS_MSDU_CNT_MASK 0xFF00 /**< index of this AMSDU sub-frame in the AMSDU */ 4250 #define RXSS_MSDU_CNT_SHIFT 8 4251 4252 /* RX signal control definitions */ 4253 /** PHYRXSTAUS validity checker; in-between ampdu, or rxs status isn't valid */ 4254 #define PRXS_IS_VALID(rxh, rev, rev_min) \ 4255 ((D11REV_GE(rev, 80) && \ 4256 (D11RXHDR_ACCESS_VAL(rxh, rev, rev_min, dma_flags) & \ 4257 RXS_PHYRXST_VALID_REV_GE80)) || \ 4258 (D11REV_GE(rev, 64) && !(D11RXHDR_ACCESS_VAL(rxh, \ 4259 rev, rev_min, dma_flags) & RXS_SHORT_MASK)) || \ 4260 (D11RXHDR_ACCESS_VAL(rxh, rev, rev_min, RxStatus2) & RXS_PHYRXST_VALID)) 4261 4262 /* RxChan */ 4263 #define RXS_CHAN_40 0x1000 4264 #define RXS_CHAN_5G 0x0800 4265 #define RXS_CHAN_ID_MASK 0x07f8 4266 #define RXS_CHAN_ID_SHIFT 3 4267 4268 #define C_BTCX_AGGOFF_BLE (1 << 0) 4269 #define C_BTCX_AGGOFF_A2DP (1 << 1) 4270 #define C_BTCX_AGGOFF_PER (1 << 2) 4271 #define C_BTCX_AGGOFF_MULTIHID (1 << 3) 4272 #define C_BTCX_AGG_LMT_SET_HIGH (1 << 4) 4273 #define C_BTCX_AGGOFF_ESCO_SLAVE (1 << 5) 4274 4275 #define BTCX_HFLG_NO_A2DP_BFR (1 << 0) /**< no check a2dp buffer */ 4276 #define BTCX_HFLG_NO_CCK (1 << 1) /**< no cck rate for null or cts2self */ 4277 #define BTCX_HFLG_NO_OFDM_FBR (1 << 2) /**< no ofdm fbr for null or cts2self */ 4278 #define BTCX_HFLG_NO_INQ_DEF (1 << 3) /**< no defer inquery */ 4279 #define BTCX_HFLG_GRANT_BT (1 << 4) /**< always grant bt */ 4280 #define BTCX_HFLG_ANT2WL (1 << 5) /**< force prisel to wl */ 4281 #define BTCX_HFLG_PS4ACL (1 << 7) /**< use ps null for unsniff acl */ 4282 #define BTCX_HFLG_DYAGG (1 << 8) /**< dynamic tx aggregation */ 4283 #define BTCX_HFLG_SKIPLMP (1 << 10) /**< no LMP check for 4331 (w 20702 A1/A3) */ 4284 #define BTCX_HFLG_ACL_BSD_BLE_SCAN_GRNT (1 << 14) /**< ACL based grant for BLE scan */ 4285 /* indication to ucode */ 4286 #define BTCX_HFLG2_TRAP_RFACTIVE (1 << 0) /* trap when RfActive too long */ 4287 #define BTCX_HFLG2_TRAP_TXCONF (1 << 1) /* trap when coex grants txconf late */ 4288 #define BTCX_HFLG2_TRAP_ANTDLY (1 << 2) /* trap when coex grants antdly late */ 4289 #define BTCX_HFLG2_TRAP_BTTYPE (1 << 3) /* trap when illegal BT tasktype receive */ 4290 /* Bit definitions for M_BTCX_CONFIG */ 4291 #define BTCX_CONFIG_FORCE_TRAP (1 << 13) /* Force a specific BTCoex TRAP when set */ 4292 4293 /* BTCX_CONFIG bits */ 4294 #define C_BTCX_CONFIG_SLOTTED_STATE_1 (1 << 3) 4295 #define C_BTCX_CONFIG_SLOTTED_STATE_2 (1 << 4) 4296 #define C_BTCX_CONFIG_SLOTTED_STATE_3 (1 << 5) 4297 #define C_BTCX_CONFIG_LOW_RSSI (1 << 7) 4298 #define C_BTCX_CONFIG_BT_STROBE (1 << 9) 4299 #define C_BTCX_CONFIG_SCO_PROT (1 << 10) 4300 #define C_BTCX_CFG_CMN_CTS2SELF (1 << 11) 4301 #define C_BTCX_CONFIG_HPP_STATE (1 << 15) 4302 4303 #define BTC_PARAMS_FW_START_IDX 1000 /**< starting index of FW only btc params */ 4304 /** BTC_PARAMS_FW definitions */ 4305 typedef enum 4306 { 4307 // allow rx-agg to be re-enabled after SCO session completes 4308 BTC_FW_RX_REAGG_AFTER_SCO = BTC_PARAMS_FW_START_IDX, 4309 // RSSI threshold at which SCO grant/deny limits are changed dynamically 4310 BTC_FW_RSSI_THRESH_SCO = BTC_PARAMS_FW_START_IDX + 1, 4311 // Enable the dynamic LE scan priority 4312 BTC_FW_ENABLE_DYN_LESCAN_PRI = BTC_PARAMS_FW_START_IDX + 2, 4313 // If Tput(mbps) is above this, then share antenna with BT's LE_SCAN packet type. 4314 BTC_FW_LESCAN_LO_TPUT_THRESH = BTC_PARAMS_FW_START_IDX + 3, 4315 // If Tput(mbps) is below this, then share antenna with BT's LE_SCAN packet type. 4316 // sampled once a second. 4317 BTC_FW_LESCAN_HI_TPUT_THRESH = BTC_PARAMS_FW_START_IDX + 4, 4318 // Numbers of denials before granting LS scans 4319 BTC_FW_LESCAN_GRANT_INT = BTC_PARAMS_FW_START_IDX + 5, 4320 // number of times algorighm changes lescn pri 4321 BTC_FW_LESCAN_ALG_CNT = BTC_PARAMS_FW_START_IDX + 6, 4322 // RSSI threshold at which aggregation will be disabled during frequent BLE activity 4323 BTC_FW_RSSI_THRESH_BLE = BTC_PARAMS_FW_START_IDX + 7, 4324 // AMPDU Aggregation state requested by BTC 4325 BTC_FW_AGG_STATE_REQ = BTC_PARAMS_FW_START_IDX + 8, 4326 // Reserving space for parameters used in other projects 4327 BTC_FW_RSVD_1 = BTC_PARAMS_FW_START_IDX + 9, 4328 BTC_FW_HOLDSCO_LIMIT = BTC_PARAMS_FW_START_IDX + 10, // Lower Limit 4329 BTC_FW_HOLDSCO_LIMIT_HI = BTC_PARAMS_FW_START_IDX + 11, // Higher Limit 4330 BTC_FW_SCO_GRANT_HOLD_RATIO = BTC_PARAMS_FW_START_IDX + 12, // Low Ratio 4331 BTC_FW_SCO_GRANT_HOLD_RATIO_HI = BTC_PARAMS_FW_START_IDX + 13, // High Ratio 4332 BTC_FW_HOLDSCO_HI_THRESH = BTC_PARAMS_FW_START_IDX + 14, // BT Period Threshold 4333 BTC_FW_MOD_RXAGG_PKT_SZ_FOR_SCO = BTC_PARAMS_FW_START_IDX + 15, 4334 /* Modify Rx Aggregation size when SCO/eSCO detected */ 4335 BTC_FW_AGG_SIZE_LOW = BTC_PARAMS_FW_START_IDX + 16, 4336 /* Agg size when BT period < 7500 ms */ 4337 BTC_FW_AGG_SIZE_HIGH = BTC_PARAMS_FW_START_IDX + 17, 4338 /* Agg size when BT period >= 7500 ms */ 4339 BTC_FW_MOD_RXAGG_PKT_SZ_FOR_A2DP = BTC_PARAMS_FW_START_IDX + 18, 4340 /* Enable COEX constraints for TWT scheduling */ 4341 BTC_FW_TWT_COEX_CONSTRAINTS_EN = BTC_PARAMS_FW_START_IDX + 19, 4342 /* Enable Rx Aggregation for P2P_GO and SOFTAP when ACL/A2DP detected */ 4343 BTC_FW_MOD_RXAGG_PKT_SZ_FOR_APMODE_ACL_A2DP = BTC_PARAMS_FW_START_IDX + 20, 4344 /* Disable amsdu dynamicaly during Rx limited aggregation */ 4345 BTC_FW_DISABLE_AMSDU_DURING_LIM_AGG = BTC_PARAMS_FW_START_IDX + 21, 4346 /* Enable acl based grant for ble scan based on number of 2G slots */ 4347 BTC_FW_ENABLE_ACL_GRNT_FOR_BLE_SCAN = BTC_PARAMS_FW_START_IDX + 22, 4348 /* Threshold slot count for 2g band to Enable acl based grant for ble scan during NAN */ 4349 BTC_FW_NAN_THRESHOLD_SLOTS_FOR_2G = BTC_PARAMS_FW_START_IDX + 23, 4350 /* BT task bm override for critical chansw slots */ 4351 BTC_FW_CHANSW_CRT_OVR_BTTASK_BM_L = BTC_PARAMS_FW_START_IDX + 24, 4352 BTC_FW_CHANSW_CRT_OVR_BTTASK_BM_H = BTC_PARAMS_FW_START_IDX + 25, 4353 /* Limited Aggr AP check grace period, # of BTC watchdog timeout */ 4354 BTC_FW_AGG_AP_GRACE_PERIOD = BTC_PARAMS_FW_START_IDX + 26, 4355 /* Limited Aggr AP check buffer limit, sample interval, # of BTC watchdog timeout */ 4356 BTC_FW_AGG_AP_BUFLIM_SMPLINTV = BTC_PARAMS_FW_START_IDX + 27, 4357 /* Limited Aggr AP check excessive DELBA, sample interval, # of BTC watchdog timeout */ 4358 BTC_FW_AGG_AP_DELBA_SMPLINTV = BTC_PARAMS_FW_START_IDX + 28, 4359 /* Limited Aggr AP check excessive DELBA, threshold, # of DELBA */ 4360 BTC_FW_AGG_AP_DELBA_THRESHOLD = BTC_PARAMS_FW_START_IDX + 29, 4361 BTC_FW_MAX_INDICES // Maximum number of btc_fw sw registers 4362 } btcParamsFirmwareDefinitions; 4363 4364 #define BTC_FW_NUM_INDICES (BTC_FW_MAX_INDICES - BTC_PARAMS_FW_START_IDX) 4365 4366 // 1: Re-enable aggregation after SCO 4367 #define BTC_FW_RX_REAGG_AFTER_SCO_INIT_VAL 1 4368 4369 // 1: Enable limited aggregation for SCO 4370 #define BTC_FW_MOD_RXAGG_PKT_SZ_FOR_SCO_INIT_VAL 0 4371 4372 /* Enable Limited aggregation for HI interval BT periodic task only (>=7.5ms) */ 4373 #ifdef WL_BTC_LIMAGG_HI_INT 4374 /* RX aggregation packet size when SCO */ 4375 #define BTC_FW_AGG_SIZE_LOW_INIT_VAL 0 4376 #else 4377 /* RX aggregation packet size when SCO */ 4378 #define BTC_FW_AGG_SIZE_LOW_INIT_VAL 1 4379 #endif 4380 4381 /* aggregation size when BT period < BT_AMPDU_RESIZE_THRESH */ 4382 #define BTC_FW_AGG_SIZE_HIGH_INIT_VAL 2 4383 /* aggregation size when BT period > BT_AMPDU_RESIZE_THRESH */ 4384 // 0: disable weak-rssi SCO coex feature. If > 0, adjust SCO COEX algorithm for weak RSSI scenario. 4385 #define BTC_FW_RSSI_THRESH_SCO_INIT_VAL 0 4386 4387 // 1: Enable limited aggregation for A2DP 4388 #define BTC_FW_MOD_RXAGG_PKT_SZ_FOR_A2DP_INIT_VAL 0 4389 4390 // Enable LE Scan Priority Algorithm 0: Disable, 1: Enable 4391 #define BTC_FW_ENABLE_DYN_LESCAN_PRI_INIT_VAL 0 4392 // If WL Tput below 7 mbps, don't grant background LE Scans 4393 #define BTC_FW_LESCAN_LO_TPUT_THRESH_INIT_VAL 7 4394 // If WL Tput above 30 mbps, don't grant background LE Scans 4395 #define BTC_FW_LESCAN_HI_TPUT_THRESH_INIT_VAL 30 4396 // If LE Priority algorithm is triggered, grant one out of 2 LE_SCAN requests 4397 #define BTC_FW_LESCAN_GRANT_INT_INIT_VAL 2 4398 // If RSSI is weaker than -70 dBm and BLE activity is frequent, then disable 4399 // RX aggregation, and clamp TX aggregation. 4400 #ifdef WL_BTCX_UDM 4401 #define BTC_FW_RSSI_THRESH_BLE_INIT_VAL 100 4402 #else 4403 #define BTC_FW_RSSI_THRESH_BLE_INIT_VAL 70 4404 #endif 4405 #define BTC_FW_HOLDSCO_LIMIT_INIT_VAL 100 4406 #define BTC_FW_HOLDSCO_LIMIT_HI_INIT_VAL 10 4407 #define BTC_FW_SCO_GRANT_HOLD_RATIO_INIT_VAL 1500 4408 #define BTC_FW_SCO_GRANT_HOLD_RATIO_HI_INIT_VAL 1000 4409 #define BTC_FW_HOLDSCO_HI_THRESH_INIT_VAL 7400 4410 #define BTC_FW_TWT_COEX_CONSTRAINTS_EN_INIT_VAL 1 4411 /* Aggregation in AP mode (P2P_GO and SOFTAP) when ACL and A2DP */ 4412 #define BTC_FW_MOD_RXAGG_PKT_SZ_FOR_APMODE_ACL_A2DP_INIT_VAL 16 4413 /* Disable amsdu dynamicaly during Rx limited aggregation */ 4414 #define BTC_FW_DISABLE_AMSDU_DURING_LIM_AGG_INIT_VAL 1 4415 /* Enable acl based grant for ble scan based on number of 2G slots during NAN */ 4416 #define BTC_FW_ENABLE_ACL_GRNT_FOR_BLE_SCAN_INIT_VAL 0 4417 /* Threshold slot count for 2g band to Enable acl based grant for ble 4418 * scan during NAN. Setting current value to 8, considering time line is 512ms 4419 * Threshold changes dynamically based on different time line 4420 */ 4421 #define BTC_FW_NAN_THRESHOLD_SLOTS_FOR_2G_INIT_VAL 8 4422 /* BT task bm override for critical chansw slots -initval */ 4423 #define BTC_FW_CHANSW_CRT_OVR_BTTASK_BM_L_INIT_VAL 0x0000 4424 #define BTC_FW_CHANSW_CRT_OVR_BTTASK_BM_H_INIT_VAL 0x0020 4425 #define BTC_FW_AGG_AP_GRACE_PERIOD_VAL 1 4426 #define BTC_FW_AGG_AP_BUFLIM_SMPLINTV_VAL 1 4427 #define BTC_FW_AGG_AP_DELBA_SMPLINTV_VAL 5 4428 #define BTC_FW_AGG_AP_DELBA_THRESHOLD_VAL 3 4429 4430 /* NR Coex Params Set/Get via wl btc_params, starting index */ 4431 #define NR5GCX_PARAMS_FW_START_IDX 1200 4432 4433 typedef enum NR5GCX_Params { 4434 // Min # of PPDU to be tracked for hysteresis 4435 NR5GCX_FW_MIN_NUM_PPDU = NR5GCX_PARAMS_FW_START_IDX, 4436 // Threshold for data stall detection, percentage 4437 NR5GCX_FW_DATA_STALL_TH = NR5GCX_PARAMS_FW_START_IDX + 1, 4438 // max number of rate recovery attempts 4439 NR5GCX_FW_MAX_NUM_ATTEMPTS = NR5GCX_PARAMS_FW_START_IDX + 2, 4440 // Rate recovery rate check duration 4441 NR5GCX_FW_RR_RATE_CHK_DUR = NR5GCX_PARAMS_FW_START_IDX + 3, 4442 // Rate recovery attempt duration 4443 NR5GCX_FW_RR_ATTEMPT_DUR = NR5GCX_PARAMS_FW_START_IDX + 4, 4444 // NR grant duration after a unsuccessful rate recovery 4445 NR5GCX_FW_RR_UNSC_DUR = NR5GCX_PARAMS_FW_START_IDX + 5, 4446 // Threshold for rate recovery, percentage 4447 NR5GCX_FW_RECOVERY_TH = NR5GCX_PARAMS_FW_START_IDX + 6, 4448 // Threshold for low RSSI 4449 NR5GCX_FW_LOWRSSI_TH = NR5GCX_PARAMS_FW_START_IDX + 7, 4450 // Maximum number of nr5gcx fw params 4451 NR5GCX_FW_MAX_INDICES 4452 } NR5GCXParamsFirmwareDefinitions; 4453 4454 #define NR5GCX_FW_NUM_INDICES (NR5GCX_FW_MAX_INDICES - NR5GCX_PARAMS_FW_START_IDX) 4455 4456 #define NR5GCX_FW_MIN_NUM_PPDU_INIT 10u 4457 #define NR5GCX_FW_DATA_STALL_TH_INIT 75u 4458 #define NR5GCX_FW_MAX_NUM_ATTEMPTS_INIT 5u 4459 #define NR5GCX_FW_RR_RATE_CHK_DUR_INIT_MS 60u /* ms */ 4460 #define NR5GCX_FW_RR_ATTEMPT_DUR_INIT_MS 60u /* ms */ 4461 #define NR5GCX_FW_RR_UNSC_DUR_INIT_MS 10000u /* ms */ 4462 #define NR5GCX_FW_RECOVERY_TH_INIT 50u 4463 #define NR5GCX_FW_LOWRSSI_TH_INIT 85u /* dBm */ 4464 4465 /* RC1 Coex Params Set/Get via wl btc_params, starting index */ 4466 #define RC1CX_PARAMS_FW_START_IDX 1200 4467 4468 typedef enum RC1CX_Params { 4469 // Min # of PPDU to be tracked for hysteresis 4470 RC1CX_FW_MIN_NUM_PPDU = RC1CX_PARAMS_FW_START_IDX, 4471 // Threshold for data stall detection, percentage 4472 RC1CX_FW_DATA_STALL_TH = RC1CX_PARAMS_FW_START_IDX + 1, 4473 // max number of rate recovery attempts 4474 RC1CX_FW_MAX_NUM_ATTEMPTS = RC1CX_PARAMS_FW_START_IDX + 2, 4475 // Rate recovery rate check duration 4476 RC1CX_FW_RR_RATE_CHK_DUR = RC1CX_PARAMS_FW_START_IDX + 3, 4477 // Rate recovery attempt duration 4478 RC1CX_FW_RR_ATTEMPT_DUR = RC1CX_PARAMS_FW_START_IDX + 4, 4479 // NR grant duration after a unsuccessful rate recovery 4480 RC1CX_FW_RR_UNSC_DUR = RC1CX_PARAMS_FW_START_IDX + 5, 4481 // Threshold for rate recovery, percentage 4482 RC1CX_FW_RECOVERY_TH = RC1CX_PARAMS_FW_START_IDX + 6, 4483 // Threshold for low RSSI 4484 RC1CX_FW_LOWRSSI_TH = RC1CX_PARAMS_FW_START_IDX + 7, 4485 // Maximum number of rc1cx fw params 4486 RC1CX_FW_MAX_INDICES 4487 } RC1CXParamsFirmwareDefinitions; 4488 4489 #define RC1CX_FW_NUM_INDICES (RC1CX_FW_MAX_INDICES - RC1CX_PARAMS_FW_START_IDX) 4490 4491 #define RC1CX_FW_MIN_NUM_PPDU_INIT 10u 4492 #define RC1CX_FW_DATA_STALL_TH_INIT 75u 4493 #define RC1CX_FW_MAX_NUM_ATTEMPTS_INIT 5u 4494 #define RC1CX_FW_RR_RATE_CHK_DUR_INIT_MS 60u /* ms */ 4495 #define RC1CX_FW_RR_ATTEMPT_DUR_INIT_MS 60u /* ms */ 4496 #define RC1CX_FW_RR_UNSC_DUR_INIT_MS 10000u /* ms */ 4497 #define RC1CX_FW_RECOVERY_TH_INIT 50u 4498 #define RC1CX_FW_LOWRSSI_TH_INIT 85u /* dBm */ 4499 4500 #ifdef GPIO_TXINHIBIT 4501 /* GPIO based TX_INHIBIT:SWWLAN-109270 */ 4502 typedef enum shm_macintstatus_ext_e { 4503 C_MISE_GPIO_TXINHIBIT_VAL_NBIT = 0, 4504 C_MISE_GPIO_TXINHIBIT_INT_NBIT = 1 4505 } shm_macintstatus_ext_t; 4506 #define C_MISE_GPIO_TXINHIBIT_VAL_MASK (1 << C_MISE_GPIO_TXINHIBIT_VAL_NBIT) 4507 #define C_MISE_GPIO_TXINHIBIT_INT_MASK (1 << C_MISE_GPIO_TXINHIBIT_INT_NBIT) 4508 #endif 4509 #define M_PSM_SOFT_REGS 0x0 4510 4511 /** Scratch Reg defs */ 4512 typedef enum 4513 { 4514 S_RSV0 = 0, 4515 S_RSV1, 4516 S_RSV2, 4517 4518 /* scratch registers for Dot11-constants */ 4519 S_DOT11_CWMIN, /**< CW-minimum 0x03 */ 4520 S_DOT11_CWMAX, /**< CW-maximum 0x04 */ 4521 S_DOT11_CWCUR, /**< CW-current 0x05 */ 4522 S_DOT11_SRC_LMT, /**< short retry count limit 0x06 */ 4523 S_DOT11_LRC_LMT, /**< long retry count limit 0x07 */ 4524 S_DOT11_DTIMCOUNT, /**< DTIM-count 0x08 */ 4525 4526 /* Tx-side scratch registers */ 4527 S_SEQ_NUM, /**< hardware sequence number reg 0x09 */ 4528 S_SEQ_NUM_FRAG, /**< seq-num for frags (Set at the start os MSDU 0x0A */ 4529 S_FRMRETX_CNT, /**< frame retx count 0x0B */ 4530 S_SSRC, /**< Station short retry count 0x0C */ 4531 S_SLRC, /**< Station long retry count 0x0D */ 4532 S_EXP_RSP, /**< Expected response frame 0x0E */ 4533 S_OLD_BREM, /**< Remaining backoff ctr 0x0F */ 4534 S_OLD_CWWIN, /**< saved-off CW-cur 0x10 */ 4535 S_TXECTL, /**< TXE-Ctl word constructed in scr-pad 0x11 */ 4536 S_CTXTST, /**< frm type-subtype as read from Tx-descr 0x12 */ 4537 4538 /* Rx-side scratch registers */ 4539 S_RXTST, /**< Type and subtype in Rxframe 0x13 */ 4540 4541 /* Global state register */ 4542 S_STREG, /**< state storage actual bit maps below 0x14 */ 4543 4544 S_TXPWR_SUM, /**< Tx power control: accumulator 0x15 */ 4545 S_TXPWR_ITER, /**< Tx power control: iteration 0x16 */ 4546 S_RX_FRMTYPE, /**< Rate and PHY type for frames 0x17 */ 4547 S_THIS_AGG, /**< Size of this AGG (A-MSDU) 0x18 */ 4548 4549 S_KEYINDX, /* 0x19 */ 4550 S_RXFRMLEN, /**< Receive MPDU length in bytes 0x1A */ 4551 4552 /* Receive TSF time stored in SCR */ 4553 S_RXTSFTMRVAL_WD3, /**< TSF value at the start of rx 0x1B */ 4554 S_RXTSFTMRVAL_WD2, /**< TSF value at the start of rx 0x1C */ 4555 S_RXTSFTMRVAL_WD1, /**< TSF value at the start of rx 0x1D */ 4556 S_RXTSFTMRVAL_WD0, /**< TSF value at the start of rx 0x1E */ 4557 S_RXSSN, /**< Received start seq number for A-MPDU BA 0x1F */ 4558 S_RXQOSFLD, /**< Rx-QoS field (if present) 0x20 */ 4559 4560 /* Scratch pad regs used in microcode as temp storage */ 4561 S_TMP0, /**< stmp0 0x21 */ 4562 S_TMP1, /**< stmp1 0x22 */ 4563 S_TMP2, /**< stmp2 0x23 */ 4564 S_TMP3, /**< stmp3 0x24 */ 4565 S_TMP4, /**< stmp4 0x25 */ 4566 S_TMP5, /**< stmp5 0x26 */ 4567 S_PRQPENALTY_CTR, /**< Probe response queue penalty counter 0x27 */ 4568 S_ANTCNT, /**< unsuccessful attempts on current ant. 0x28 */ 4569 S_SYMBOL, /**< flag for possible symbol ctl frames 0x29 */ 4570 S_RXTP, /**< rx frame type 0x2A */ 4571 S_STREG2, /**< extra state storage 0x2B */ 4572 S_STREG3, /**< even more extra state storage 0x2C */ 4573 S_STREG4, /**< ... 0x2D */ 4574 S_STREG5, /**< remember to initialize it to zero 0x2E */ 4575 4576 S_UNUSED_0X2F, /**< No longer used 0x2F */ 4577 S_UPTR, /* Use this to initialize utrace 0x30 */ 4578 S_ADJPWR_IDX, /**< PR 37101 WAR, adj_pwr_idx 0x31 */ 4579 S_CUR_PTR, /**< Temp pointer for A-MPDU re-Tx SHM table 0x32 */ 4580 S_REVID4, /**< 0x33 */ 4581 S_INDX, /**< 0x34 */ 4582 S_ADDR0, /**< 0x35 */ 4583 S_ADDR1, /**< 0x36 */ 4584 S_ADDR2, /**< 0x37 */ 4585 S_ADDR3, /**< 0x38 */ 4586 S_ADDR4, /**< 0x39 */ 4587 S_ADDR5, /**< 0x3A */ 4588 S_TMP6, /**< 0x3B */ 4589 S_KEYINDX_BU, /**< Backup for Key index 0x3C */ 4590 S_MFGTEST_TMP0, /**< Temp register used for RX test calculations 0x3D */ 4591 S_RXESN, /**< Received end sequence number for A-MPDU BA 0x3E */ 4592 S_STREG6, /**< 0x3F */ 4593 } ePsmScratchPadRegDefinitions; 4594 4595 #define C_STREG_SLOWCAL_PD_NBIT 0x00000004 /* BIT 2 slow clock cal is pending */ 4596 #define C_STREG_SLOWCAL_DN_NBIT 0x00000008 /* BIT 3 slow clock cal is done */ 4597 4598 #define S_BEACON_INDX S_OLD_BREM 4599 #define S_PRS_INDX S_OLD_CWWIN 4600 #define S_BTCX_BT_DUR S_REVID4 4601 #define S_PHYTYPE S_SSRC 4602 #define S_PHYVER S_SLRC 4603 4604 /* IHR GPT_2 is corerev >= 3 */ 4605 #define TSF_GPT_2_STAT 0x133 4606 #define TSF_GPT_2_CTR_L 0x134 4607 #define TSF_GPT_2_CTR_H 0x135 4608 #define TSF_GPT_2_VAL_L 0x136 4609 #define TSF_GPT_2_VAL_H 0x137 4610 4611 /* IHR TSF_GPT STAT values */ 4612 #define TSF_GPT_PERIODIC (1 << 12) 4613 #define TSF_GPT_ADJTSF (1 << 13) 4614 #define TSF_GPT_USETSF (1 << 14) 4615 #define TSF_GPT_ENABLE (1 << 15) 4616 4617 /** ucode mac statistic counters in shared memory */ 4618 #define MACSTAT_OFFSET_SZ 64 4619 #define MACSTAT_REV80_OFFSET_SZ 118 4620 4621 /* ucode macstat txfunflw offset */ 4622 #define UCODEMSTAT_TXFUNFL_BLK ((0x70 * 2) + (0x76 * 2)) 4623 4624 /* MACSTAT offset to SHM address */ 4625 #define MACSTAT_ADDR(x, offset) (M_PSM2HOST_STATS(x) + (offset)) 4626 4627 /** ucode mac statistic counters in shared memory, base addr defined in M_UCODE_MACSTAT1 */ 4628 typedef struct macstat1 { 4629 uint16 txndpa; /* + 0 (0x0) */ 4630 uint16 txndp; /* + 1*2 (0x2) */ 4631 uint16 txsf; /* + 2*2 (0x4) */ 4632 uint16 txcwrts; /* + 3*2 (0x6) */ 4633 uint16 txcwcts; /* + 4*2 (0x8) */ 4634 uint16 txbfm; /* + 5*2 (0xa) */ 4635 uint16 rxndpaucast; /* + 6*2 (0xc) */ 4636 uint16 bferptrdy; /* + 7*2 (0xe) */ 4637 uint16 rxsfucast; /* + 8*2 (0x10) */ 4638 uint16 rxcwrtsucast; /* + 9*2 (0x12) */ 4639 uint16 rxcwctsucast; /* +10*2 (0x14) */ 4640 uint16 rx20s; /* +11*2 (0x16) */ 4641 uint16 bcntrim; /* +12*2 (0x18) */ 4642 uint16 btc_rfact_l; /* +13*2 (0x1a) */ 4643 uint16 btc_rfact_h; /* +14*2 (0x1c) */ 4644 uint16 btc_txconf_l; /* +15*2 (0x1e) : cnt */ 4645 uint16 btc_txconf_h; /* +16*2 (0x20) : cnt */ 4646 uint16 btc_txconf_durl; /* +17*2 (0x22) : dur */ 4647 uint16 btc_txconf_durh; /* +18*2 (0x24) : dur */ 4648 uint16 rxsecrssi0; /* +19*2 (0x26) : high bin */ 4649 uint16 rxsecrssi1; /* +20*2 (0x28) : med bin */ 4650 uint16 rxsecrssi2; /* +21*2 (0x2a) : low bin */ 4651 uint16 rxpri_durl; /* +22*2 (0x2c) : dur */ 4652 uint16 rxpri_durh; /* +23*2 (0x2e) : dur */ 4653 uint16 rxsec20_durl; /* +24*2 (0x30) : dur */ 4654 uint16 rxsec20_durh; /* +25*2 (0x32) : dur */ 4655 uint16 rxsec40_durl; /* +26*2 (0x34) : dur */ 4656 uint16 rxsec40_durh; /* +27*2 (0x36) : dur */ 4657 } macstat1_t; 4658 4659 #define MX_UCODEX_MACSTAT (0x40 * 2) 4660 /* ucodex mac statistic counters in shared memory */ 4661 #define MACXSTAT_OFFSET_SZ 6 4662 4663 /* psm2 statistic counters in shared memory, base addr defined in MX_PSM2HOST_STATS */ 4664 typedef enum { 4665 MCXSTOFF_MACXSUSP = 0, 4666 MCXSTOFF_M2VMSG = 1, 4667 MCXSTOFF_V2MMSG = 2, 4668 MCXSTOFF_MBOXOUT = 3, 4669 MCXSTOFF_MUSND = 4, 4670 MCXSTOFF_SFB2V = 5 4671 } macxstat_offset_t; 4672 4673 /* dot11 core-specific control flags */ 4674 #define SICF_MCLKE 0x0001 /* Mac core clock Enable */ 4675 #define SICF_FCLKON 0x0002 /* Force clocks On */ 4676 #define SICF_PCLKE 0x0004 /**< PHY clock enable */ 4677 #define SICF_PRST 0x0008 /**< PHY reset */ 4678 #define SICF_MPCLKE 0x0010 /**< MAC PHY clockcontrol enable */ 4679 #define SICF_FREF 0x0020 /**< PLL FreqRefSelect (corerev >= 5) */ 4680 /* NOTE: the following bw bits only apply when the core is attached 4681 * to a NPHY (and corerev >= 11 which it will always be for NPHYs). 4682 */ 4683 #ifdef SICF_160M_BWMASK_DEF 4684 #define SICF_BWMASK(macrev) (D11REV_GE(macrev, 86) ? 0x00e0 : 0x00c0) /**< phy clkmsk */ 4685 #define SICF_BW160(macrev) (D11REV_GE(macrev, 86) ? 0x0080 : 0x00c0) /**< 160MHz BW */ 4686 #define SICF_BW80(macrev) (D11REV_GE(macrev, 86) ? 0x0060 : 0x00c0) /**< 80MHz BW */ 4687 #define SICF_BW40(macrev) (D11REV_GE(macrev, 86) ? 0x0040 : 0x0080) /**< 40MHz BW */ 4688 #define SICF_BW20(macrev) (D11REV_GE(macrev, 86) ? 0x0020 : 0x0040) /**< 20MHz BW */ 4689 #define SICF_BW10(macrev) (D11REV_GE(macrev, 86) ? 0x0000 : 0x0000) /**< 10MHz BW */ 4690 #else 4691 #define SICF_BWMASK 0x00c0 /**< phy clock mask (b6 & b7) */ 4692 #define SICF_BW160 0x00c0 /**< 160MHz BW */ 4693 #define SICF_BW80 0x00c0 /**< 80MHz BW */ 4694 #define SICF_BW40 0x0080 /**< 40MHz BW (160MHz phyclk) */ 4695 #define SICF_BW20 0x0040 /**< 20MHz BW (80MHz phyclk) */ 4696 #define SICF_BW10 0x0000 /**< 10MHz BW (40MHz phyclk) */ 4697 #endif 4698 #define SICF_DAC 0x0300 /**< Highspeed DAC mode control field */ 4699 #define SICF_GMODE 0x2000 /**< gmode enable */ 4700 4701 /* Macmode / Phymode / Opmode are used interchangebly sometimes 4702 * even though they all mean the same. Going ahead with the HW 4703 * signal name - using phymode here on (even though we know its 4704 * a misnomer). Applicable to d11 corerev >= 50 ---- ACPHY only 4705 */ 4706 #define SICF_PHYMODE_SHIFT 16 4707 #define SICF_PHYMODE 0xf0000 /**< mask */ 4708 4709 #define SICF_160CLKSEL 0x100000u /* main phy clock speed selection */ 4710 4711 /* dot11 core-specific status flags */ 4712 #define SISF_2G_PHY 0x0001 /**< 2.4G capable phy (corerev >= 5) */ 4713 #define SISF_5G_PHY 0x0002 /**< 5G capable phy (corerev >= 5) */ 4714 #define SISF_FCLKA 0x0004 /**< FastClkAvailable (corerev >= 5) */ 4715 #define SISF_DB_PHY 0x0008 /**< Dualband phy (corerev >= 11) */ 4716 4717 /* === End of MAC reg, Beginning of PHY(b/a/g/n) reg, radio and LPPHY regs are separated === */ 4718 4719 /* Bits in phytest(0x0a): */ 4720 #define TST_DDFS 0x2000 4721 #define TST_TXFILT1 0x0800 4722 #define TST_UNSCRAM 0x0400 4723 #define TST_CARR_SUPP 0x0200 4724 #define TST_DC_COMP_LOOP 0x0100 4725 #define TST_LOOPBACK 0x0080 4726 #define TST_TXFILT0 0x0040 4727 #define TST_TXTEST_ENABLE 0x0020 4728 #define TST_TXTEST_RATE 0x0018 4729 #define TST_TXTEST_PHASE 0x0007 4730 4731 /* phytest txTestRate values */ 4732 #define TST_TXTEST_RATE_1MBPS 0 4733 #define TST_TXTEST_RATE_2MBPS 1 4734 #define TST_TXTEST_RATE_5_5MBPS 2 4735 #define TST_TXTEST_RATE_11MBPS 3 4736 #define TST_TXTEST_RATE_SHIFT 3 4737 4738 typedef struct shm_mbss_prq_entry_s shm_mbss_prq_entry_t; 4739 BWL_PRE_PACKED_STRUCT struct shm_mbss_prq_entry_s { 4740 struct ether_addr ta; 4741 uint8 prq_info[2]; 4742 uint8 time_stamp; 4743 uint8 flags; /**< bit 0 HT STA Indication, bit 7:1 Reserved */ 4744 } BWL_POST_PACKED_STRUCT; 4745 4746 typedef enum shm_mbss_prq_ft_e { 4747 SHM_MBSS_PRQ_FT_CCK, 4748 SHM_MBSS_PRQ_FT_OFDM, 4749 SHM_MBSS_PRQ_FT_MIMO, 4750 SHM_MBSS_PRQ_FT_RESERVED 4751 } shm_mbss_prq_ft_t; 4752 4753 #define SHM_MBSS_PRQ_FT_COUNT SHM_MBSS_PRQ_FT_RESERVED 4754 4755 #define SHM_MBSS_PRQ_ENT_FRAMETYPE(entry) ((entry)->prq_info[0] & 0x3) 4756 #define SHM_MBSS_PRQ_ENT_UPBAND(entry) ((((entry)->prq_info[0] >> 2) & 0x1) != 0) 4757 4758 /** What was the index matched? */ 4759 #define SHM_MBSS_PRQ_ENT_UC_BSS_IDX(entry) (((entry)->prq_info[0] >> 2) & 0x3) 4760 #define SHM_MBSS_PRQ_ENT_PLCP0(entry) ((entry)->prq_info[1]) 4761 4762 /** Was this directed to a specific SSID or BSSID? If bit clear, quantity known */ 4763 #define SHM_MBSS_PRQ_ENT_DIR_SSID(entry) \ 4764 ((((entry)->prq_info[0] >> 6) == 0) || ((entry)->prq_info[0] >> 6) == 1) 4765 #define SHM_MBSS_PRQ_ENT_DIR_BSSID(entry) \ 4766 ((((entry)->prq_info[0] >> 6) == 0) || ((entry)->prq_info[0] >> 6) == 2) 4767 4768 #define SHM_MBSS_PRQ_ENT_TIMESTAMP(entry) ((entry)->time_stamp) 4769 /** Was the probe request from a ht STA or a legacy STA */ 4770 #define SHM_MBSS_PRQ_ENT_HTSTA(entry) ((entry)->flags & 0x1) 4771 4772 typedef struct d11ac_tso_s d11ac_tso_t; 4773 4774 BWL_PRE_PACKED_STRUCT struct d11ac_tso_s { 4775 uint8 flag[3]; 4776 uint8 sfh_hdr_offset; 4777 uint16 tso_mss; /**< tso segment size */ 4778 uint16 msdu_siz; /**< msdu size */ 4779 uint32 tso_payload_siz; /**< total byte cnt in tcp payload */ 4780 uint16 ip_hdr_offset; /**< relative to the start of txd header */ 4781 uint16 tcp_hdr_offset; /**< relative to start of txd header */ 4782 } BWL_POST_PACKED_STRUCT; 4783 4784 /* toe_ctl TCP offload engine register definitions */ 4785 #define TOE_CTL_DISAB (1u << 0) 4786 #define TOE_CTL_MASK (1u << 0) 4787 #define TOE_CTL_ENAB (0xFFFEu) 4788 #define TOE_CLK_GATING_DISAB (1u << 1) 4789 4790 #define TSO_HDR_TOE_FLAG_OFFSET (0u) 4791 4792 #define TOE_F0_HDRSIZ_NORMAL (1u << 0) 4793 #define TOE_F0_PASSTHROUGH (1u << 1) 4794 #define TOE_F0_TCPSEG_EN (1u << 3) 4795 #define TOE_F0_IPV4 (1u << 4) 4796 #define TOE_F0_IPV6 (1u << 5) 4797 #define TOE_F0_TCP (1u << 6) 4798 #define TOE_F0_UDP (1u << 7) 4799 4800 #define TOE_F1_IPV4_CSUM_EN (1u << 0) 4801 #define TOE_F1_TCPUDP_CSUM_EN (1u << 1) 4802 #define TOE_F1_PSEUDO_CSUM_EN (1u << 2) 4803 #define TOE_F1_FRAG_ALLOW (1u << 5) 4804 #define TOE_F1_FRAMETYPE_1 (1u << 6) 4805 #define TOE_F1_FRAMETYPE_2 (1u << 7) 4806 #define TOE_F1_FT_MASK (TOE_F1_FRAMETYPE_1 | TOE_F1_FRAMETYPE_2) 4807 #define TOE_F1_FT_SHIFT (6u) 4808 4809 #define TOE_F2_TXD_HEAD_SHORT (1u << 0) 4810 #define TOE_F2_EPOCH_SHIFT (1u) 4811 #define TOE_F2_EPOCH (1u << TOE_F2_EPOCH_SHIFT) 4812 #define TOE_F2_EPOCH_EXT (1u << 2) 4813 #define TOE_F2_EPOCH_EXT_MASK (TOE_F2_EPOCH | TOE_F2_EPOCH_EXT) 4814 #define TOE_F2_AMSDU_AGGR_EN (1u << 4) 4815 #define TOE_F2_AMSDU_CSUM_EN (1u << 5) 4816 #define TOE_F2_AMSDU_FS_MID (1u << 6) 4817 #define TOE_F2_AMSDU_FS_LAST (1u << 7) 4818 4819 #define TOE_TXDMA_FLAGS_AMSDU_FIRST (0x14u) 4820 #define TOE_TXDMA_FLAGS_AMSDU_MID (0x24u) 4821 #define TOE_TXDMA_FLAGS_AMSDU_LAST (0x34u) 4822 4823 /* This marks the end of a packed structure section. */ 4824 #include <packed_section_end.h> 4825 4826 #define SHM_BYT_CNT 0x2 /**< IHR location */ 4827 #define MAX_BYT_CNT 0x600 /**< Maximum frame len */ 4828 4829 /* WOWL Template Regions */ 4830 #define WOWL_NS_CHKSUM (0x57 * 2) 4831 #define WOWL_PSP_TPL_BASE (0x334 * 2) 4832 #define WOWL_GTK_MSG2 (0x434 * 2) 4833 #define WOWL_NS_OFFLOAD (0x634 * 2) 4834 #define T_KEEPALIVE_0 (0x6b4 * 2) 4835 #define T_KEEPALIVE_1 ((0x6b4 + 0x40) * 2) 4836 #define WOWL_ARP_OFFLOAD (0x734 * 2) 4837 #define WOWL_TX_FIFO_TXRAM_BASE (0x774 * 2) /**< conservative, leave 1KB for GTKM2 */ 4838 4839 /* template regions for 11ac */ 4840 #define D11AC_WOWL_PSP_TPL_BASE (0x4c0 * 2) 4841 #define D11AC_WOWL_GTK_MSG2 (0x5c0 * 2) /**< for core rev >= 42 */ 4842 #define WOWL_NS_OFFLOAD_GE42 (0x7c0 * 2) 4843 #define T_KEEPALIVE_0_GE42 (0x840 * 2) 4844 #define T_KEEPALIVE_1_GE42 ((0x840 + 0x40) * 2) 4845 #define WOWL_ARP_OFFLOAD_GE42 (0x8c0 * 2) 4846 #define D11AC_WOWL_TX_FIFO_TXRAM_BASE (0x900 * 2) /**< GTKM2 for core rev >= 42 */ 4847 4848 /* Event definitions */ 4849 #define WOWL_MAGIC (1 << 0) /**< Wakeup on Magic packet */ 4850 #define WOWL_NET (1 << 1) /**< Wakeup on Netpattern */ 4851 #define WOWL_DIS (1 << 2) /**< Wakeup on loss-of-link due to Disassoc/Deauth */ 4852 #define WOWL_RETR (1 << 3) /**< Wakeup on retrograde TSF */ 4853 #define WOWL_BCN (1 << 4) /**< Wakeup on loss of beacon */ 4854 #define WOWL_TST (1 << 5) /**< Wakeup after test */ 4855 #define WOWL_M1 (1 << 6) /**< Wakeup after PTK refresh */ 4856 #define WOWL_EAPID (1 << 7) /**< Wakeup after receipt of EAP-Identity Req */ 4857 #define WOWL_PME_GPIO (1 << 8) /**< Wakeind via PME(0) or GPIO(1) */ 4858 #define WOWL_NEEDTKIP1 (1 << 9) /**< need tkip phase 1 key to be updated by the driver */ 4859 #define WOWL_GTK_FAILURE (1 << 10) /**< enable wakeup if GTK fails */ 4860 #define WOWL_EXTMAGPAT (1 << 11) /**< support extended magic packets */ 4861 #define WOWL_ARPOFFLOAD (1 << 12) /**< support ARP/NS offloading */ 4862 #define WOWL_WPA2 (1 << 13) /**< read protocol version for EAPOL frames */ 4863 #define WOWL_KEYROT (1 << 14) /**< If the bit is set, use key rotaton */ 4864 #define WOWL_BCAST (1 << 15) /**< If the bit is set, frm received was bcast frame */ 4865 4866 #define MAXBCNLOSS (1 << 13) - 1 /**< max 12-bit value for bcn loss */ 4867 4868 /* UCODE shm view: 4869 * typedef struct { 4870 * uint16 offset; // byte offset 4871 * uint16 patternsize; // the length of value[.] in bytes 4872 * uchar bitmask[MAXPATTERNSIZE/8]; // 16 bytes, the effect length is (patternsize+7)/8 4873 * uchar value[MAXPATTERNSIZE]; // 128 bytes, the effect length is patternsize. 4874 * } netpattern_t; 4875 */ 4876 #define NETPATTERNSIZE (148) /* 128 value + 16 mask + 4 offset + 4 patternsize */ 4877 #define MAXPATTERNSIZE 128 4878 #define MAXMASKSIZE MAXPATTERNSIZE/8 4879 4880 /** Security Algorithm defines */ 4881 #define WOWL_TSCPN_SIZE 6 4882 #define WOWL_TSCPN_COUNT 4 /**< 4 ACs */ 4883 #define WOWL_TSCPN_BLK_SIZE (WOWL_TSCPN_SIZE * WOWL_TSCPN_COUNT) 4884 4885 #define WOWL_SECSUITE_GRP_ALGO_MASK 0x0007 4886 #define WOWL_SECSUITE_GRP_ALGO_SHIFT 0 4887 #define WOWL_SECSUITE_ALGO_MASK 0x0700 4888 #define WOWL_SECSUITE_ALGO_SHIFT 8 4889 4890 #define EXPANDED_KEY_RNDS 10 4891 #define EXPANDED_KEY_LEN 176 /* the expanded key from KEK (4*11*4, 16-byte state, 11 rounds) */ 4892 4893 /* Organization of Template RAM is as follows 4894 * typedef struct { 4895 * uint8 AES_XTIME9DBE[1024]; 4896 * uint8 AES_INVSBOX[256]; 4897 * uint8 AES_KEYW[176]; 4898 * } AES_TABLES_t; 4899 */ 4900 /* See dot11_firmware/diag/wmac_tcl/wmac_762_wowl_gtk_aes: proc write_aes_tables, 4901 * for an example of writing those tables into the tx fifo buffer. 4902 */ 4903 4904 typedef struct { 4905 uint16 MacTxControlLow; /**< mac-tx-ctl-low word */ 4906 uint16 MacTxControlHigh; /**< mac-tx-ctl-high word */ 4907 uint16 PhyTxControlWord; /**< phy control word */ 4908 uint16 PhyTxControlWord_1; /**< extra phy control word for mimophy */ 4909 union { 4910 uint16 XtraFrameTypes; /**< frame type for RTS/FRAG fallback (used only for AES) */ 4911 uint16 bssenc_pos; /**< BssEnc includes key ID , for corerev >= 42 */ 4912 } u1; 4913 uint8 plcp[6]; /**< plcp of template */ 4914 4915 uint16 mac_frmtype; /**< MAC frame type for GTK MSG2, can be 4916 * dot11_data frame (0x20) or dot11_QoS_Data frame (0x22). 4917 */ 4918 uint16 frm_bytesize; /**< number of bytes in the template, it includes: 4919 * PLCP, MAC header, IV/EIV, the data payload 4920 * (eth-hdr and EAPOL-Key), TKIP MIC 4921 */ 4922 uint16 payload_wordoffset; /**< the word offset of the data payload */ 4923 4924 /* ALIGN */ 4925 uint16 seqnum; /**< Sequence number for this frame */ 4926 uint8 seciv[18]; /**< 10-byte TTAK used for TKIP, 8-byte IV/EIV. 4927 * See <SecurityInitVector> in the general tx descriptor. 4928 */ 4929 } wowl_templ_ctxt_t; 4930 4931 #define WOWL_TEMPL_CTXT_LEN 42 /**< For making sure that no PADs are needed */ 4932 #define WOWL_TEMPL_CTXT_FRMTYPE_DATA 0x2 4933 #define WOWL_TEMPL_CTXT_FRMTYPE_QOS 0x22 4934 4935 /** constant tables required for AES key unwrapping for key rotation */ 4936 extern uint16 aes_invsbox[128]; 4937 extern uint16 aes_xtime9dbe[512]; 4938 4939 #define MAX_MPDU_SPACE (D11_TXH_LEN + 1538) 4940 4941 /* Bits in TXE_BMCCTL */ 4942 #define BMCCTL_INITREQ_SHIFT 0 4943 #define BMC_CTL_DONE (1 << BMCCTL_INITREQ_SHIFT) 4944 #define BMCCTL_RESETSTATS_SHIFT 1 4945 #define BMCCTL_TXBUFSIZE_SHIFT 2 4946 #define BMCCTL_LOOPBACK_SHIFT 5 4947 #define BMCCTL_TXBUFSZ_MASK ((1 << BMCCTL_LOOPBACK_SHIFT) - (1 << BMCCTL_TXBUFSIZE_SHIFT)) 4948 #define BMCCTL_CLKGATEEN_SHIFT 8 4949 4950 /* Bits in TXE_BMCConfig */ 4951 #define BMCCONFIG_BUFCNT_SHIFT 0 4952 #define BMCCONFIG_DISCLKGATE_SHIFT 13 4953 #define BMCCONFIG_BUFCNT_MASK ((1 << BMCCONFIG_DISCLKGATE_SHIFT) - (1 << BMCCONFIG_BUFCNT_SHIFT)) 4954 4955 /* Bits in TXE_BMCStartAddr */ 4956 #define BMCSTARTADDR_STRTADDR_MASK 0x3ff 4957 4958 /* Bits in TXE_BMCDescrLen */ 4959 #define BMCDescrLen_ShortLen_SHIFT 0 4960 #define BMCDescrLen_LongLen_SHIFT 8 4961 4962 /* Bits in TXE_BMCAllocCtl */ 4963 #define BMCAllocCtl_AllocCount_SHIFT 0 4964 /* Rev==50 || Rev>52 4965 * BMCAllocCtl.AllocCount [0:10] 4966 * BMCAllocCtl.AllocThreshold [11:14] 4967 * !Rev50 4968 * BMCAllocCtl.AllocCount [0:7] 4969 * BMCAllocCtl.AllocThreshold [8:15] 4970 */ 4971 #define BMCAllocCtl_AllocThreshold_SHIFT_Rev50 11 4972 #define BMCAllocCtl_AllocThreshold_SHIFT 8 4973 4974 /* Bits in TXE_BMCCmd1 */ 4975 #define BMCCMD1_TIDSEL_SHIFT 1 4976 #define BMCCMD1_RDSRC_SHIFT 6 4977 #define BMCCmd1_RXMapPassThru_SHIFT 12 4978 #define BMCCMD1_BQSelNum_SHIFT 1u 4979 #define BMCCMD1_BQSelType_SHIFT 7u 4980 #define BMCCMD1_RDSRC_Group0 0u /* register itself */ 4981 #define BMCCMD1_RDSRC_Group1 1u /* staged max/min */ 4982 #define BMCCMD1_RDSRC_Group2 2u /* staged max/previous min */ 4983 #define BMCCMD1_RDSRC_Group3 3u /* active max/min */ 4984 #define BMCCMD1_RDSRC_SHIFT_rev80 10u 4985 #define BMCCMD1_CoreSel_SHIFT 13u 4986 #define BMCCMD1_CoreSel_SHIFT_rev80 15u 4987 4988 /* Bits in TXE_BMCCmd */ 4989 #define BMCCmd_TIDSel_SHIFT 0 4990 #define BMCCmd_Enable_SHIFT 4 4991 #define BMCCmd_ReleasePreAlloc_SHIFT 5 4992 #define BMCCmd_ReleasePreAllocAll_SHIFT 6 4993 #define BMCCmd_UpdateBA_SHIFT 7 4994 #define BMCCmd_Consume_SHIFT 8 4995 #define BMCCmd_Aggregate_SHIFT 9 4996 #define BMCCmd_UpdateRetryCount_SHIFT 10 4997 #define BMCCmd_DisableTID_SHIFT 11 4998 4999 #define BMCCmd_BQSelType_TX 0 5000 #define BMCCmd_BQSelType_RX 1 5001 #define BMCCmd_BQSelType_Templ 2 5002 5003 /* Bits in TXE_BMCCMD for rev >= 80 */ 5004 #define BMCCmd_BQSelType_MASK_Rev80 0x00c0 5005 #define BMCCmd_BQSelType_SHIFT_Rev80 6 5006 #define BMCCmd_Enable_SHIFT_rev80 8 5007 #define BMCCmd_ReleasePreAllocAll_SHIFT_rev80 10 5008 5009 /* Bits in TXE_BMCCmd1 */ 5010 #define BMCCmd1_Minmaxappall_SHIFT 0 5011 #define BMCCmd1_Minmaxlden_SHIFT 5 5012 #define BMCCmd1_Minmaxffszlden_SHIFT 8 5013 #define BMCCmd_Core1_Sel_MASK 0x2000 5014 5015 /* Bits in TXE_BMCStatCtl */ 5016 #define BMCStatCtl_TIDSel_SHIFT 0u 5017 #define BMCStatCtl_STATSel_SHIFT 4u 5018 #define BMCStatCtl_BQSelNum_SHIFT 0u 5019 #define BMCStatCtl_BQSelType_SHIFT 6u 5020 #define BMCStatCtl_STATSel_SHIFT_rev80 8u 5021 5022 /* Bits in BMVpConfig */ 5023 #define BMCVPConfig_SingleVpModePortA_SHIFT 4 5024 5025 /* Bits in TXE_PsmMSDUAccess */ 5026 #define PsmMSDUAccess_TIDSel_SHIFT 0 5027 #define PsmMSDUAccess_MSDUIdx_SHIFT 4 5028 #define PsmMSDUAccess_ReadBusy_SHIFT 14 5029 #define PsmMSDUAccess_WriteBusy_SHIFT 15 5030 5031 /* Bits in TXE_PsmMSDUAccess for rev >= 80 */ 5032 #define PsmMSDUAccess_BQSelType_SHIFT 5 5033 #define PsmMSDUAccess_MSDUIdx_SHIFT_rev80 7 5034 #define PsmMSDUAccess_BQSelType_Templ 2 5035 #define PsmMSDUAccess_BQSelType_TX 0 5036 5037 #ifdef WLRSDB 5038 #define MAX_RSDB_MAC_NUM 2 5039 #else 5040 #define MAX_RSDB_MAC_NUM 1 5041 #endif 5042 #define MAX_MIMO_MAC_NUM 1 5043 5044 #ifdef WL_SCAN_CORE 5045 #define MAX_MAC_CORE_NUM (MAX_RSDB_MAC_NUM + 1) 5046 #else 5047 #define MAX_MAC_CORE_NUM (MAX_RSDB_MAC_NUM) 5048 #endif /* WL_SCAN_CORE */ 5049 5050 #define MAC_CORE_UNIT_0 0x0u /**< First mac core unit */ 5051 #define MAC_CORE_UNIT_1 0x1u /**< Second mac core unit */ 5052 5053 /* HW unit of scan core. 5054 * This is used to overwrite the tunables specific to scan core 5055 */ 5056 #define SCAN_CORE_UNIT 0x2u 5057 5058 /* Supported phymodes / macmodes / opmodes */ 5059 #define SINGLE_MAC_MODE 0x0 /**< only single mac is enabled */ 5060 #define DUAL_MAC_MODE 0x1 /**< enables dual mac */ 5061 /* (JIRA: CRDOT11ACPHY-652) Following two #defines support 5062 * exclusive reg access to core 0/1 in MIMO mode 5063 */ 5064 #define SUPPORT_EXCLUSIVE_REG_ACCESS_CORE0 0x2 5065 #define SUPPORT_EXCLUSIVE_REG_ACCESS_CORE1 0x4 /**< not functional in 4349A0 */ 5066 #define SUPPORT_CHANNEL_BONDING 0x8 /**< enables channel bonding, 5067 * supported in single mac mode only 5068 */ 5069 #define SCAN_CORE_ACTIVE 0x10 /* scan core enabled for background DFS */ 5070 5071 #define PHYMODE_MIMO (SINGLE_MAC_MODE) 5072 #define PHYMODE_80P80 (SINGLE_MAC_MODE | SUPPORT_CHANNEL_BONDING) 5073 #define PHYMODE_RSDB_SISO_0 (DUAL_MAC_MODE | SUPPORT_EXCLUSIVE_REG_ACCESS_CORE0) 5074 #define PHYMODE_RSDB_SISO_1 (DUAL_MAC_MODE | SUPPORT_EXCLUSIVE_REG_ACCESS_CORE1) 5075 #define PHYMODE_RSDB (PHYMODE_RSDB_SISO_0 | PHYMODE_RSDB_SISO_1) 5076 #define PHYMODE_BGDFS 31 5077 #define PHYMODE_3x3_1x1 31 5078 5079 #define RX_INTR_FIFO_0 0x1 /**< FIFO-0 interrupt */ 5080 #define RX_INTR_FIFO_1 0x2 /**< FIFO-1 interrupt */ 5081 #define RX_INTR_FIFO_2 0x4 /**< FIFO-2 interrupt */ 5082 5083 #define MAX_RX_FIFO 3 5084 5085 #define RX_CTL_FIFOSEL_SHIFT 8 5086 #define RX_CTL_FIFOSEL_MASK (0x3 << RX_CTL_FIFOSEL_SHIFT) 5087 5088 #define RCO_EN (0x1u) /**< Receive checksum offload */ 5089 5090 /* MAC_PTM_CTRL1 bit definitions */ 5091 #define PTM_RX_TMSTMP_CAPTURE_EN 0x0001u 5092 #define PTM_TX_TMSTMP_CAPTURE_EN 0x0001u 5093 #define PTM_TMSTMP_OVERRIDE_EN 0x1000u 5094 5095 /* For corerev >= 64 5096 * Additional DMA descriptor flags for AQM Descriptor. These are used in 5097 * conjunction with the descriptor control flags defined in sbhnddma.h 5098 */ 5099 /* AQM DMA Descriptor control flags 1 */ 5100 #define D64_AQM_CTRL1_SOFPTR 0x0000FFFF /* index of the descr which 5101 * is SOF decriptor in DMA table 5102 */ 5103 #define D64_AQM_CTRL1_EPOCH 0x00010000 /* Epoch bit for the frame */ 5104 #define D64_AQM_CTRL1_NUMD_MASK 0x00F00000 /* NumberofDescriptors(NUMD) */ 5105 #define D64_AQM_CTRL1_NUMD_SHIFT 20 5106 #define D64_AQM_CTRL1_AC_MASK 0x0F000000 /* AC of the current frame */ 5107 #define D64_AQM_CTRL1_AC_SHIFT 24 5108 5109 /* AQM DMA Descriptor control flags 2 */ 5110 #define D64_AQM_CTRL2_MPDULEN_MASK 0x00003FFF /* Length of the entire MPDU */ 5111 #define D64_AQM_CTRL2_TXDTYPE 0x00080000 /* When set to 1 the long form of the 5112 * TXD is used for the frame. 5113 */ 5114 /* For corerev >= 83 5115 * DMA descriptor flags for AQM Descriptor. These are used in 5116 * conjunction with the descriptor control flags defined in sbhnddma.h 5117 */ 5118 /* AQM DMA Descriptor control flags 1 */ 5119 #define D11_REV83_AQM_DESC_CTRL1_SOFPTR 0x0000FFFFu /* index of the descr which 5120 * is SOF decriptor in DMA table 5121 */ 5122 #define D11_REV83_AQM_DESC_CTRL1_EPOCH_SHIFT 16u 5123 #define D11_REV83_AQM_DESC_CTRL1_EPOCH (1u << D11_REV83_AQM_DESC_CTRL1_EPOCH_SHIFT) 5124 #define D11_REV83_AQM_DESC_CTRL1_EPOCH_EXT_SHIFT 17u 5125 #define D11_REV83_AQM_DESC_CTRL1_EPOCH_EXT (1u << \ 5126 D11_REV83_AQM_DESC_CTRL1_EPOCH_EXT_SHIFT) 5127 #define D11_REV83_AQM_DESC_CTRL1_EPOCH_MASK (D11_REV83_AQM_DESC_CTRL1_EPOCH | \ 5128 D11_REV83_AQM_DESC_CTRL1_EPOCH_EXT) 5129 #define D11_REV83_AQM_DESC_CTRL1_RESV1 0x00040000u /* RESERVED */ 5130 #define D11_REV83_AQM_DESC_CTRL1_FRAGALLOW_SHIFT 19u /* Fragmentation allowance flag 5131 * shift. 5132 */ 5133 #define D11_REV83_AQM_DESC_CTRL1_FRAGALLOW (1u << D11_REV83_AQM_DESC_CTRL1_FRAGALLOW_SHIFT) 5134 /* Fragmentation allowance flag 5135 * of the frame 5136 */ 5137 #define D11_REV83_AQM_DESC_CTRL1_NUMD_SHIFT 20u /* NumberofDescriptors(NUMD) */ 5138 #define D11_REV83_AQM_DESC_CTRL1_NUMD_MASK (0xFu << D11_REV83_AQM_DESC_CTRL1_NUMD_SHIFT) 5139 #define D11_REV83_AQM_DESC_CTRL1_AC_SHIFT 24u /* AC of the current frame */ 5140 #define D11_REV83_AQM_DESC_CTRL1_AC_MASK (0xFu << D11_REV83_AQM_DESC_CTRL1_AC_SHIFT) 5141 #define D11_REV83_AQM_DESC_CTRL1_ET 0x10000000u /* End of table */ 5142 #define D11_REV83_AQM_DESC_CTRL1_IC 0x20000000u /* Interrupt on Completion */ 5143 #define D11_REV83_AQM_DESC_CTRL1_RESV2 0x40000000u /* Used to be EF: End of frame, 5144 * and would have been set to 1. 5145 */ 5146 #define D11_REV83_AQM_DESC_CTRL1_RESV3 0x80000000u /* Used to be SF: Start of Frame, 5147 * and would have been set to 1 5148 */ 5149 5150 /* AQM DMA Descriptor control flags 2 */ 5151 #define D11_REV83_AQM_DESC_CTRL2_MPDULEN_MASK 0x00003FFFu /* Length of the entire MPDU */ 5152 #define D11_REV83_AQM_DESC_CTRL2_FTYPE_SHIFT 14u /* Frame Type, Indicate whether 5153 * frame is Data, Management or 5154 * Control Frame. 2 bits: 5155 * 2'b00=Data, 2'b01=Management, 5156 * 2'b10=Control, 2'b11=Invalid 5157 * value 5158 */ 5159 #define D11_REV83_AQM_DESC_CTRL2_FTYPE_MASK (0x3u << D11_REV83_AQM_DESC_CTRL2_FTYPE_SHIFT) 5160 #define D11_REV83_AQM_DESC_CTRL2_PTXDLENIDX_SHIFT 16u /* pTxD length index in 4-deep table */ 5161 #define D11_REV83_AQM_DESC_CTRL2_PTXDLENIDX_MASK (0x3u << \ 5162 D11_REV83_AQM_DESC_CTRL2_PTXDLENIDX_SHIFT) 5163 #define D11_REV83_AQM_DESC_CTRL2_PT 0x00040000u /* Parity bit. Choose a 5164 * value such that the entire 5165 * descriptor haseven parity 5166 */ 5167 #define D11_REV83_AQM_DESC_CTRL2_USERIT 0x00080000u /* If set, the Rate Table Index and 5168 * RIT entry are fetched into SHM by 5169 * hardware. Otherwise, software 5170 * uses pTxD to convey this 5171 * information to ucode 5172 */ 5173 #define D11_REV83_AQM_DESC_CTRL2_USELIT 0x00100000u /* If set, the Link Info Table Index 5174 * and LIT entry are fetched into 5175 * SHM by hardware. Otherwise, 5176 * software uses pTxD to convey this 5177 * information to ucode 5178 */ 5179 #define D11_REV83_AQM_DESC_CTRL2_LIT_SHIFT 21u /* LTI(Link info Table Index) */ 5180 #define D11_REV83_AQM_DESC_CTRL2_LIT_MASK (0x3Fu << D11_REV83_AQM_DESC_CTRL2_LIT_SHIFT) 5181 #define D11_REV83_AQM_DESC_CTRL2_RIT_SHIFT 27u /* bit[4:0] of RTI(Rate info Table Index) */ 5182 #define D11_REV83_AQM_DESC_CTRL2_RIT_MASK (0x1Fu << D11_REV83_AQM_DESC_CTRL2_RIT_SHIFT) 5183 5184 /* AQM DMA Descriptor control flags 3 */ 5185 #define D11_REV86_AQM_DESC_CTRL3_RTI_BIT5 0x00000001u /* bit[5] of RTI (cont'd from ctrl2) */ 5186 #define D11_REV86_AQM_DESC_CTRL3_RTI_BIT5_MASK 1u /* bit[5] of RTI (cont'd from ctrl2) */ 5187 #define D11_REV86_AQM_DESC_CTRL3_RTI_BIT5_SHIFT 0u 5188 #define D11_REV83_AQM_DESC_CTRL3_AGGR_ID 0x0000000Eu /* Aggregation ID */ 5189 #define D11_REV83_AQM_DESC_CTRL3_CO 0x00000010u /* Coherency */ 5190 #define D11_REV84_AQM_DESC_CTRL3_TXDPTR_SHIFT 5u /* TxD ptr */ 5191 #define D11_REV84_AQM_DESC_CTRL3_TXDPTR_MASK 0xFFFFFFu /* bit[23:0] of TxD addr */ 5192 #define D11_REV86_AQM_DESC_CTRL3_TID_SHIFT 29u /* TID for BSR */ 5193 #define D11_REV86_AQM_DESC_CTRL3_TID_MASK (0x7u << D11_REV86_AQM_DESC_CTRL3_TID_SHIFT) 5194 5195 /* values for psm_patchcopy_ctrl (0x1AC) post corerev 60 */ 5196 #define PSM_PATCHCC_PMODE_MASK (0x3) 5197 #define PSM_PATCHCC_PMODE_RAM (0) /* default */ 5198 #define PSM_PATCHCC_PMODE_ROM_RO (1) 5199 #define PSM_PATCHCC_PMODE_ROM_PATCH (2) 5200 5201 #define PSM_PATCHCC_PENG_TRIGGER_SHIFT (2) 5202 #define PSM_PATCHCC_PENG_TRIGGER_MASK (1 << PSM_PATCHCC_PENG_TRIGGER_SHIFT) 5203 #define PSM_PATCHCC_PENG_TRIGGER (1 << PSM_PATCHCC_PENG_TRIGGER_SHIFT) 5204 5205 #define PSM_PATCHCC_PCTRL_RST_SHIFT (3) 5206 #define PSM_PATCHCC_PCTRL_RST_MASK (0x3 << PSM_PATCHCC_PCTRL_RST_SHIFT) 5207 #define PSM_PATCHCC_PCTRL_RST_RESET (0x0 << PSM_PATCHCC_PCTRL_RST_SHIFT) 5208 #define PSM_PATCHCC_PCTRL_RST_HW (0x1 << PSM_PATCHCC_PCTRL_RST_SHIFT) 5209 5210 #define PSM_PATCHCC_COPYEN_SHIFT (5) 5211 #define PSM_PATCHCC_COPYEN_MASK (1 << PSM_PATCHCC_COPYEN_SHIFT) 5212 #define PSM_PATCHCC_COPYEN (1 << PSM_PATCHCC_COPYEN_SHIFT) 5213 5214 #define PSM_PATCHCC_UCIMGSEL_SHIFT (16) 5215 #define PSM_PATCHCC_UCIMGSEL_MASK (0x30000) 5216 #define PSM_PATCHCC_UCIMGSEL_DS0 (0x00000) /* default image */ 5217 #define PSM_PATCHCC_UCIMGSEL_DS1 (0x10000) /* image 1 */ 5218 5219 /* patch copy delay for psm: 2millisec */ 5220 #define PSM_PATCHCOPY_DELAY (2000) 5221 5222 /* START-below WAS in d11_if_shm.h which we can move to auto shm. 5223 * Some of them are offsets, but some of them are not given by ucode [possibly legacy] 5224 * so, not taken care by autoshm. 5225 */ 5226 5227 /* Addr is byte address used by SW; offset is word offset used by uCode */ 5228 5229 /** Per AC TX limit settings */ 5230 #define M_AC_TXLMT_ADDR(x, _ac) (M_AC_TXLMT_BLK(x) + (2 * (_ac))) 5231 5232 /** delay from end of PLCP reception to RxTSFTime */ 5233 #define M_APHY_PLCPRX_DLY 3 5234 #define M_BPHY_PLCPRX_DLY 4 5235 5236 /* btcx debug shmem size */ 5237 #define C_BTCX_DBGBLK_SZ 6 /**< Number of 16bit words */ 5238 #define C_BTCX_DBGBLK2_SZ 11 /* size of statistics at 2nd SHM segment */ 5239 5240 #define C_BTCX_STATS_DBGBLK_SZ 18 /* total size of statistics at A2DP stats */ 5241 #define C_BTCX_A2DP_PRI_SZ 6 /* size of a2dp priority counters stats */ 5242 #define C_BTCX_A2DP_BUFCNT_SZ 8 /* size of a2dp buffer counters stats */ 5243 #define C_BTCX_ANT_GRANT_SZ 4 /* size of ant granted duration to BT */ 5244 #define C_BTCX_STATS_ECNTR_BLK_SZ C_BTCX_STATS_DBGBLK_SZ /* blk size for btcx ecounters */ 5245 5246 #define D11_DMA_CHANNELS 6 5247 5248 /* WME shared memory */ 5249 #define M_EDCF_STATUS_OFF(x) (0x007 * 2) 5250 5251 /* Beacon-related parameters */ 5252 #define M_BCN_LI(x) M_PS_MORE_DTIM_TBTT(x) /**< beacon listen interval */ 5253 5254 /* prerev 40 defines */ 5255 #define D11_PRE40_M_SECKINDXALGO_BLK(x) (0x2ea * 2) 5256 5257 /* corerev 40 defines */ 5258 /* BLK SIZE needs to change for GE64 */ 5259 #define D11_POST80_MAX_KEY_SIZE 32 5260 #define D11_PRE80_MAX_KEY_SIZE 16 5261 5262 #define D11_MAX_KEY_SIZE(_corerev) ((D11REV_GE(_corerev, 80)) ? \ 5263 D11_POST80_MAX_KEY_SIZE : D11_PRE80_MAX_KEY_SIZE) 5264 5265 #define M_SECKINDXALGO_BLK_SZ(_corerev) (AMT_SIZE(_corerev) + 4 /* default keys */) 5266 5267 #define C_CTX_PCTLWD_POS (0x4 * 2) 5268 5269 #define D11_MAX_TX_FRMS 32 /**< max frames allowed in tx fifo */ 5270 5271 /* Current channel number plus upper bits */ 5272 #define D11_CURCHANNEL_5G 0x0100; 5273 #define D11_CURCHANNEL_40 0x0200; 5274 #define D11_CURCHANNEL_MAX 0x00FF; 5275 5276 #define INVALIDFID 0xffff 5277 5278 #define D11_RT_DIRMAP_SIZE 16 5279 5280 /** Rate table entry offsets */ 5281 #define M_RT_PRS_PLCP_POS(x) 10 5282 #define M_RT_PRS_DUR_POS(x) 16 5283 #define M_RT_OFDM_PCTL1_POS(x) 18 5284 #define M_RT_TXPWROFF_POS(x) 20 5285 #define M_REV40_RT_TXPWROFF_POS(x) 14 5286 5287 #define MIMO_MAXSYM_DEF 0x8000 /* 32k */ 5288 #define MIMO_MAXSYM_MAX 0xffff /* 64k */ 5289 5290 #define WATCHDOG_8TU_DEF_LT42 5 5291 #define WATCHDOG_8TU_MAX_LT42 10 5292 #define WATCHDOG_8TU_DEF 3 5293 #define WATCHDOG_8TU_MAX 4 5294 5295 #define M_PKTENG_RXAVGPWR_ANT(x, w) (M_MFGTEST_RXAVGPWR_ANT0(x) + (w) * 2) 5296 5297 /* M_MFGTEST_NUM (pkt eng) bit definitions */ 5298 #define MFGTEST_TXMODE 0x0001 /* TX frames indefinitely */ 5299 #define MFGTEST_RXMODE 0x0002 /* RX frames */ 5300 #define MFGTEST_RXMODE_ACK 0x0402 /* RX frames with sending ACKs back */ 5301 #define MFGTEST_RXMODE_FWD2FW 0x8000 /* RX frames - forward packet to the fw */ 5302 #define MFGTEST_TXMODE_FRMCNT 0x0101 /* TX frames by frmcnt */ 5303 #define MFGTEST_RU_TXMODE 0x0011 /* RU frames TX indefinetly */ 5304 #define MFGTEST_RU_TXMODE_FRMCNT 0x0111 /* RU TX frames by frmcnt */ 5305 5306 /* UOTA interface bit definitions */ 5307 enum { 5308 C_UOTA_CNTSRT_NBIT = 0, /* 0 OTA rx frame count start bit (14 LSB's) */ 5309 C_UOTA_RXFST_NBIT = 14, /* 14 indicating first frame */ 5310 C_UOTA_RSSION_NBIT = 15, /* 15 OTA rx ON bit position */ 5311 }; 5312 5313 #define M_EDCF_QLEN(x) (M_EDCF_QINFO1_OFFSET(x)) 5314 #define M_PWRIND_MAP(x, core) (M_PWRIND_BLKS(x) + ((core)<<1)) 5315 5316 #define M_BTCX_MAX_INDEX 320u 5317 #define M_BTCX_BACKUP_SIZE 130 5318 #define BTCX_AMPDU_MAX_DUR 2500 5319 5320 #define ADDR_STAMON_NBIT (1 << 10) /* STA monitor bit in AMT_INFO_BLK entity */ 5321 5322 #ifdef WLP2P_UCODE 5323 5324 /** The number of scheduling blocks */ 5325 #ifdef BCMFUZZ /* need more for fuzzing */ 5326 #define M_P2P_BSS_MAX 8 5327 #else 5328 #define M_P2P_BSS_MAX 4 5329 #endif /* BCMFUZZ */ 5330 5331 /** WiFi P2P interrupt block positions */ 5332 #define M_P2P_I_BLK_SZ 4 5333 #define M_P2P_I_BLK_OFFSET(x) (M_P2P_INTR_BLK(x) - M_P2P_INTF_BLK(x)) 5334 #define M_P2P_I_BLK(x, b) (M_P2P_I_BLK_OFFSET(x) + (M_P2P_I_BLK_SZ * (b) * 2)) 5335 #define M_P2P_I(x, b, i) (M_P2P_I_BLK(x, b) + ((i) * 2)) 5336 5337 #define M_P2P_I_PRE_TBTT 0 /**< pretbtt, wake up just before beacon reception */ 5338 #define M_P2P_I_CTW_END 1 /**< CTWindow ends */ 5339 #define M_P2P_I_ABS 2 /**< absence period start, trigger for switching channels */ 5340 #define M_P2P_I_PRS 3 /**< presence period starts */ 5341 5342 /** P2P hps flags */ 5343 #define M_P2P_HPS_CTW(b) (1 << (b)) 5344 #define M_P2P_HPS_NOA(b) (1 << ((b) + M_P2P_BSS_MAX)) 5345 5346 /** WiFi P2P address attribute block */ 5347 #define M_ADDR_BMP_BLK_SZ 12 5348 #define M_ADDR_RANDMAC_BMP_BLK_SZ 40u 5349 5350 #define M_ADDR_BMP_BLK(x, b) (M_ADDR_BMP_BLK_OFFSET(x) + ((b) * 2)) 5351 5352 #define ADDR_BMP_RA (1 << 0) /**< Receiver Address (RA) */ 5353 #define ADDR_BMP_TA (1 << 1) /**< Transmitter Address (TA) */ 5354 #define ADDR_BMP_BSSID (1 << 2) /**< BSSID */ 5355 #define ADDR_BMP_AP (1 << 3) /**< Infra-BSS Access Point (AP) */ 5356 #define ADDR_BMP_STA (1 << 4) /**< Infra-BSS Station (STA) */ 5357 #define ADDR_BMP_P2P_DISC (1 << 5) /**< P2P Device */ 5358 #define ADDR_BMP_P2P_GO (1 << 6) /**< P2P Group Owner */ 5359 #define ADDR_BMP_P2P_GC (1 << 7) /**< P2P Client */ 5360 #define ADDR_BMP_BSS_IDX_MASK (3 << 8) /**< BSS control block index */ 5361 #define ADDR_BMP_BSS_IDX_SHIFT 8 5362 5363 /** WiFi P2P address starts from this entry in RCMTA */ 5364 #define P2P_ADDR_STRT_INDX (RCMTA_SIZE - M_ADDR_BMP_BLK_SZ) 5365 5366 /* WiFi P2P per BSS control block positions. 5367 * all time related fields are in units of (1<<P2P_UCODE_TIME_SHIFT)us unless noted otherwise. 5368 */ 5369 5370 #define P2P_UCODE_TIME_SHIFT 7 5371 #define M_P2P_BSS_BLK_SZ 12 5372 #define M_P2P_BSS_BLK_OFFSET(x) (M_P2P_PERBSS_BLK(x) - M_P2P_INTF_BLK(x)) 5373 #define M_P2P_BSS_BLK(x, b) (M_P2P_BSS_BLK_OFFSET(x) + (M_P2P_BSS_BLK_SZ * (b) * 2)) 5374 #define M_P2P_BSS(x, b, p) (M_P2P_BSS_BLK(x, b) + (p) * 2) 5375 #define M_P2P_BSS_BCN_INT(x, b) (M_P2P_BSS_BLK(x, b) + (0 * 2)) /**< beacon interval */ 5376 #define M_P2P_BSS_DTIM_PRD(x, b) (M_P2P_BSS_BLK(x, b) + (1 * 2)) /**< DTIM period */ 5377 #define M_P2P_BSS_ST(x, b) (M_P2P_BSS_BLK(x, b) + (2 * 2)) /**< current state */ 5378 #define M_P2P_BSS_N_PRE_TBTT(x, b) (M_P2P_BSS_BLK(x, b) + (3 * 2)) /**< next pretbtt time */ 5379 #define M_P2P_BSS_CTW(x, b) (M_P2P_BSS_BLK(x, b) + (4 * 2)) /**< CTWindow duration */ 5380 #define M_P2P_BSS_N_CTW_END(x, b) (M_P2P_BSS_BLK(x, b) + (5 * 2)) /**< next CTWindow end */ 5381 #define M_P2P_BSS_NOA_CNT(x, b) (M_P2P_BSS_BLK(x, b) + (6 * 2)) /**< NoA count */ 5382 #define M_P2P_BSS_N_NOA(x, b) (M_P2P_BSS_BLK(x, b) + (7 * 2)) /**< next absence time */ 5383 #define M_P2P_BSS_NOA_DUR(x, b) (M_P2P_BSS_BLK(x, b) + (8 * 2)) /**< absence period */ 5384 #define M_P2P_BSS_NOA_TD(x, b) (M_P2P_BSS_BLK(x, b) + (9 * 2)) 5385 /**< presence period (int - dur) */ 5386 #define M_P2P_BSS_NOA_OFS(x, b) (M_P2P_BSS_BLK(x, b) + (10 * 2)) 5387 /* last 7 bits of interval in us */ 5388 #define M_P2P_BSS_DTIM_CNT(x, b) (M_P2P_BSS_BLK(x, b) + (11 * 2)) 5389 /**< DTIM count */ 5390 5391 /* M_P2P_BSS_ST word positions. */ 5392 #define M_P2P_BSS_ST_CTW (1 << 0) /**< BSS is in CTWindow */ 5393 #define M_P2P_BSS_ST_SUPR (1 << 1) /**< BSS is suppressing frames */ 5394 #define M_P2P_BSS_ST_ABS (1 << 2) /**< BSS is in absence period */ 5395 #define M_P2P_BSS_ST_WAKE (1 << 3) 5396 #define M_P2P_BSS_ST_AP (1 << 4) /**< BSS is Infra-BSS AP */ 5397 #define M_P2P_BSS_ST_STA (1 << 5) /**< BSS is Infra-BSS STA */ 5398 #define M_P2P_BSS_ST_GO (1 << 6) /**< BSS is P2P Group Owner */ 5399 #define M_P2P_BSS_ST_GC (1 << 7) /**< BSS is P2P Client */ 5400 #define M_P2P_BSS_ST_IBSS (1 << 8) /**< BSS is an IBSS */ 5401 #define M_P2P_BSS_ST_AWDL (1 << 9) /* BSS is AWDL */ 5402 #define M_P2P_BSS_ST_NAN (1 << 10) /**< BSS is NAN */ 5403 #define M_P2P_BSS_ST_MULTIDTIM (1 << 11) /* BSS is Muti-DTIM enabled */ 5404 5405 /** WiFi P2P TSF block positions */ 5406 #define M_P2P_TSF_BLK_SZ 4 5407 #define M_P2P_TSF_BLK_OFFSET(x) (M_P2P_TSF_OFFSET_BLK(x) - M_P2P_INTF_BLK(x)) 5408 #define M_P2P_TSF_BLK(x, b) (M_P2P_TSF_BLK_OFFSET(x) + (M_P2P_TSF_BLK_SZ * (b) * 2)) 5409 #define M_P2P_TSF(x, b, w) (M_P2P_TSF_BLK(x, b) + (w) * 2) 5410 5411 #define M_P2P_TSF_DRIFT_OFFSET(x) (M_P2P_TSF_DRIFT_WD0(x) - M_P2P_INTF_BLK(x)) 5412 #define M_P2P_TSF_DRIFT(x, w) (M_P2P_TSF_DRIFT_OFFSET(x) + (w) * 2) 5413 5414 #define M_P2P_GO_CHANNEL_OFFSET(x) (M_P2P_GO_CHANNEL(x) - M_P2P_INTF_BLK(x)) 5415 #define M_P2P_GO_IND_BMP_OFFSET(x) (M_P2P_GO_IND_BMP(x) - M_P2P_INTF_BLK(x)) 5416 5417 /** 5418 * M_P2P_GO_IND_BMP now has multiple fields: 5419 * 7:0 - GO_IND_BMP 5420 * 10:8 - BSS Index 5421 * 15:11 - Reserved 5422 */ 5423 #define M_P2P_GO_IND_BMP_MASK (0xFF) 5424 #define M_P2P_BSS_INDEX_MASK (0x700) 5425 #define M_P2P_BSS_INDEX_SHIFT_BITS (8) 5426 5427 /* per BSS PreTBTT */ 5428 /* BOM 768.0 and above */ 5429 #define M_P2P_PRE_TBTT_OFFSET(x) (M_P2P_PRETBTT_BLK(x) - M_P2P_INTF_BLK(x)) 5430 #define M_P2P_PRE_TBTT(x, b) (M_P2P_PRE_TBTT_OFFSET(x) + ((b) * 2)) /**< in us */ 5431 5432 /* Reserve bottom of RCMTA for P2P Addresses */ 5433 #define WSEC_MAX_RCMTA_KEYS (54 - M_ADDR_BMP_BLK_SZ) 5434 #else 5435 #define WSEC_MAX_RCMTA_KEYS 54 5436 #endif /* WLP2P_UCODE */ 5437 5438 #define TXCOREMASK 0x0F 5439 #define SPATIAL_SHIFT 8 5440 #define MAX_COREMASK_BLK 5 5441 #define COREMASK_BLK_TRIG_FRAMES (MAX_COREMASK_BLK + 1) 5442 5443 #define BPHY_ONE_CORE_TX (1 << 15) /**< enable TX ant diversity for 11b frames */ 5444 5445 #define M_WLCX_CONFIG_EN(x) 0x1 /**< 1: enable wifi coex */ 5446 #define M_WLCX_CONFIG_MASTER(x) 0x2 /**< 1: Coex Master(5357) */ 5447 5448 /* ucode debug status codes */ 5449 #define DBGST_INACTIVE 0 /**< not valid really */ 5450 #define DBGST_INIT 1 /**< after zeroing SHM, before suspending at init */ 5451 #define DBGST_ACTIVE 2 /**< "normal" state */ 5452 #define DBGST_SUSPENDED 3 /**< suspended */ 5453 #define DBGST_ASLEEP 4 /**< asleep (PS mode) */ 5454 #define DBGST_SLP2WAKE 7 /* On wake up path. */ 5455 5456 /** 5457 * Defines for Self Mac address (used currently for CTS2SELF frames 5458 * generated by BTCX ucode for protection purposes) in SHM. GE40 only. 5459 */ 5460 #define M_MYMAC_ADDR_L(x) (M_MYMAC_ADDR(x)) 5461 #define M_MYMAC_ADDR_M(x) (M_MYMAC_ADDR(x) + (1*2)) 5462 #define M_MYMAC_ADDR_H(x) (M_MYMAC_ADDR(x) + (2*2)) 5463 5464 /* Re-uses M_SSID */ 5465 #define SHM_MBSS_BCNLEN0(x) M_SSID(x) 5466 5467 #define SHM_MBSS_CLOSED_NET(x) (0x80) /**< indicates closed network */ 5468 5469 /** SSID Search Engine entries */ 5470 #define SHM_MBSS_SSIDSE_BASE_ADDR(x) (0) 5471 #define SHM_MBSS_SSIDSE_BLKSZ(x) (36) 5472 #define SHM_MBSS_SSIDLEN_BLKSZ (4) 5473 #define SHM_MBSS_SSID_BLKSZ (32) 5474 5475 /* END New for ucode template based mbss */ 5476 5477 /** Definitions for PRQ fifo data */ 5478 5479 #define SHM_MBSS_PRQ_ENTRY_BYTES 10 /**< Size of each PRQ entry */ 5480 #define SHM_MBSS_PRQ_ENTRY_COUNT 12 /**< Number of PRQ entries */ 5481 #define SHM_MBSS_PRQ_TOT_BYTES (SHM_MBSS_PRQ_ENTRY_BYTES * SHM_MBSS_PRQ_ENTRY_COUNT) 5482 5483 #define M_WOWL_NOBCN (0x06c * 2) /**< loss of bcn value */ 5484 5485 #define M_KEK(x) M_EAPOLMICKEY_BLK(x) + (0x10 * 2) /* < KEK for WEP/TKIP */ 5486 5487 #define M_ARPRESP_BYTESZ_OFFSET 0 /**< 2 bytes; ARP resp pkt size */ 5488 #define M_NA_BYTESZ_0_OFFSET 2 /**< 2 bytes ; NA pkt size */ 5489 #define M_NA_BYTESZ_1_OFFSET 4 /**< 2 bytes ; NA pkt size */ 5490 #define M_KEEPALIVE_BYTESZ_0_OFFSET 6 /**< 2 bytes; size of first keepalive */ 5491 #define M_KEEPALIVE_BYTESZ_1_OFFSET 8 /**< 2 bytes; size of second keepalive */ 5492 #define M_NPAT_ARPIDX_OFFSET 10 /**< 2 bytes; net pattern index of ARP */ 5493 #define M_NPAT_NS0IDX_OFFSET 12 /**< 2 bytes; net pattern index of NS 0 */ 5494 #define M_NPAT_NS1IDX_OFFSET 14 /**< 2 bytes; net pattern index of NS 1 */ 5495 #define M_EXTWAKEPATTERN_0_OFFSET 16 /**< 6 bytes; ext magic pattern */ 5496 #define M_EXTWAKEPATTERN_U0_OFFSET 22 /**< 8 bytes; unaligned ext magic pattern */ 5497 #define M_KEEPALIVE_INTVL_0_OFFSET 30 /**< 2 bytes; in no of beacon intervals */ 5498 #define M_KEEPALIVE_INTVL_1_OFFSET 32 /**< 2 bytes; in no of beacon intervals */ 5499 5500 #define M_COREMASK_BLK_WOWL_L30 (0x298 * 2) 5501 5502 /* corerev > 29 && corerev < 40 */ 5503 #define M_COREMASK_BLK_WOWL (0x7e8 *2) 5504 5505 /* corerev >= 42 */ 5506 #define D11AC_M_COREMASK_BLK_WOWL (0x1b0*2) 5507 5508 #define M_EXTLNA_PWRSAVE(x) M_RADIO_PWR(x) /**< External LNA power control support */ 5509 5510 /* D11AC shm location changes */ 5511 #define D11AC_T_NULL_TPL_BASE (0x16 * 2) 5512 #define D11AC_T_NULL_TPL_SIZE_BYTES (24) 5513 #define D11_T_BCN0_TPL_BASE T_BCN0_TPL_BASE 5514 #define D11AC_T_BCN0_TPL_BASE (0x100 * 2) 5515 #define D11_T_BCN1_TPL_BASE T_BCN1_TPL_BASE 5516 #define D11AC_T_BCN1_TPL_BASE (0x240 * 2) 5517 #define D11AC_T_GACT_TWT_INFO_TPL_BASE (0xB0 * 2) 5518 #define D11AC_T_GACT_TWT_INFO_TPL_SIZE_BYTES (36) 5519 5520 /* The response (ACK/BA) phyctrl words */ 5521 #define D11AC_RSP_TXPCTL0 (0x4c * 2) 5522 #define D11AC_RSP_TXPCTL1 (0x4d * 2) 5523 5524 #define D11AC_T_PRS_TPL_BASE (0x380 * 2) 5525 5526 #define D11_M_RT_PRS_PLCP_POS(x) M_RT_PRS_PLCP_POS(x) 5527 #define D11_M_RT_PRS_DUR_POS(x) M_RT_PRS_DUR_POS(x) 5528 #define D11AC_M_RT_PRS_PLCP_POS 8 5529 #define D11AC_M_RT_PRS_DUR_POS 12 5530 5531 /* Field definitions for M_REV40_RT_TXPWROFF_POS */ 5532 #define M_REV40_RT_HTTXPWR_OFFSET_MASK 0x01f8 /**< bit 8:3 */ 5533 #define M_REV40_RT_HTTXPWR_OFFSET_SHIFT 3 5534 5535 /* for axphy */ 5536 #define M_REV80_RT_TXPWR_OFFSET_MASK 0xff00 /* bit 15:8 */ 5537 #define M_REV80_RT_TXPWR_OFFSET_SHIFT 9 /* 8 (byte align) + 1 (convert from S5.1 to S5.2) */ 5538 5539 /* shmem locations for Beamforming */ 5540 /* shmem defined with prefix M_ are in shmem */ 5541 #define shm_addr(base, offset) (((base)+(offset))*2) 5542 5543 #define C_BFI_REFRESH_THR_OFFSET (1u) 5544 #define C_BFI_NDPA_TXLMT_OFFSET (2u) 5545 #define C_BFI_NRXC_OFFSET (3u) 5546 #define C_BFI_MLBF_LUT_OFFSET (4u) // for corerev < 64 only 5547 5548 #define C_BFI_BLK_SIZE(corerev) ((D11REV_GE(corerev, 86) ? 18u: 16u)) 5549 5550 /* BFI block definitions (Beamforming) */ 5551 #define C_BFI_BFRIDX_POS (0) 5552 #define C_BFI_NDPA_TST_POS (1) 5553 #define C_BFI_NDPA_TXCNT_POS (2) 5554 #define C_BFI_NDPA_SEQ_POS (3) 5555 #define C_BFI_NDPA_FCTST_POS (4) 5556 #define C_BFI_BFRCTL_POS (5) 5557 #define C_BFI_BFR_CONFIG0_POS (6) 5558 #define C_BFI_BFE_CONFIG0_POS (7) 5559 #define C_BFI_BFE_MIMOCTL_POS (8) 5560 #define C_BFI_BSSID0_POS (9) 5561 #define C_BFI_BSSID1_POS (10) 5562 #define C_BFI_BSSID2_POS (11) 5563 #define C_BFI_STAINFO_POS (12) 5564 #define C_BFI_STAINFO1_POS (13) 5565 #define C_BFI_BFE_MYAID_POS (13) /* stainfo1 is mutually exclusive */ 5566 #define C_BFI_BFMSTAT_POS (14) 5567 #define C_BFI_BFE_MIMOCTL_EXT_POS (15) 5568 /* below SHMs for rev >= 86 */ 5569 #define C_BFI_BFE_11AXMIMOCTL_POS (16) /* phyreg bfeMimoCtlReg for 11AX */ 5570 #define C_BFI_BFE_NDPNR_POS (17) 5571 /* used by BFR */ 5572 #define C_BFI_STA_ADDR_POS C_BFI_BSSID0_POS 5573 5574 /* to be removed -start */ 5575 #define M_BFI_BLK_SIZE (16u) 5576 #define BFI_BLK_SIZE 18 5577 /* to be removed -end */ 5578 5579 /* Phy cache index Bit<8> indicates the validity. Cleared during TxBf link Init 5580 * to trigger a new sounding sequence. 5581 */ 5582 #define C_BFRIDX_VLD_NBIT 8 /* valid */ 5583 #define C_BFRIDX_EN_NBIT 7 /* BFI block is enabled (has valid info), 5584 * applicable only for MU BFI block in shmemx 5585 */ 5586 #define C_BFRIDX_BW_NBIT 12 5587 5588 #define C_STAINFO_FBT_NBIT 12 /* 0: SU; 1: MU */ 5589 #define C_STAINFO_NCIDX_NBIT 13 /* Bits13-15: NC IDX; Reserved if Feedback Type is SU */ 5590 5591 /* NDP control blk */ 5592 #define C_BFI_BFRCTL_POS_NDP_TYPE_SHIFT (0) /* 0: HT NDP; 1: VHT NDP; HE no need */ 5593 #define C_BFI_BFRCTL_POS_NSTS_SHIFT (1) /* 0: 2ss; 1: 3ss; 2: 4ss */ 5594 #define C_BFI_BFRCTL_POS_MLBF_SHIFT (4) /* 1 enable MLBF(used for corerev < 64) */ 5595 #define C_BFI_BFRCTL_POS_BFM_SHIFT (8) /* Bits15-8: BFM mask for BFM frame tx */ 5596 5597 /** dynamic rflo ucode WAR defines */ 5598 #define UCODE_WAR_EN 1 5599 #define UCODE_WAR_DIS 0 5600 5601 /** LTE coex definitions */ 5602 #define LTECX_FLAGS_LPBK_OFF 0 5603 5604 /** LTECX shares BTCX shmem block */ 5605 #define M_LTECX_BLK_PTR(x) M_BTCX_BLK_PTR(x) 5606 5607 /** NR5GCX shares BTCX shmem block */ 5608 #define M_NR5GCX_BLK_PTR(x) M_BTCX_BLK_PTR(x) 5609 5610 /** RC1CX shares BTCX shmem block */ 5611 #define M_RC1CX_BLK_PTR(x) M_BTCX_BLK_PTR(x) 5612 5613 /** RC2CX shares BTCX shmem block */ 5614 #define M_RC2CX_BLK_PTR(x) M_BTCX_BLK_PTR(x) 5615 5616 /* CORE0 MODE */ 5617 #define CORE0_MODE_RSDB 0x0 5618 #define CORE0_MODE_MIMO 0x1 5619 #define CORE0_MODE_80P80 0x2 5620 5621 #define CORE1_MODE_RSDB 0x100 5622 5623 #define HWACI_HOST_FLAG_ADDR (0x186) 5624 #define HWACI_SET_SW_MITIGATION_MODE (0x0008) 5625 5626 /* split RX war shm locations */ 5627 #define RXFIFO_0_OFFSET 0x1A0 5628 #define RXFIFO_1_OFFSET 0x19E 5629 #define HDRCONV_FIFO0_STSLEN 0x4 /* status length in header conversion mode */ 5630 5631 /* GE80: 5632 * [15:8]: Phy status length 5633 * [7:0]: Ucode status length 5634 */ 5635 #define DEFAULT_FIFO0_STSLEN(corerev, corerev_minor) \ 5636 (D11REV_MAJ_MIN_GE(corerev, corerev_minor, 87, 1) ? 0x2018 : \ 5637 D11REV_GE(corerev, 80) ? 0x2010: 0x24) 5638 5639 /* M_ULP_WAKEIND bits */ 5640 #define C_WATCHDOG_EXPIRY (1 << 0) 5641 #define C_FCBS_ERROR (1 << 1) 5642 #define C_RETX_FAILURE (1 << 2) 5643 #define C_HOST_WAKEUP (1 << 3) 5644 #define C_INVALID_FCBS_BLOCK (1 << 4) 5645 #define C_HUDI_DS1_EXIT (1 << 5) 5646 #define C_LOB_SLEEP (1 << 6) 5647 5648 /* values for M_ULP_FEATURES */ 5649 #define C_P2P_NOA (0x0001) 5650 #define C_INFINITE_NOA (0x0002) 5651 #define C_P2P_CTWIN (0x0004) 5652 #define C_P2P_GC (0x0008) 5653 #define C_BCN_TRIM (0x0010) 5654 #define C_BT_COEX (0x0020) 5655 #define C_LTE_COEX (0x0040) 5656 #define C_ADS1 (0x0080) 5657 #define C_LTECX_PSPOLL_PRIO_EN (0x0100) 5658 #define C_ULP_SLOWCAL_SKIP (0x0200) 5659 #define C_HUDI_ENABLE (0x0400) 5660 5661 #define M_WOWL_ULP_SW_DAT_BLK (0xBFF * 2) /* (0xFFF * 2) - 1024 */ 5662 #define M_WOWL_ULP_SW_DAT_BLK_MAX_SZ (0x400) /* 1024 bytes */ 5663 5664 #define RX_INTR_FIFO_0 0x1 /* FIFO-0 interrupt */ 5665 #define RX_INTR_FIFO_1 0x2 /* FIFO-1 interrupt */ 5666 #define RX_INTR_FIFO_2 0x4 /* FIFO-2 interrupt */ 5667 5668 /* M_TOF_FLAG bits */ 5669 typedef enum { 5670 TOF_RX_FTM_NBIT = 0, 5671 TOF_SEQ_DISRXENTX_RFCTL = 1, 5672 TOF_IS_TARGET = 2, 5673 TOF_TPC_FREEZE = 3 5674 } eTOFFlags; 5675 5676 /* TOF feature flags */ 5677 #define M_UCODE_F2_TOF_BIT 7 /* part of features_2 shm */ 5678 #define M_UCODE_F3_AVB_BIT 2 /* part of features_3 shm */ 5679 #define M_UCODE_F3_SEQ_BIT 3 /* part of features_3 shm */ 5680 5681 /* New SHM definitions required for tsync based time stamping of FTM frames. 5682 * More details in below conf 5683 * http://confluence.broadcom.com/display/WLAN/NewUcodeInterfaceForProxdFeature 5684 */ 5685 #define FTM_TIMESTAMP_SHIFT 16 5686 #define TXS_ACK_INDEX_SHIFT 3 5687 #define FTM_ACK_TS_BLOCK_SIZE 3 5688 #define RXH_ACK_SHIFT(corerev) (D11REV_GE((corerev), 80) ? 12u:8u) 5689 #define FTM_INVALID_SHM_INDEX(corerev) (D11REV_GE((corerev), 80) ? 0x04u:0x0Fu) 5690 #define FTM_ACK_INDEX_MASK 0x0F 5691 #define NUM_UCODE_ACK_TS_BLKS 4 5692 5693 #define FTM_TXSTATUS_ACK_RSPEC_BLOCK_MASK 0xFF 5694 #define FTM_TXSTATUS_ACK_RSPEC_BW_MASK 0x3 5695 #define FTM_TXSTATUS_ACK_RSPEC_BW_SHIFT 2 5696 #define FTM_TXSTATUS_ACK_RSPEC_BW_20 0 5697 #define FTM_TXSTATUS_ACK_RSPEC_BW_40 1 5698 #define FTM_TXSTATUS_ACK_RSPEC_BW_80 2 5699 #define FTM_TXSTATUS_ACK_RSPEC_BW_160 3 5700 #define FTM_TXSTATUS_ACK_RSPEC_TYPE_SHIFT 4 5701 #define FTM_TXSTATUS_ACK_RSPEC_TYPE_MASK 0x7 5702 #define FTM_TXSTATUS_ACK_RSPEC_TYPE_CCK 0 5703 #define FTM_TXSTATUS_ACK_RSPEC_TYPE_LEG 1 /* Legacy */ 5704 #define FTM_TXSTATUS_ACK_RSPEC_TYPE_HT 2 5705 #define FTM_TXSTATUS_ACK_RSPEC_TYPE_VHT 3 5706 #define FTM_TXSTATUS_ACK_RSPEC_TYPE_HE 4 5707 #define FTM_TXSTATUS_ACK_RSPEC_RATE_6M(ackword) (ackword >> 7) 5708 /* Following are the offsets in M_DRVR_UCODE_IF_PTR block. Start address of 5709 * M_DRVR_UCODE_IF_PTR block is present in M_DRVR_UCODE_IF_PTR. 5710 */ 5711 #define M_ULP_FEATURES (0x0 * 2) 5712 5713 /* M_HOST_FLAGS5 offset changed in ULP ucode */ 5714 #define M_ULP_HOST_FLAGS5 (0x3d * 2) 5715 5716 #define M_RADAR_REG_TMP (0x033 * 2) 5717 5718 /* Bit masks for ClkGateUcodeReq2: Ucode MAC Clock Request2 (IHR Address 0x375) register */ 5719 #define D11_FUNC16_MAC_CLOCKREQ_MASK (0x3) 5720 5721 /* 5722 * Clock gating registers 5723 */ 5724 #define CLKREQ_BLOCK 0 5725 #define CLKREQ_MAC_ILP 1 5726 #define CLKREQ_MAC_ALP 2 5727 #define CLKREQ_MAC_HT 3 5728 5729 /* ClkGateSts */ 5730 #define CLKGTE_FORCE_MAC_CLK_REQ_SHIFT 0 5731 #define CLKGTE_MAC_PHY_CLK_REQ_SHIFT 4 5732 5733 /* ClkGateReqCtrl0 */ 5734 #define CLKGTE_PSM_PATCHCOPY_CLK_REQ_SHIFT 0 5735 #define CLKGTE_RXKEEP_OCP_CLK_REQ_SHIFT 2 5736 #define CLKGTE_PSM_MAC_CLK_REQ_SHIFT 4 5737 #define CLKGTE_TSF_CLK_REQ_SHIFT 6 5738 #define CLKGTE_AQM_CLK_REQ_SHIFT 8 5739 #define CLKGTE_SERIAL_CLK_REQ_SHIFT 10 5740 #define CLKGTE_TX_CLK_REQ_SHIFT 12 5741 #define CLKGTE_POSTTX_CLK_REQ_SHIFT 14 5742 5743 /* ClkGateReqCtrl1 */ 5744 #define CLKGTE_RX_CLK_REQ_SHIFT 0 5745 #define CLKGTE_TXKEEP_OCP_CLK_REQ_SHIFT 2 5746 #define CLKGTE_HOST_RW_CLK_REQ_SHIFT 4 5747 #define CLKGTE_IHR_WR_CLK_REQ_SHIFT 6 5748 #define CLKGTE_TKIP_KEY_CLK_REQ_SHIFT 8 5749 #define CLKGTE_TKIP_MISC_CLK_REQ_SHIFT 10 5750 #define CLKGTE_AES_CLK_REQ_SHIFT 12 5751 #define CLKGTE_WAPI_CLK_REQ_SHIFT 14 5752 5753 /* ClkGateReqCtrl2 */ 5754 #define CLKGTE_WEP_CLK_REQ_SHIFT 0 5755 #define CLKGTE_PSM_CLK_REQ_SHIFT 2 5756 #define CLKGTE_MACPHY_CLK_REQ_BY_PHY_SHIFT 4 5757 #define CLKGTE_FCBS_CLK_REQ_SHIFT 6 5758 #define CLKGTE_HIN_AXI_MAC_CLK_REQ_SHIFT 8 5759 5760 /* ClkGateStretch0 */ 5761 #define CLKGTE_MAC_HT_CLOCK_STRETCH_SHIFT 0 5762 #define CLKGTE_MAC_ALP_CLOCK_STRETCH_SHIFT 8 5763 #define CLKGTE_MAC_HT_CLOCK_STRETCH_VAL 0x4 5764 5765 /* ClkGateStretch1 */ 5766 #define CLKGTE_MAC_PHY_CLOCK_STRETCH_SHIFT 13 5767 5768 /* ClkGateMisc */ 5769 #define CLKGTE_TPF_CLK_REQTHRESH 0xF 5770 #define CLKGTE_AQM_CLK_REQEXT 0x70 5771 5772 /* ClkGateDivCtrl */ 5773 #define CLKGTE_MAC_ILP_OFF_COUNT_MASK 0x0007 5774 #define CLKGTE_MAC_ILP_OFF_COUNT_SHIFT 0 5775 #define CLKGTE_MAC_ILP_ON_COUNT_MASK 0x0020 5776 #define CLKGTE_MAC_ILP_ON_COUNT_MASK_GE_REV80 0x0030 5777 #define CLKGTE_MAC_ALP_OFF_COUNT_MASK 0x03C0 5778 #define CLKGTE_MAC_ALP_OFF_COUNT_SHIFT 6 5779 5780 /* ClkGatePhyClkCtrl */ 5781 #define CLKGTE_PHY_MAC_PHY_CLK_REQ_EN_SHIFT 0 5782 #define CLKGTE_O2C_HIN_PHY_CLK_EN_SHIFT 1 5783 #define CLKGTE_HIN_PHY_CLK_EN_SHIFT 2 5784 #define CLKGTE_IHRP_PHY_CLK_EN_SHIFT 3 5785 #define CLKGTE_CCA_MAC_PHY_CLK_REQ_EN_SHIFT 4 5786 #define CLKGTE_TX_MAC_PHY_CLK_REQ_EN_SHIFT 5 5787 #define CLKGTE_HRP_MAC_PHY_CLK_REQ_EN_SHIFT 6 5788 #define CLKGTE_SYNC_MAC_PHY_CLK_REQ_EN_SHIFT 7 5789 #define CLKGTE_RX_FRAME_MAC_PHY_CLK_REQ_EN_SHIFT 8 5790 #define CLKGTE_RX_START_MAC_PHY_CLK_REQ_EN_SHIFT 9 5791 #define CLKGTE_FCBS_MAC_PHY_CLK_REQ_SHIFT 10 5792 #define CLKGTE_POSTRX_MAC_PHY_CLK_REQ_EN_SHIFT 11 5793 #define CLKGTE_DOT11_MAC_PHY_RXVALID_SHIFT 12 5794 #define CLKGTE_NOT_PHY_FIFO_EMPTY_SHIFT 13 5795 #define CLKGTE_DOT11_MAC_PHY_BFE_REPORT_DATA_READY 14 5796 #define CLKGTE_DOT11_MAC_PHY_CLK_BIT15 15 5797 5798 /* ClkGateExtReq0 */ 5799 #define CLKGTE_TOE_SYNC_MAC_CLK_REQ_SHIFT 0 5800 #define CLKGTE_TXBF_SYNC_MAC_CLK_REQ_SHIFT 2 5801 #define CLKGTE_HIN_SYNC_MAC_CLK_REQ_SHIFT 4 5802 #define CLKGTE_SLOW_SYNC_CLK_REQ_SHIFT 6 5803 #define CLKGTE_ERCX_SYNC_CLK_REQ_SHIFT 8 5804 #define CLKGTE_BTCX_SYNC_CLK_REQ_SHIFT 10 5805 #define CLKGTE_IFS_CRS_SYNC_CLK_REQ_SHIFT 12 5806 #define CLKGTE_IFS_GCI_SYNC_CLK_REQ_SHIFT 14 5807 5808 #define CLKGTE_TOE_SYNC_MAC_CLK_REQ_80_SHIFT 2 5809 #define CLKGTE_TXBF_SYNC_MAC_CLK_REQ_80_SHIFT 4 5810 #define CLKGTE_HIN_SYNC_MAC_CLK_REQ_80_SHIFT 6 5811 #define CLKGTE_SLOW_SYNC_CLK_REQ_80_SHIFT 8 5812 #define CLKGTE_ERCX_SYNC_CLK_REQ_80_SHIFT 10 5813 #define CLKGTE_BTCX_SYNC_CLK_REQ_80_SHIFT 12 5814 #define CLKGTE_IFS_CRS_SYNC_CLK_REQ_80_SHIFT 14 5815 5816 #define CLKGTE_TOE_SYNC_MAC_CLK_REQ_83_SHIFT 2 5817 #define CLKGTE_TXBF_SYNC_MAC_CLK_REQ_83_SHIFT 4 5818 #define CLKGTE_HIN_SYNC_MAC_CLK_REQ_83_SHIFT 6 5819 #define CLKGTE_SLOW_SYNC_CLK_REQ_83_SHIFT 8 5820 #define CLKGTE_ERCX_SYNC_CLK_REQ_83_SHIFT 10 5821 #define CLKGTE_BTCX2_SYNC_CLK_REQ_83_SHIFT 12 5822 #define CLKGTE_BTCX_SYNC_CLK_REQ_83_SHIFT 14 5823 5824 /* ClkGateExtReq1 */ 5825 #define CLKGTE_PHY_FIFO_SYNC_CLK_REQ_SHIFT 0 5826 #define CLKGTE_RXE_CHAN_SYNC_CLK_REQ_SHIFT 2 5827 #define CLKGTE_PMU_MDIS_SYNC_MAC_CLK_REQ_SHIFT 4 5828 #define CLKGTE_PSM_IPC_SYNC_CLK_REQ_SHIFT 6 5829 5830 #define CLKGTE_IFS_GCI_SYNC_CLK_REQ_80_SHIFT 0 5831 #define CLKGTE_PHY_FIFO_SYNC_CLK_REQ_80_SHIFT 2 5832 #define CLKGTE_RXE_CHAN_SYNC_CLK_REQ_80_SHIFT 4 5833 #define CLKGTE_PMU_MDIS_SYNC_MAC_CLK_REQ_80_SHIFT 6 5834 #define CLKGTE_PSM_IPC_SYNC_CLK_REQ_80_SHIFT 8 5835 5836 #define CLKGTE_IFS_CRS_SYNC_CLK_REQ_83_SHIFT 0 5837 #define CLKGTE_IFS_GCI_SYNC_CLK_REQ_83_SHIFT 2 5838 #define CLKGTE_PHY_FIFO_SYNC_CLK_REQ_83_SHIFT 4 5839 #define CLKGTE_RXE_CHAN_SYNC_CLK_REQ_83_SHIFT 6 5840 #define CLKGTE_PMU_MDIS_SYNC_MAC_CLK_REQ_83_SHIFT 8 5841 #define CLKGTE_PSM_IPC_SYNC_CLK_REQ_83_SHIFT 10 5842 5843 /* PFE CtlStat1 register */ 5844 #define PFE_CTLSTAT1_ROUTE_PFE_TO_BMSTAT (1u << 15u) 5845 #define PFE_CTLSTAT1_PFE_ENABLE (1u << 0u) 5846 5847 /* PPR Ctrl1 register */ 5848 #define PPR_CTMODE_SHIFT 8u 5849 #define PPR_CTMODE_MASK (3u << PPR_CTMODE_SHIFT) 5850 5851 #define PPR_CTMODE_A (0u << PPR_CTMODE_SHIFT) 5852 #define PPR_CTMODE_B (1u << PPR_CTMODE_SHIFT) 5853 #define PPR_CTMODE_C (2u << PPR_CTMODE_SHIFT) 5854 5855 /* Ptxd Len */ 5856 #define PTXD_LEN0_SHIFT (0u) 5857 #define PTXD_LEN1_SHIFT (8u) 5858 #define PTXD_LEN2_SHIFT (0u) 5859 #define PTXD_LEN3_SHIFT (8u) 5860 /* =========== LHL regs =========== */ 5861 /* WL ARM Timer0 Interrupt Status (lhl_wl_armtim0_st_adr) */ 5862 #define LHL_WL_ARMTIM0_ST_WL_ARMTIM_INT_ST 0x00000001 5863 5864 #define D11_AUTO_MEM_STBY_RET_SHIFT (4u) 5865 #define D11_AUTO_MEM_STBY_RET_83_SHIFT (5u) 5866 #define D11_AUTO_MEM_STBY_NON_RET_SHIFT (6u) 5867 #define D11_AUTO_MEM_STBY_BM_SHIFT (9u) 5868 5869 #define D11_AUTO_MEM_STBY_RET_SHIFT_REV(d11rev) \ 5870 (((d11rev) >= 83) ? D11_AUTO_MEM_STBY_RET_83_SHIFT : D11_AUTO_MEM_STBY_RET_SHIFT) 5871 5872 /* WiFi P2P TX stop timestamp block (only applicable with AC ucode) */ 5873 #define P2P_TXSTOP_SHMPERBSS 2u /* 2 shmems per BSS */ 5874 #define M_P2P_TXSTOP_TS(x, b, w) (M_P2P_TXSTOP_T_BLK(x) +\ 5875 (P2P_TXSTOP_SHMPERBSS * (b) + (w)) * 2) 5876 5877 #define D11TXHDR_RATEINFO_ACCESS_VAL(txh, corerev, member) \ 5878 ((((txh)->corerev).RateInfo[3]).member) 5879 5880 /* QoS + BSR information */ 5881 #define D11_QOS_BSR_TIDQS_SHIFT 0u 5882 #define D11_QOS_BSR_TIDQS_SZ 8u 5883 #define D11_QOS_BSR_TIDQS_MASK (((1 << D11_QOS_BSR_TIDQS_SZ) - 1) << D11_QOS_BSR_TIDQS_SHIFT) 5884 5885 #define D11_QOS_BSR_UV_SHIFT 8u 5886 #define D11_QOS_BSR_UV_SZ 6u 5887 #define D11_QOS_BSR_UV_MASK (((1 << D11_QOS_BSR_UV_SZ) - 1) << D11_QOS_BSR_UV_SHIFT) 5888 5889 #define D11_QOS_BSR_SF_SHIFT 14u 5890 #define D11_QOS_BSR_SF_SZ 2u 5891 #define D11_QOS_BSR_SF_MASK (((1 << D11_QOS_BSR_SF_SZ) - 1) << D11_QOS_BSR_SF_SHIFT) 5892 5893 /* Queue size in QoS control */ 5894 #define D11_QOS_BSR_SF_0 0u 5895 #define D11_QOS_BSR_SF_1 1u 5896 #define D11_QOS_BSR_SF_2 2u 5897 #define D11_QOS_BSR_SF_3 3u 5898 5899 #define D11_QS_OFFSET_SF_0 0u 5900 #define D11_QS_OFFSET_SF_1 1024u 5901 #define D11_QS_OFFSET_SF_2 17408u 5902 #define D11_QS_OFFSET_SF_3 148480u 5903 5904 #define D11_QOS_BSR_SF_0_SHIFT 4u /* Scale: 16 bytes */ 5905 #define D11_QOS_BSR_SF_1_SHIFT 8u /* Scale: 256 bytes */ 5906 #define D11_QOS_BSR_SF_2_SHIFT 11u /* Scale: 2048 bytes */ 5907 #define D11_QOS_BSR_SF_3_SHIFT 15u /* Scale: 32768 bytes */ 5908 5909 #define D11_MIN_QS_UV 0u 5910 #define D11_MAX_QS_UV 63u 5911 #define D11_MAX_QS_UV_SF3 ((D11_MAX_QS_UV) - 1) 5912 5913 /* 1008: 16 * UV when the Scaling Factor subfield is 0 */ 5914 #define D11_MAX_QS_SF_0 (D11_QS_OFFSET_SF_0 + (D11_MAX_QS_UV << D11_QOS_BSR_SF_0_SHIFT)) 5915 /* 17152: 1024 + 256 * UV when the Scaling Factor subfield is 1 */ 5916 #define D11_MAX_QS_SF_1 (D11_QS_OFFSET_SF_1 + (D11_MAX_QS_UV << D11_QOS_BSR_SF_1_SHIFT)) 5917 /* 146432: 17408 + 2048 * UV when the Scaling Factor subfield is 2 */ 5918 #define D11_MAX_QS_SF_2 (D11_QS_OFFSET_SF_2 + (D11_MAX_QS_UV << D11_QOS_BSR_SF_2_SHIFT)) 5919 /* 2147328: 148480 + 32768 * UV when the Scaling Factor subfield is 3 */ 5920 #define D11_MAX_QS_SF_3 (D11_QS_OFFSET_SF_3 + ((D11_MAX_QS_UV_SF3-1) << D11_QOS_BSR_SF_3_SHIFT)) 5921 5922 /* 2 bits for HE signature and 4 bits for control ID */ 5923 #define D11_BSR_HE_SIG_SHIFT 6u 5924 /* HE Variant with BSR control ID */ 5925 #define D11_BSR_HE_SIG (0xf) 5926 #define D11_BSR_ACI_BMAP_SHIFT (0 + D11_BSR_HE_SIG_SHIFT) 5927 #define D11_BSR_DELTA_TID_SHIFT (4 + D11_BSR_HE_SIG_SHIFT) 5928 #define D11_BSR_SF_SHIFT (8 + D11_BSR_HE_SIG_SHIFT) 5929 #define D11_BSR_QUEUE_SIZE_HIGH_SHIFT (10 + D11_BSR_HE_SIG_SHIFT) 5930 #define D11_BSR_QUEUE_SIZE_ALL_SHIFT (18 + D11_BSR_HE_SIG_SHIFT) 5931 5932 #define D11_BSR_DELTA_TID_ALLTID_SIGNATURE 3u 5933 5934 #define D11_BSR_QUEUE_SIZE_WIDTH 8u 5935 #define D11_BSR_QUEUE_SIZE_WIDTH_VAL ((1 << D11_BSR_QUEUE_SIZE_WIDTH) - 1) 5936 #define D11_BSR_QUEUE_SIZE_UNKNOWN (255u) 5937 #define D11_BSR_QUEUE_SIZE_MAX (254u) 5938 #define D11_BSR_QUEUE_SIZE_HIGH_MASK (D11_BSR_QUEUE_SIZE_WIDTH_VAL <<\ 5939 D11_BSR_QUEUE_SIZE_HIGH_SHIFT) 5940 #define D11_BSR_QUEUE_SIZE_ALL_MASK (D11_BSR_QUEUE_SIZE_WIDTH_VAL <<\ 5941 D11_BSR_QUEUE_SIZE_ALL_SHIFT) 5942 5943 #define D11_BSR_WD1_SHIFT 16u 5944 5945 enum { 5946 D11_BSR_SF_ID_16 = 0, /* 0 */ 5947 D11_BSR_SF_ID_256 = 1, /* 1 */ 5948 D11_BSR_SF_ID_2048 = 2, /* 2 */ 5949 D11_BSR_SF_ID_32768 = 3 /* 3 */ 5950 }; 5951 5952 enum { 5953 D11_PING_BLOCK_VALID = 0, /* 0 */ 5954 D11_PONG_BLOCK_VALID = 1, /* 1 */ 5955 D11_UC_READING_PING_BLOCK = 2, /* 2 */ 5956 D11_UC_READING_PONG_BLOCK = 3 /* 3 */ 5957 }; 5958 5959 enum { 5960 D11_BSR_TID0_POS = 0, /* 0 */ 5961 D11_BSR_TID1_POS = 1, /* 1 */ 5962 D11_BSR_TID2_POS = 2, /* 2 */ 5963 D11_BSR_TID3_POS = 3, /* 3 */ 5964 D11_BSR_TID4_POS = 4, /* 4 */ 5965 D11_BSR_TID5_POS = 5, /* 5 */ 5966 D11_BSR_TID6_POS = 6, /* 6 */ 5967 D11_BSR_TID7_POS = 7, /* 7 */ 5968 D11_BSR_WD0_POS = 8, /* 8 */ 5969 D11_BSR_WD1_POS = 9, /* 9 */ 5970 }; 5971 5972 #define D11_IS_PING_PONG_IN_RESET(i) (((i) & ((1 << D11_PING_BLOCK_VALID) |\ 5973 (1 << D11_UC_READING_PING_BLOCK) | (1 << D11_PONG_BLOCK_VALID) |\ 5974 (1 << D11_UC_READING_PONG_BLOCK))) == 0) 5975 #define D11_PING_BLOCK_VALID_MASK ((1 << D11_PONG_BLOCK_VALID) |\ 5976 (1 << D11_UC_READING_PING_BLOCK)) 5977 #define D11_PONG_BLOCK_VALID_MASK ((1 << D11_PING_BLOCK_VALID) |\ 5978 (1 << D11_UC_READING_PONG_BLOCK)) 5979 #define D11_PING_PONG_UPDATE_MASK ((1 << D11_PING_BLOCK_VALID) |\ 5980 (1 << D11_PONG_BLOCK_VALID)) 5981 #define D11_IS_PING_BLOCK_WRITABLE(i) (((i) & D11_PING_BLOCK_VALID_MASK) == \ 5982 (1 << D11_PONG_BLOCK_VALID)) 5983 #define D11_IS_PONG_BLOCK_WRITABLE(i) (((i) & D11_PONG_BLOCK_VALID_MASK) == \ 5984 (1 << D11_PING_BLOCK_VALID)) 5985 #define D11_SET_PING_BLOCK_VALID(i) (((i) & ~(1 << D11_PONG_BLOCK_VALID)) |\ 5986 (1 << D11_PING_BLOCK_VALID)) 5987 #define D11_SET_PONG_BLOCK_VALID(i) (((i) & ~(1 << D11_PING_BLOCK_VALID)) |\ 5988 (1 << D11_PONG_BLOCK_VALID)) 5989 #define D11_SET_PING_PONG_INVALID(i) (((i) & ~(1 << D11_PING_BLOCK_VALID)) |\ 5990 ((i) & ~(1 << D11_PONG_BLOCK_VALID))) 5991 5992 /* valid rx plcp check */ 5993 #define PLCP_VALID(plcp) (((plcp)[0] | (plcp)[1] | (plcp)[2]) != 0) 5994 enum { 5995 D11_TXTRIG_EN = 0, /* 0 */ 5996 D11_TXTRIG_PROG = 1, /* 1 */ 5997 D11_TXTRIG_DONE = 2, /* 2 */ 5998 D11_TXTRIG_TYPE = 4, /* 4 */ 5999 }; 6000 6001 #define D11_SET_TXTRIG_EN (1 << D11_TXTRIG_EN) 6002 #define D11_TXTRIG_TYPE_MASK ((1 << D11_TXTRIG_TYPE) | (1 << (D11_TXTRIG_TYPE+1))) 6003 #define D11_SET_TXTRIG_TYPE(i) (((i) << D11_TXTRIG_TYPE) & D11_TXTRIG_TYPE_MASK) 6004 6005 enum { 6006 D11_MUEDCA_AIFSN = 0, /* 0 */ 6007 D11_MUEDCA_CWMIN = 1, /* 1 */ 6008 D11_MUEDCA_CWMAX = 2, /* 2 */ 6009 D11_MUEDCA_TIMER = 3, /* 3 */ 6010 D11_MUEDCA_SU_AIFSN = 4, /* 4 */ 6011 D11_MUEDCA_SU_CWMIN = 5, /* 5 */ 6012 D11_MUEDCA_SU_CWMAX = 6, /* 6 */ 6013 D11_MUEDCA_EXPIRY_TSF = 7, /* 7 */ 6014 D11_MUEDCA_QINFO = 8, /* 8 */ 6015 D11_MUEDCA_STAT = 9, /* 9 */ 6016 D11_MUEDCA_BLK_SIZE = 10 /* 10 */ 6017 }; 6018 #define D11_MUEDCA_BLK(x, idx, offset) (M_MUEDCA_BLK((x)) +\ 6019 (idx * (D11_MUEDCA_BLK_SIZE << 1)) + (offset << 1)) 6020 6021 #define D11_BSSCOLOR_VALID_SHIFT 15u 6022 #define D11_BSSCOLOR_VALID_MASK (1 << D11_BSSCOLOR_VALID_SHIFT) 6023 6024 #ifdef BCMPCIE_HP2P 6025 /* HP2P (High Priority P2P) shared memory EDCA parameters */ 6026 typedef struct shm_hp2p_edca_params { 6027 uint16 txop; 6028 uint16 cwmin; 6029 uint16 cwmax; 6030 uint16 cwcur; 6031 uint16 aifs; 6032 uint16 bslots; 6033 uint16 reggap; 6034 uint16 status; 6035 } shm_hp2p_edca_params_t; 6036 6037 #define HP2P_STATUS_NEWPARAMS (1u << 8u) 6038 #endif /* BCMPCIE_HP2P */ 6039 6040 #define MAX_D11_GPIOS 16 6041 6042 /* Workaround register */ 6043 #define WAR_TXDMA_NONMODIFIABLE_EN 0x00000010 /* For TxDMA initiated AXI reads */ 6044 #define WAR_AQMDMA_NONMODIFIABLE_EN 0x00000020 /* For AQMDMA initiated AXI reads */ 6045 6046 /* noise cal timeout when NAN is enabled. 6047 * 54 * 256 = ~14ms . 6048 * smallest NAN CRB possible is 16ms..choose 14ms 6049 * as timeout to ensure noise cal happens within this 16ms 6050 */ 6051 #define M_NOISE_CALTIMEOUT_FOR_NAN 54u 6052 6053 #define TXPU_CMD_SET 1u /**< txpu set command */ 6054 6055 #endif /* _D11_H */ 6056