xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/ti,cal.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/media/ti,cal.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Texas Instruments DRA72x CAMERA ADAPTATION LAYER (CAL) Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Benoit Parrot <bparrot@ti.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |-
13*4882a593Smuzhiyun  The Camera Adaptation Layer (CAL) is a key component for image capture
14*4882a593Smuzhiyun  applications. The capture module provides the system interface and the
15*4882a593Smuzhiyun  processing capability to connect CSI2 image-sensor modules to the
16*4882a593Smuzhiyun  DRA72x device.
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun  CAL supports 2 camera port nodes on MIPI bus. Each CSI2 camera port nodes
19*4882a593Smuzhiyun  should contain a 'port' child node with child 'endpoint' node. Please
20*4882a593Smuzhiyun  refer to the bindings defined in
21*4882a593Smuzhiyun  Documentation/devicetree/bindings/media/video-interfaces.txt.
22*4882a593Smuzhiyun
23*4882a593Smuzhiyunproperties:
24*4882a593Smuzhiyun  compatible:
25*4882a593Smuzhiyun    enum:
26*4882a593Smuzhiyun      # for DRA72 controllers
27*4882a593Smuzhiyun      - ti,dra72-cal
28*4882a593Smuzhiyun      # for DRA72 controllers pre ES2.0
29*4882a593Smuzhiyun      - ti,dra72-pre-es2-cal
30*4882a593Smuzhiyun      # for DRA76 controllers
31*4882a593Smuzhiyun      - ti,dra76-cal
32*4882a593Smuzhiyun      # for AM654 controllers
33*4882a593Smuzhiyun      - ti,am654-cal
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun  reg:
36*4882a593Smuzhiyun    minItems: 2
37*4882a593Smuzhiyun    items:
38*4882a593Smuzhiyun      - description: The CAL main register region
39*4882a593Smuzhiyun      - description: The RX Core0 (DPHY0) register region
40*4882a593Smuzhiyun      - description: The RX Core1 (DPHY1) register region
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun  reg-names:
43*4882a593Smuzhiyun    minItems: 2
44*4882a593Smuzhiyun    items:
45*4882a593Smuzhiyun      - const: cal_top
46*4882a593Smuzhiyun      - const: cal_rx_core0
47*4882a593Smuzhiyun      - const: cal_rx_core1
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun  interrupts:
50*4882a593Smuzhiyun    maxItems: 1
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun  ti,camerrx-control:
53*4882a593Smuzhiyun    $ref: "/schemas/types.yaml#/definitions/phandle-array"
54*4882a593Smuzhiyun    description:
55*4882a593Smuzhiyun      phandle to the device control module and offset to the
56*4882a593Smuzhiyun      control_camerarx_core register
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun  clocks:
59*4882a593Smuzhiyun    maxItems: 1
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun  clock-names:
62*4882a593Smuzhiyun    const: fck
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun  power-domains:
65*4882a593Smuzhiyun    description:
66*4882a593Smuzhiyun      List of phandle and PM domain specifier as documented in
67*4882a593Smuzhiyun      Documentation/devicetree/bindings/power/power_domain.txt
68*4882a593Smuzhiyun    maxItems: 1
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun  # See ./video-interfaces.txt for details
71*4882a593Smuzhiyun  ports:
72*4882a593Smuzhiyun    type: object
73*4882a593Smuzhiyun    additionalProperties: false
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun    properties:
76*4882a593Smuzhiyun      "#address-cells":
77*4882a593Smuzhiyun        const: 1
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun      "#size-cells":
80*4882a593Smuzhiyun        const: 0
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun      port@0:
83*4882a593Smuzhiyun        type: object
84*4882a593Smuzhiyun        additionalProperties: false
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun        properties:
87*4882a593Smuzhiyun          reg:
88*4882a593Smuzhiyun            const: 0
89*4882a593Smuzhiyun            description: CSI2 Port #0
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun        patternProperties:
92*4882a593Smuzhiyun          endpoint:
93*4882a593Smuzhiyun            type: object
94*4882a593Smuzhiyun            additionalProperties: false
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun            properties:
97*4882a593Smuzhiyun              clock-lanes:
98*4882a593Smuzhiyun                maxItems: 1
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun              data-lanes:
101*4882a593Smuzhiyun                minItems: 1
102*4882a593Smuzhiyun                maxItems: 4
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun              remote-endpoint: true
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun        required:
107*4882a593Smuzhiyun          - reg
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun      port@1:
110*4882a593Smuzhiyun        type: object
111*4882a593Smuzhiyun        additionalProperties: false
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun        properties:
114*4882a593Smuzhiyun          reg:
115*4882a593Smuzhiyun            const: 1
116*4882a593Smuzhiyun            description: CSI2 Port #1
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun        patternProperties:
119*4882a593Smuzhiyun          endpoint:
120*4882a593Smuzhiyun            type: object
121*4882a593Smuzhiyun            additionalProperties: false
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun            properties:
124*4882a593Smuzhiyun              clock-lanes:
125*4882a593Smuzhiyun                maxItems: 1
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun              data-lanes:
128*4882a593Smuzhiyun                minItems: 1
129*4882a593Smuzhiyun                maxItems: 4
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun              remote-endpoint: true
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun        required:
134*4882a593Smuzhiyun          - reg
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun    required:
137*4882a593Smuzhiyun      - "#address-cells"
138*4882a593Smuzhiyun      - "#size-cells"
139*4882a593Smuzhiyun      - port@0
140*4882a593Smuzhiyun
141*4882a593Smuzhiyunrequired:
142*4882a593Smuzhiyun  - compatible
143*4882a593Smuzhiyun  - reg
144*4882a593Smuzhiyun  - reg-names
145*4882a593Smuzhiyun  - interrupts
146*4882a593Smuzhiyun  - ti,camerrx-control
147*4882a593Smuzhiyun
148*4882a593SmuzhiyunadditionalProperties: false
149*4882a593Smuzhiyun
150*4882a593Smuzhiyunexamples:
151*4882a593Smuzhiyun  - |
152*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun    cal: cal@4845b000 {
155*4882a593Smuzhiyun        compatible = "ti,dra72-cal";
156*4882a593Smuzhiyun        reg = <0x4845B000 0x400>,
157*4882a593Smuzhiyun              <0x4845B800 0x40>,
158*4882a593Smuzhiyun              <0x4845B900 0x40>;
159*4882a593Smuzhiyun        reg-names = "cal_top",
160*4882a593Smuzhiyun                    "cal_rx_core0",
161*4882a593Smuzhiyun                    "cal_rx_core1";
162*4882a593Smuzhiyun        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
163*4882a593Smuzhiyun        ti,camerrx-control = <&scm_conf 0xE94>;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun        ports {
166*4882a593Smuzhiyun              #address-cells = <1>;
167*4882a593Smuzhiyun              #size-cells = <0>;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun              csi2_0: port@0 {
170*4882a593Smuzhiyun                    reg = <0>;
171*4882a593Smuzhiyun                    csi2_phy0: endpoint {
172*4882a593Smuzhiyun                           remote-endpoint = <&csi2_cam0>;
173*4882a593Smuzhiyun                           clock-lanes = <0>;
174*4882a593Smuzhiyun                           data-lanes = <1 2>;
175*4882a593Smuzhiyun                    };
176*4882a593Smuzhiyun              };
177*4882a593Smuzhiyun        };
178*4882a593Smuzhiyun    };
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun    i2c {
181*4882a593Smuzhiyun        clock-frequency = <400000>;
182*4882a593Smuzhiyun        #address-cells = <1>;
183*4882a593Smuzhiyun        #size-cells = <0>;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun        camera-sensor@3c {
186*4882a593Smuzhiyun               compatible = "ovti,ov5640";
187*4882a593Smuzhiyun               reg = <0x3c>;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun               clocks = <&clk_ov5640_fixed>;
190*4882a593Smuzhiyun               clock-names = "xclk";
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun               port {
193*4882a593Smuzhiyun                    csi2_cam0: endpoint {
194*4882a593Smuzhiyun                            remote-endpoint = <&csi2_phy0>;
195*4882a593Smuzhiyun                            clock-lanes = <0>;
196*4882a593Smuzhiyun                            data-lanes = <1 2>;
197*4882a593Smuzhiyun                    };
198*4882a593Smuzhiyun               };
199*4882a593Smuzhiyun        };
200*4882a593Smuzhiyun    };
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun...
203