Searched +full:tx +full:- +full:level +full:- +full:trig (Results 1 – 25 of 69) sorted by relevance
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1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/spi/spi-pl022.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Linus Walleij <linus.walleij@linaro.org>13 - $ref: "spi-controller.yaml#"22 - compatible27 - const: arm,pl02228 - const: arm,primecell39 clock-names:[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later8 /dts-v1/;13 compatible = "st,spear1310-evb", "st,spear1310";14 #address-cells = <1>;15 #size-cells = <1>;23 pinctrl-names = "default";24 pinctrl-0 = <&state_default>;63 smi-pmx {127 label = "u-boot";149 compatible = "gpio-keys";[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later8 /dts-v1/;13 compatible = "st,spear1340-evb", "st,spear1340";14 #address-cells = <1>;15 #size-cells = <1>;23 pinctrl-names = "default";24 pinctrl-0 = <&state_default>;47 spdif-in {51 spdif-out {59 smi-pmx {[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later3 * PHYTEC phyCORE-LPC3250 board5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>9 /dts-v1/;13 model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";22 compatible = "gpio-leds";26 default-state = "off";31 linux,default-trigger = "heartbeat";37 power-supply = <®_lcd>;41 remote-endpoint = <&cldc_output>;[all …]
33 /dts-v1/;39 compatible = "brcm,ns2-svk", "brcm,ns2";49 stdout-path = "serial0:115200n8";113 spi-max-frequency = <5000000>;114 spi-cpha;115 spi-cpol;118 pl022,slave-tx-disable = <0>;119 pl022,com-mode = <0>;120 pl022,rx-level-trig = <1>;121 pl022,tx-level-trig = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.08 /dts-v1/;10 /include/ "amd-seattle-soc.dtsi"14 compatible = "amd,seattle-overdrive", "amd,seattle";17 stdout-path = &serial0;48 compatible = "mmc-spi-slot";50 spi-max-frequency = <20000000>;51 voltage-ranges = <3200 3400>;53 interrupt-parent = <&gpio0>;57 pl022,com-mode = <0x0>;[all …]
1 // SPDX-License-Identifier: GPL-2.04 * Note: Based-on AMD Seattle Rev.B09 /dts-v1/;11 /include/ "amd-seattle-soc.dtsi"15 compatible = "amd,seattle-overdrive", "amd,seattle";18 stdout-path = &serial0;22 compatible = "arm,psci-0.2";29 amd,zlib-support = <1>;70 compatible = "mmc-spi-slot";72 spi-max-frequency = <20000000>;[all …]
1 // SPDX-License-Identifier: GPL-2.09 /dts-v1/;11 /include/ "amd-seattle-soc.dtsi"15 compatible = "amd,seattle-overdrive", "amd,seattle";18 stdout-path = &serial0;22 compatible = "arm,psci-0.2";29 amd,zlib-support = <1>;70 compatible = "mmc-spi-slot";72 spi-max-frequency = <20000000>;73 voltage-ranges = <3200 3400>;[all …]
1 // SPDX-License-Identifier: GPL-2.09 /dts-v1/;11 /include/ "amd-seattle-soc.dtsi"15 compatible = "amd,seattle-overdrive", "amd,seattle";18 stdout-path = &serial0;22 compatible = "arm,psci-0.2";29 amd,zlib-support = <1>;74 compatible = "mmc-spi-slot";76 spi-max-frequency = <20000000>;77 voltage-ranges = <3200 3400>;[all …]
1 // SPDX-License-Identifier: GPL-2.0-only27 * vuart - An inter-partition data link service.31 * The vuart provides a bi-directional byte stream data link between logical63 * struct ps3_vuart_port_priv - private vuart device data.86 BUG_ON(!dev->driver_priv); in to_port_priv()87 return (struct ps3_vuart_port_priv *)dev->driver_priv; in to_port_priv()91 * struct ports_bmp - bitmap indicating ports needing service.106 pr_debug("%s:%d: ports_bmp: %016llxh\n", func, line, bmp->status); in _dump_ports_bmp()143 struct vuart_triggers *trig) in ps3_vuart_get_triggers() argument148 u64 tx; in ps3_vuart_get_triggers() local[all …]
9 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-649730 * Copyright(c) 2012 - 2014, 2018 - 2020 Intel Corporation65 * AUX indices follows - 1 for non-CDB, 2 for CDB.85 * enum iwl_mac_protection_flags - MAC context flags104 * enum iwl_mac_types - Supported MAC types108 * @FW_MAC_TYPE_PIBSS: Pseudo-IBSS132 * enum iwl_tsf_id - TSF hw timer ID148 * struct iwl_mac_data_ap - configuration data for AP MAC context171 * struct iwl_mac_data_ibss - configuration data for IBSS MAC context[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * Copyright 2003-2005 Devicescape Software, Inc.6 * Copyright 2013-2014 Intel Mobile Communications GmbH8 * Copyright (C) 2018 - 2020 Intel Corporation17 #include "driver-ops.h"26 struct sta_info *sta = file->private_data; \28 format_string, sta->field); \89 char *end = buf + sizeof(buf) - 1; in sta_flags_read()90 struct sta_info *sta = file->private_data; in sta_flags_read()97 pos += scnprintf(pos, end - pos, "%s\n", in sta_flags_read()[all …]
1 // SPDX-License-Identifier: GPL-2.0-or-later5 * Copyright (C) 2008-2012 ST-Ericsson AB11 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c31 #include <linux/dma-mapping.h>93 * SSP Control Register 0 - SSP_CR0111 * SSP Control Register 0 - SSP_CR1131 * SSP Status Register - SSP_SR140 * SSP Clock Prescale Register - SSP_CPSR145 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC153 * SSP Raw Interrupt Status Register - SSP_RIS[all …]
3 * Copyright (C) 2012-2015 ROCKCHIP.4 * Author: luowei <lw@rock-chips.com>33 #include <linux/sensor-dev.h>74 /*! \name AK8975 fuse-rom address76 Defines a read-only address of the fuse ROM of the AK8975.*/121 //sensor->ops->ctrl_data = sensor_read_reg(client, sensor->ops->ctrl_reg); in sensor_active()126 sensor->ops->ctrl_data = AK8975_MODE_SNG_MEASURE; in sensor_active()130 sensor->ops->ctrl_data = AK8975_MODE_POWERDOWN; in sensor_active()133 …DBG("%s:reg=0x%x,reg_ctrl=0x%x,enable=%d\n",__func__,sensor->ops->ctrl_reg, sensor->ops->ctrl_data… in sensor_active()134 result = sensor_write_reg(client, sensor->ops->ctrl_reg, sensor->ops->ctrl_data); in sensor_active()[all …]
... d dbm, %d mW Override is %s -o -d -q -m Error: Missing ...
1 // SPDX-License-Identifier: GPL-2.0+6 * COMEDI - Linux Control and Measurement Device Interface13 * Devices: [Real Time Devices] DM7520HR-1 (DM7520), DM7520HR-8,14 * PCI4520 (PCI4520), PCI4520-816 * Status: Works. Only tested on DM7520-8. Not SMP safe.24 * The PCI4520 is a PCI card. The DM7520 is a PC/104-plus card.40 * These boards can support external multiplexors and multi-board46 * Call them and ask for the register level manual.71 * Analog-In supports instruction and command mode.73 * With DMA, you can sample at 1.15Mhz with 70% idle on a 400Mhz K6-2[all …]
3 * Copyright(c) 2019 - 2021 Realtek Corporation.28 return mac->hw_info->macid_num; in hal_mac_get_macid_num()33 struct mac_ax_hw_info *mac_info = mac->hw_info; in hal_mac_get_hwinfo()34 struct mac_ax_ops *ops = mac->ops; in hal_mac_get_hwinfo()37 mac_info = ops->get_hw_info(mac); in hal_mac_get_hwinfo()39 hal_spec->macid_num = mac_info->macid_num; in hal_mac_get_hwinfo()41 hal->hal_com->cv = mac_info->cv; in hal_mac_get_hwinfo()42 PHL_INFO("[MAC-INFO]- CV : %d\n", mac_info->cv); in hal_mac_get_hwinfo()43 PHL_INFO("[MAC-INFO]- tx_ch_num: %d\n", mac_info->tx_ch_num); in hal_mac_get_hwinfo()45 PHL_INFO("[MAC-INFO]- tx_data_ch_num: %d\n", mac_info->tx_data_ch_num); in hal_mac_get_hwinfo()[all …]
2 * Chip-specific hardware definitions for14 * <<Broadcom-WL-IPTag/Proprietary:>>68 /* TX FIFO numbers using WME Access Classes */69 #define TX_AC_BK_FIFO 0 /**< Access Category Background TX FIFO */70 #define TX_AC_BE_FIFO 1 /**< Access Category Best-Effort TX FIFO */71 #define TX_AC_VI_FIFO 2 /**< Access Class Video TX FIFO */72 #define TX_AC_VO_FIFO 3 /**< Access Class Voice TX FIFO */73 #define TX_BCMC_FIFO 4 /**< Broadcast/Multicast TX FIFO */74 #define TX_ATIM_FIFO 5 /**< TX fifo for ATIM window info */77 /* TX FIFO numbers for trigger queues for HE STA only chips (i.e[all …]
3 * Copyright (c) 2007-2013 Broadcom Corporation13 * R - Read only14 * RC - Clear on read15 * RW - Read/Write16 * ST - Statistics register (clear on read)17 * W - Write only18 * WB - Wide bus register - the size is over 32 bits and it should be20 * WR - Write Clear (write 1 to clear the bit)32 /* [RW 1] Initiate the ATC array - reset all the valid bits */56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -[all …]
... 502 [QUEUE_MANAGER] %p failed to set non-blocking mode on pipe descriptors mali-cinstr-timer
30 /*--------------------Define -------------------------------------------*/33 hal_sdio_cmd52_r8(adapter->drv_adapter, addr)35 hal_sdio_cmd53_r8(adapter->drv_adapter, addr)37 hal_sdio_cmd53_r16(adapter->drv_adapter, addr)39 hal_sdio_cmd53_r32(adapter->drv_adapter, addr)41 hal_sdio_cmd53_rn(adapter->drv_adapter, addr, size, val)43 hal_sdio_cmd52_w8(adapter->drv_adapter, addr, val)45 hal_sdio_cmd53_w8(adapter->drv_adapter, addr, val)47 hal_sdio_cmd53_wn(adapter->drv_adapter, addr, size, val)49 hal_sdio_cmd53_w16(adapter->drv_adapter, addr, val)[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * This is the new netlink-based wireless configuration interface.5 * Copyright 2006-2010 Johannes Berg <johannes@sipsolutions.net>6 * Copyright 2013-2014 Intel Mobile Communications GmbH7 * Copyright 2015-2017 Intel Deutschland GmbH8 * Copyright (C) 2018-2021 Intel Corporation32 #include "rdev-ops.h"50 NL80211_MCGRP_TESTMODE /* keep last - ifdef! */74 int wiphy_idx = -1; in __cfg80211_wdev_from_attrs()75 int ifidx = -1; in __cfg80211_wdev_from_attrs()[all …]