1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * DTS file for AMD Seattle Overdrive Development Board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Advanced Micro Devices, Inc. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun/dts-v1/; 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun/include/ "amd-seattle-soc.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "AMD Seattle Development Board (Overdrive)"; 14*4882a593Smuzhiyun compatible = "amd,seattle-overdrive", "amd,seattle"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun chosen { 17*4882a593Smuzhiyun stdout-path = &serial0; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun}; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun&ccp0 { 22*4882a593Smuzhiyun status = "ok"; 23*4882a593Smuzhiyun}; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun&gpio0 { 26*4882a593Smuzhiyun status = "ok"; 27*4882a593Smuzhiyun}; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun&gpio1 { 30*4882a593Smuzhiyun status = "ok"; 31*4882a593Smuzhiyun}; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun&i2c0 { 34*4882a593Smuzhiyun status = "ok"; 35*4882a593Smuzhiyun}; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun&pcie0 { 38*4882a593Smuzhiyun status = "ok"; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun&spi0 { 42*4882a593Smuzhiyun status = "ok"; 43*4882a593Smuzhiyun}; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun&spi1 { 46*4882a593Smuzhiyun status = "ok"; 47*4882a593Smuzhiyun sdcard0: sdcard@0 { 48*4882a593Smuzhiyun compatible = "mmc-spi-slot"; 49*4882a593Smuzhiyun reg = <0>; 50*4882a593Smuzhiyun spi-max-frequency = <20000000>; 51*4882a593Smuzhiyun voltage-ranges = <3200 3400>; 52*4882a593Smuzhiyun gpios = <&gpio0 7 0>; 53*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 54*4882a593Smuzhiyun interrupts = <7 3>; 55*4882a593Smuzhiyun pl022,hierarchy = <0>; 56*4882a593Smuzhiyun pl022,interface = <0>; 57*4882a593Smuzhiyun pl022,com-mode = <0x0>; 58*4882a593Smuzhiyun pl022,rx-level-trig = <0>; 59*4882a593Smuzhiyun pl022,tx-level-trig = <0>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun}; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun&v2m0 { 64*4882a593Smuzhiyun arm,msi-base-spi = <64>; 65*4882a593Smuzhiyun arm,msi-num-spis = <256>; 66*4882a593Smuzhiyun}; 67