1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * PHYTEC phyCORE-LPC3250 board 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com> 6*4882a593Smuzhiyun * Copyright 2012 Roland Stigge <stigge@antcom.de> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/dts-v1/; 10*4882a593Smuzhiyun#include "lpc32xx.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250"; 14*4882a593Smuzhiyun compatible = "phytec,phy3250", "nxp,lpc3250"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun memory@80000000 { 17*4882a593Smuzhiyun device_type = "memory"; 18*4882a593Smuzhiyun reg = <0x80000000 0x4000000>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun leds { 22*4882a593Smuzhiyun compatible = "gpio-leds"; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun led0 { /* red */ 25*4882a593Smuzhiyun gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */ 26*4882a593Smuzhiyun default-state = "off"; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun led1 { /* green */ 30*4882a593Smuzhiyun gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */ 31*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun panel: panel { 36*4882a593Smuzhiyun compatible = "sharp,lq035q7db03"; 37*4882a593Smuzhiyun power-supply = <®_lcd>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun port { 40*4882a593Smuzhiyun panel_input: endpoint { 41*4882a593Smuzhiyun remote-endpoint = <&cldc_output>; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun reg_backlight: regulator-backlight { 47*4882a593Smuzhiyun compatible = "regulator-fixed"; 48*4882a593Smuzhiyun regulator-name = "backlight"; 49*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 50*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 51*4882a593Smuzhiyun gpio = <&gpio 5 4 0>; 52*4882a593Smuzhiyun enable-active-high; 53*4882a593Smuzhiyun regulator-boot-on; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun reg_lcd: regulator-lcd { 57*4882a593Smuzhiyun compatible = "regulator-fixed"; 58*4882a593Smuzhiyun regulator-name = "lcd"; 59*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 60*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 61*4882a593Smuzhiyun gpio = <&gpio 5 0 0>; 62*4882a593Smuzhiyun enable-active-high; 63*4882a593Smuzhiyun regulator-boot-on; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun reg_sd: regulator-sd { 67*4882a593Smuzhiyun compatible = "regulator-fixed"; 68*4882a593Smuzhiyun regulator-name = "sd"; 69*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 70*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 71*4882a593Smuzhiyun gpio = <&gpio 5 5 0>; 72*4882a593Smuzhiyun enable-active-high; 73*4882a593Smuzhiyun regulator-boot-on; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun}; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun&clcd { 78*4882a593Smuzhiyun max-memory-bandwidth = <18710000>; 79*4882a593Smuzhiyun status = "okay"; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun port { 82*4882a593Smuzhiyun cldc_output: endpoint { 83*4882a593Smuzhiyun remote-endpoint = <&panel_input>; 84*4882a593Smuzhiyun arm,pl11x,tft-r0g0b0-pads = <0 8 16>; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&i2c1 { 90*4882a593Smuzhiyun clock-frequency = <100000>; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun uda1380: uda1380@18 { 93*4882a593Smuzhiyun compatible = "nxp,uda1380"; 94*4882a593Smuzhiyun reg = <0x18>; 95*4882a593Smuzhiyun power-gpio = <&gpio 3 10 0>; 96*4882a593Smuzhiyun reset-gpio = <&gpio 3 2 0>; 97*4882a593Smuzhiyun dac-clk = "wspll"; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun pcf8563: rtc@51 { 101*4882a593Smuzhiyun compatible = "nxp,pcf8563"; 102*4882a593Smuzhiyun reg = <0x51>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun}; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun&i2c2 { 107*4882a593Smuzhiyun clock-frequency = <100000>; 108*4882a593Smuzhiyun}; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun&i2cusb { 111*4882a593Smuzhiyun clock-frequency = <100000>; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun isp1301: usb-transceiver@2c { 114*4882a593Smuzhiyun compatible = "nxp,isp1301"; 115*4882a593Smuzhiyun reg = <0x2c>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun}; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun&key { 120*4882a593Smuzhiyun keypad,num-rows = <1>; 121*4882a593Smuzhiyun keypad,num-columns = <1>; 122*4882a593Smuzhiyun nxp,debounce-delay-ms = <3>; 123*4882a593Smuzhiyun nxp,scan-delay-ms = <34>; 124*4882a593Smuzhiyun linux,keymap = <0x00000002>; 125*4882a593Smuzhiyun status = "okay"; 126*4882a593Smuzhiyun}; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun&mac { 129*4882a593Smuzhiyun phy-mode = "rmii"; 130*4882a593Smuzhiyun use-iram; 131*4882a593Smuzhiyun status = "okay"; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun/* Here, choose exactly one from: ohci, usbd */ 135*4882a593Smuzhiyun&ohci /* &usbd */ { 136*4882a593Smuzhiyun transceiver = <&isp1301>; 137*4882a593Smuzhiyun status = "okay"; 138*4882a593Smuzhiyun}; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun&sd { 141*4882a593Smuzhiyun wp-gpios = <&gpio 3 0 0>; 142*4882a593Smuzhiyun cd-gpios = <&gpio 3 1 0>; 143*4882a593Smuzhiyun cd-inverted; 144*4882a593Smuzhiyun bus-width = <4>; 145*4882a593Smuzhiyun vmmc-supply = <®_sd>; 146*4882a593Smuzhiyun status = "okay"; 147*4882a593Smuzhiyun}; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun/* 64MB Flash via SLC NAND controller */ 150*4882a593Smuzhiyun&slc { 151*4882a593Smuzhiyun status = "okay"; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun nxp,wdr-clks = <14>; 154*4882a593Smuzhiyun nxp,wwidth = <40000000>; 155*4882a593Smuzhiyun nxp,whold = <100000000>; 156*4882a593Smuzhiyun nxp,wsetup = <100000000>; 157*4882a593Smuzhiyun nxp,rdr-clks = <14>; 158*4882a593Smuzhiyun nxp,rwidth = <40000000>; 159*4882a593Smuzhiyun nxp,rhold = <66666666>; 160*4882a593Smuzhiyun nxp,rsetup = <100000000>; 161*4882a593Smuzhiyun nand-on-flash-bbt; 162*4882a593Smuzhiyun gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */ 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun partitions { 165*4882a593Smuzhiyun compatible = "fixed-partitions"; 166*4882a593Smuzhiyun #address-cells = <1>; 167*4882a593Smuzhiyun #size-cells = <1>; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun mtd0@0 { 170*4882a593Smuzhiyun label = "phy3250-boot"; 171*4882a593Smuzhiyun reg = <0x00000000 0x00064000>; 172*4882a593Smuzhiyun read-only; 173*4882a593Smuzhiyun }; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun mtd1@64000 { 176*4882a593Smuzhiyun label = "phy3250-uboot"; 177*4882a593Smuzhiyun reg = <0x00064000 0x00190000>; 178*4882a593Smuzhiyun read-only; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun mtd2@1f4000 { 182*4882a593Smuzhiyun label = "phy3250-ubt-prms"; 183*4882a593Smuzhiyun reg = <0x001f4000 0x00010000>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun mtd3@204000 { 187*4882a593Smuzhiyun label = "phy3250-kernel"; 188*4882a593Smuzhiyun reg = <0x00204000 0x00400000>; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun mtd4@604000 { 192*4882a593Smuzhiyun label = "phy3250-rootfs"; 193*4882a593Smuzhiyun reg = <0x00604000 0x039fc000>; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun }; 196*4882a593Smuzhiyun}; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun&ssp0 { 199*4882a593Smuzhiyun num-cs = <1>; 200*4882a593Smuzhiyun cs-gpios = <&gpio 3 5 0>; 201*4882a593Smuzhiyun status = "okay"; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun eeprom: at25@0 { 204*4882a593Smuzhiyun compatible = "atmel,at25"; 205*4882a593Smuzhiyun reg = <0>; 206*4882a593Smuzhiyun spi-max-frequency = <5000000>; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun pl022,interface = <0>; 209*4882a593Smuzhiyun pl022,com-mode = <0>; 210*4882a593Smuzhiyun pl022,rx-level-trig = <1>; 211*4882a593Smuzhiyun pl022,tx-level-trig = <1>; 212*4882a593Smuzhiyun pl022,ctrl-len = <11>; 213*4882a593Smuzhiyun pl022,wait-state = <0>; 214*4882a593Smuzhiyun pl022,duplex = <0>; 215*4882a593Smuzhiyun 216*4882a593Smuzhiyun at25,byte-len = <0x8000>; 217*4882a593Smuzhiyun at25,addr-mode = <2>; 218*4882a593Smuzhiyun at25,page-size = <64>; 219*4882a593Smuzhiyun }; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&tsc { 223*4882a593Smuzhiyun status = "okay"; 224*4882a593Smuzhiyun}; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun&uart2 { 227*4882a593Smuzhiyun status = "okay"; 228*4882a593Smuzhiyun}; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun&uart3 { 231*4882a593Smuzhiyun status = "okay"; 232*4882a593Smuzhiyun}; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun&uart5 { 235*4882a593Smuzhiyun status = "okay"; 236*4882a593Smuzhiyun}; 237