1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/spi/spi-pl022.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: ARM PL022 SPI controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Linus Walleij <linus.walleij@linaro.org> 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunallOf: 13*4882a593Smuzhiyun - $ref: "spi-controller.yaml#" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun# We need a select here so we don't match all nodes with 'arm,primecell' 16*4882a593Smuzhiyunselect: 17*4882a593Smuzhiyun properties: 18*4882a593Smuzhiyun compatible: 19*4882a593Smuzhiyun contains: 20*4882a593Smuzhiyun const: arm,pl022 21*4882a593Smuzhiyun required: 22*4882a593Smuzhiyun - compatible 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunproperties: 25*4882a593Smuzhiyun compatible: 26*4882a593Smuzhiyun items: 27*4882a593Smuzhiyun - const: arm,pl022 28*4882a593Smuzhiyun - const: arm,primecell 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun reg: 31*4882a593Smuzhiyun maxItems: 1 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun interrupts: 34*4882a593Smuzhiyun maxItems: 1 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun clocks: 37*4882a593Smuzhiyun maxItems: 2 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clock-names: 40*4882a593Smuzhiyun items: 41*4882a593Smuzhiyun - enum: 42*4882a593Smuzhiyun - SSPCLK 43*4882a593Smuzhiyun - sspclk 44*4882a593Smuzhiyun - const: apb_pclk 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun pl022,autosuspend-delay: 47*4882a593Smuzhiyun description: delay in ms following transfer completion before the 48*4882a593Smuzhiyun runtime power management system suspends the device. A setting of 0 49*4882a593Smuzhiyun indicates no delay and the device will be suspended immediately. 50*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun pl022,rt: 53*4882a593Smuzhiyun description: indicates the controller should run the message pump with realtime 54*4882a593Smuzhiyun priority to minimise the transfer latency on the bus (boolean) 55*4882a593Smuzhiyun type: boolean 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun dmas: 58*4882a593Smuzhiyun description: 59*4882a593Smuzhiyun Two or more DMA channel specifiers following the convention outlined 60*4882a593Smuzhiyun in bindings/dma/dma.txt 61*4882a593Smuzhiyun minItems: 2 62*4882a593Smuzhiyun maxItems: 32 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun dma-names: 65*4882a593Smuzhiyun description: 66*4882a593Smuzhiyun There must be at least one channel named "tx" for transmit and named "rx" 67*4882a593Smuzhiyun for receive. 68*4882a593Smuzhiyun minItems: 2 69*4882a593Smuzhiyun maxItems: 32 70*4882a593Smuzhiyun additionalItems: true 71*4882a593Smuzhiyun items: 72*4882a593Smuzhiyun - const: rx 73*4882a593Smuzhiyun - const: tx 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunpatternProperties: 76*4882a593Smuzhiyun "^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$": 77*4882a593Smuzhiyun type: object 78*4882a593Smuzhiyun # SPI slave nodes must be children of the SPI master node and can 79*4882a593Smuzhiyun # contain the following properties. 80*4882a593Smuzhiyun properties: 81*4882a593Smuzhiyun pl022,interface: 82*4882a593Smuzhiyun description: SPI interface type 83*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 84*4882a593Smuzhiyun enum: 85*4882a593Smuzhiyun - 0 # SPI 86*4882a593Smuzhiyun - 1 # Texas Instruments Synchronous Serial Frame Format 87*4882a593Smuzhiyun - 2 # Microwire (Half Duplex) 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun pl022,com-mode: 90*4882a593Smuzhiyun description: Specifies the transfer mode 91*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 92*4882a593Smuzhiyun enum: 93*4882a593Smuzhiyun - 0 # interrupt mode 94*4882a593Smuzhiyun - 1 # polling mode 95*4882a593Smuzhiyun - 2 # DMA mode 96*4882a593Smuzhiyun default: 1 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun pl022,rx-level-trig: 99*4882a593Smuzhiyun description: Rx FIFO watermark level 100*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 101*4882a593Smuzhiyun minimum: 0 102*4882a593Smuzhiyun maximum: 4 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun pl022,tx-level-trig: 105*4882a593Smuzhiyun description: Tx FIFO watermark level 106*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 107*4882a593Smuzhiyun minimum: 0 108*4882a593Smuzhiyun maximum: 4 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun pl022,ctrl-len: 111*4882a593Smuzhiyun description: Microwire interface - Control length 112*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 113*4882a593Smuzhiyun minimum: 0x03 114*4882a593Smuzhiyun maximum: 0x1f 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun pl022,wait-state: 117*4882a593Smuzhiyun description: Microwire interface - Wait state 118*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 119*4882a593Smuzhiyun enum: [0, 1] 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun pl022,duplex: 122*4882a593Smuzhiyun description: Microwire interface - Full/Half duplex 123*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/uint32" 124*4882a593Smuzhiyun enum: [0, 1] 125*4882a593Smuzhiyun 126*4882a593Smuzhiyunrequired: 127*4882a593Smuzhiyun - compatible 128*4882a593Smuzhiyun - reg 129*4882a593Smuzhiyun - interrupts 130*4882a593Smuzhiyun 131*4882a593SmuzhiyununevaluatedProperties: false 132*4882a593Smuzhiyun 133*4882a593Smuzhiyunexamples: 134*4882a593Smuzhiyun - | 135*4882a593Smuzhiyun spi@e0100000 { 136*4882a593Smuzhiyun compatible = "arm,pl022", "arm,primecell"; 137*4882a593Smuzhiyun reg = <0xe0100000 0x1000>; 138*4882a593Smuzhiyun #address-cells = <1>; 139*4882a593Smuzhiyun #size-cells = <0>; 140*4882a593Smuzhiyun interrupts = <0 31 0x4>; 141*4882a593Smuzhiyun dmas = <&dma_controller 23 1>, 142*4882a593Smuzhiyun <&dma_controller 24 0>; 143*4882a593Smuzhiyun dma-names = "rx", "tx"; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun m25p80@1 { 146*4882a593Smuzhiyun compatible = "st,m25p80"; 147*4882a593Smuzhiyun reg = <1>; 148*4882a593Smuzhiyun spi-max-frequency = <12000000>; 149*4882a593Smuzhiyun spi-cpol; 150*4882a593Smuzhiyun spi-cpha; 151*4882a593Smuzhiyun pl022,interface = <0>; 152*4882a593Smuzhiyun pl022,com-mode = <0x2>; 153*4882a593Smuzhiyun pl022,rx-level-trig = <0>; 154*4882a593Smuzhiyun pl022,tx-level-trig = <0>; 155*4882a593Smuzhiyun pl022,ctrl-len = <0x11>; 156*4882a593Smuzhiyun pl022,wait-state = <0>; 157*4882a593Smuzhiyun pl022,duplex = <0>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun }; 160*4882a593Smuzhiyun... 161