Searched +full:sci +full:- +full:intr (Results 1 – 17 of 17) sorted by relevance
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/21 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based23 * @sci: Pointer to TISCI handle24 * @out_irqs: TISCI resource pointer representing INTR irqs.26 * @ti_sci_id: TI-SCI device identifier30 const struct ti_sci_handle *sci; member38 .name = "INTR",48 * ti_sci_intr_irq_domain_translate() - Retrieve hwirq and type from62 struct ti_sci_intr_irq_domain *intr = domain->host_data; in ti_sci_intr_irq_domain_translate() local[all …]
1 # SPDX-License-Identifier: GPL-2.02 obj-$(CONFIG_IRQCHIP) += irqchip.o4 obj-$(CONFIG_AL_FIC) += irq-al-fic.o5 obj-$(CONFIG_ALPINE_MSI) += irq-alpine-msi.o6 obj-$(CONFIG_ATH79) += irq-ath79-cpu.o7 obj-$(CONFIG_ATH79) += irq-ath79-misc.o8 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o9 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o10 obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o11 obj-$(CONFIG_DAVINCI_AINTC) += irq-davinci-aintc.o[all …]
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Lokesh Vutla <lokeshvutla@ti.com>13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#16 The Interrupt Router (INTR) module provides a mechanism to mux M22 +----------------------+24 +-------+ | +------+ +-----+ |25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "ti,am654-sci";11 ti,host-id = <12>;12 #address-cells = <1>;13 #size-cells = <1>;16 mbox-names = "rx", "tx";21 k3_pds: power-controller {22 compatible = "ti,sci-pm-domain";23 #power-domain-cells = <2>;[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "mmio-sram";12 #address-cells = <1>;13 #size-cells = <1>;16 atf-sram@0 {21 scm_conf: scm-conf@100000 {22 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";24 #address-cells = <1>;25 #size-cells = <1>;[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "ti,k2g-sci";11 ti,host-id = <12>;13 mbox-names = "rx", "tx";18 reg-names = "debug_messages";21 k3_pds: power-controller {22 compatible = "ti,sci-pm-domain";23 #power-domain-cells = <2>;27 compatible = "ti,k2g-sci-clk";[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/10 compatible = "ti,k2g-sci";11 ti,host-id = <12>;13 mbox-names = "rx", "tx";18 reg-names = "debug_messages";21 k3_pds: power-controller {22 compatible = "ti,sci-pm-domain";23 #power-domain-cells = <2>;27 compatible = "ti,k2g-sci-clk";[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy-am654-serdes.h>11 compatible = "mmio-sram";13 #address-cells = <1>;14 #size-cells = <1>;17 atf-sram@0 {21 sysfw-sram@f0000 {25 l3cache-sram@100000 {30 gic500: interrupt-controller@1800000 {[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/7 #include <dt-bindings/phy/phy.h>8 #include <dt-bindings/mux/mux.h>9 #include <dt-bindings/mux/ti-serdes.h>12 cmn_refclk: clock-cmnrefclk {13 #clock-cells = <0>;14 compatible = "fixed-clock";15 clock-frequency = <0>;18 cmn_refclk1: clock-cmnrefclk1 {[all …]
1 // SPDX-License-Identifier: GPL-2.05 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/8 #include <dt-bindings/interrupt-controller/arm-gic.h>9 #include <dt-bindings/pinctrl/keystone.h>10 #include <dt-bindings/gpio/gpio.h>15 #address-cells = <2>;16 #size-cells = <2>;17 interrupt-parent = <&gic>;32 #address-cells = <1>;33 #size-cells = <0>;[all …]
4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf9 - #address-cells: number of cells required to define a chip select11 - #size-cells: should be zero.12 - compatible:13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC17 - reg: Offset and length of SPI controller register space[all …]
25 routed to different processor sub-systems on DRA7xx as they are routed through35 a SoC. The sub-mailboxes are represented as child nodes of this parent node.38 --------------------39 - compatible: Should be one of the following,40 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs41 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs42 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,44 "ti,am654-mailbox" for K3 AM65x and J721E SoCs45 - reg: Contains the mailbox register address range (base47 - interrupts: Contains the interrupt information for the mailbox[all …]
4 * Copyright(c) 2015-2017 Intel Corporation.26 * - Redistributions of source code must retain the above copyright28 * - Redistributions in binary form must reproduce the above copyright32 * - Neither the name of Intel Corporation nor the names of its63 /* PIO release codes - in bits, as there could more than one that apply */70 #define PRC_SC_DISABLE 0x20 /* clean-up after a context disable */97 /* per-NUMA send context */99 /* read-only after init */133 u32 credit_intr_count; /* count of credit intr users */174 * Since the mapping now allows for non-uniform send contexts per vl, the[all …]
2 * Copyright(c) 2015 - 2020 Intel Corporation.24 * - Redistributions of source code must retain the above copyright26 * - Redistributions in binary form must reproduce the above copyright30 * - Neither the name of Intel Corporation nor the names of its73 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");119 #define SEC_SC_HALTED 0x4 /* per-context only */120 #define SEC_SPC_FREEZE 0x8 /* per-HFI only */128 * 0 - User Fecn Handling129 * 1 - Vnic130 * 2 - AIP[all …]
6 * Copyright (C) 2008-2009 coresystems GmbH9 * SPDX-License-Identifier: GPL-2.041 #define INTR 0x3c macro239 #define D22IP_IDERIP 8 /* IDE-R Pin */356 #define INTEL_USB2_EN (1 << 18) /* Intel-Specific USB2 SMI logic */361 #define BIOS_RLS (1 << 7) /* asserts SCI on bit set */381 * pch_silicon_revision() - Read silicon device ID from the PCH389 * pch_pch_iobp_update() - Update a pch register
9 -------------------------30 ``diff -u`` to make the patch easy to merge. Be prepared to get your40 See Documentation/process/coding-style.rst for guidance here.46 See Documentation/process/submitting-patches.rst for details.57 include a Signed-off-by: line. The current version of this59 Documentation/process/submitting-patches.rst.70 that the bug would present a short-term risk to other users if it76 Documentation/admin-guide/security-bugs.rst for details.81 ---------------------------------------------------97 W: *Web-page* with status/info[all …]
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