1*4882a593Smuzhiyun// SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Device Tree Source for K2G SOC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#include <dt-bindings/interrupt-controller/arm-gic.h> 9*4882a593Smuzhiyun#include <dt-bindings/pinctrl/keystone.h> 10*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun compatible = "ti,k2g","ti,keystone"; 14*4882a593Smuzhiyun model = "Texas Instruments K2G SoC"; 15*4882a593Smuzhiyun #address-cells = <2>; 16*4882a593Smuzhiyun #size-cells = <2>; 17*4882a593Smuzhiyun interrupt-parent = <&gic>; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun chosen { }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun aliases { 22*4882a593Smuzhiyun serial0 = &uart0; 23*4882a593Smuzhiyun serial1 = &uart1; 24*4882a593Smuzhiyun serial2 = &uart2; 25*4882a593Smuzhiyun i2c0 = &i2c0; 26*4882a593Smuzhiyun i2c1 = &i2c1; 27*4882a593Smuzhiyun i2c2 = &i2c2; 28*4882a593Smuzhiyun rproc0 = &dsp0; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun cpus { 32*4882a593Smuzhiyun #address-cells = <1>; 33*4882a593Smuzhiyun #size-cells = <0>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun cpu@0 { 36*4882a593Smuzhiyun compatible = "arm,cortex-a15"; 37*4882a593Smuzhiyun device_type = "cpu"; 38*4882a593Smuzhiyun reg = <0>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun gic: interrupt-controller@2561000 { 43*4882a593Smuzhiyun compatible = "arm,gic-400", "arm,cortex-a15-gic"; 44*4882a593Smuzhiyun #interrupt-cells = <3>; 45*4882a593Smuzhiyun interrupt-controller; 46*4882a593Smuzhiyun reg = <0x0 0x02561000 0x0 0x1000>, 47*4882a593Smuzhiyun <0x0 0x02562000 0x0 0x2000>, 48*4882a593Smuzhiyun <0x0 0x02564000 0x0 0x2000>, 49*4882a593Smuzhiyun <0x0 0x02566000 0x0 0x2000>; 50*4882a593Smuzhiyun interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 51*4882a593Smuzhiyun IRQ_TYPE_LEVEL_HIGH)>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun timer { 55*4882a593Smuzhiyun compatible = "arm,armv7-timer"; 56*4882a593Smuzhiyun interrupts = 57*4882a593Smuzhiyun <GIC_PPI 13 58*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 59*4882a593Smuzhiyun <GIC_PPI 14 60*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 61*4882a593Smuzhiyun <GIC_PPI 11 62*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 63*4882a593Smuzhiyun <GIC_PPI 10 64*4882a593Smuzhiyun (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun pmu { 68*4882a593Smuzhiyun compatible = "arm,cortex-a15-pmu"; 69*4882a593Smuzhiyun interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun usbphy { 73*4882a593Smuzhiyun #address-cells = <1>; 74*4882a593Smuzhiyun #size-cells = <0>; 75*4882a593Smuzhiyun compatible = "simple-bus"; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun usb0_phy: usb-phy@0 { 78*4882a593Smuzhiyun compatible = "usb-nop-xceiv"; 79*4882a593Smuzhiyun reg = <0>; 80*4882a593Smuzhiyun status = "disabled"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun usb1_phy: usb-phy@1 { 84*4882a593Smuzhiyun compatible = "usb-nop-xceiv"; 85*4882a593Smuzhiyun reg = <1>; 86*4882a593Smuzhiyun status = "disabled"; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun soc0: soc@0 { 91*4882a593Smuzhiyun #address-cells = <1>; 92*4882a593Smuzhiyun #size-cells = <1>; 93*4882a593Smuzhiyun #pinctrl-cells = <1>; 94*4882a593Smuzhiyun compatible = "ti,keystone","simple-bus"; 95*4882a593Smuzhiyun ranges = <0x0 0x0 0x0 0xc0000000>; 96*4882a593Smuzhiyun dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun msm_ram: sram@c000000 { 99*4882a593Smuzhiyun compatible = "mmio-sram"; 100*4882a593Smuzhiyun reg = <0x0c000000 0x100000>; 101*4882a593Smuzhiyun ranges = <0x0 0x0c000000 0x100000>; 102*4882a593Smuzhiyun #address-cells = <1>; 103*4882a593Smuzhiyun #size-cells = <1>; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun bm-sram@f7000 { 106*4882a593Smuzhiyun reg = <0x000f7000 0x8000>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun k2g_pinctrl: pinmux@2621000 { 111*4882a593Smuzhiyun compatible = "pinctrl-single"; 112*4882a593Smuzhiyun reg = <0x02621000 0x410>; 113*4882a593Smuzhiyun pinctrl-single,register-width = <32>; 114*4882a593Smuzhiyun pinctrl-single,function-mask = <0x001b0007>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun devctrl: device-state-control@2620000 { 118*4882a593Smuzhiyun compatible = "ti,keystone-devctrl", "syscon", "simple-mfd"; 119*4882a593Smuzhiyun reg = <0x02620000 0x1000>; 120*4882a593Smuzhiyun #address-cells = <1>; 121*4882a593Smuzhiyun #size-cells = <1>; 122*4882a593Smuzhiyun ranges = <0x0 0x02620000 0x1000>; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun kirq0: keystone_irq@2a0 { 125*4882a593Smuzhiyun compatible = "ti,keystone-irq"; 126*4882a593Smuzhiyun reg = <0x2a0 0x10>; 127*4882a593Smuzhiyun interrupts = <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>; 128*4882a593Smuzhiyun interrupt-controller; 129*4882a593Smuzhiyun #interrupt-cells = <1>; 130*4882a593Smuzhiyun ti,syscon-dev = <&devctrl 0x2a0>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun dspgpio0: keystone_dsp_gpio@240 { 134*4882a593Smuzhiyun compatible = "ti,keystone-dsp-gpio"; 135*4882a593Smuzhiyun reg = <0x240 0x4>; 136*4882a593Smuzhiyun gpio-controller; 137*4882a593Smuzhiyun #gpio-cells = <2>; 138*4882a593Smuzhiyun gpio,syscon-dev = <&devctrl 0x240>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun uart0: serial@2530c00 { 143*4882a593Smuzhiyun compatible = "ti,da830-uart", "ns16550a"; 144*4882a593Smuzhiyun current-speed = <115200>; 145*4882a593Smuzhiyun reg-shift = <2>; 146*4882a593Smuzhiyun reg-io-width = <4>; 147*4882a593Smuzhiyun reg = <0x02530c00 0x100>; 148*4882a593Smuzhiyun interrupts = <GIC_SPI 164 IRQ_TYPE_EDGE_RISING>; 149*4882a593Smuzhiyun clocks = <&k2g_clks 0x2c 0>; 150*4882a593Smuzhiyun power-domains = <&k2g_pds 0x2c>; 151*4882a593Smuzhiyun status = "disabled"; 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun uart1: serial@2531000 { 155*4882a593Smuzhiyun compatible = "ti,da830-uart", "ns16550a"; 156*4882a593Smuzhiyun current-speed = <115200>; 157*4882a593Smuzhiyun reg-shift = <2>; 158*4882a593Smuzhiyun reg-io-width = <4>; 159*4882a593Smuzhiyun reg = <0x02531000 0x100>; 160*4882a593Smuzhiyun interrupts = <GIC_SPI 165 IRQ_TYPE_EDGE_RISING>; 161*4882a593Smuzhiyun clocks = <&k2g_clks 0x2d 0>; 162*4882a593Smuzhiyun power-domains = <&k2g_pds 0x2d>; 163*4882a593Smuzhiyun status = "disabled"; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun uart2: serial@2531400 { 167*4882a593Smuzhiyun compatible = "ti,da830-uart", "ns16550a"; 168*4882a593Smuzhiyun current-speed = <115200>; 169*4882a593Smuzhiyun reg-shift = <2>; 170*4882a593Smuzhiyun reg-io-width = <4>; 171*4882a593Smuzhiyun reg = <0x02531400 0x100>; 172*4882a593Smuzhiyun interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 173*4882a593Smuzhiyun clocks = <&k2g_clks 0x2e 0>; 174*4882a593Smuzhiyun power-domains = <&k2g_pds 0x2e>; 175*4882a593Smuzhiyun status = "disabled"; 176*4882a593Smuzhiyun }; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun dcan0: can@260b200 { 179*4882a593Smuzhiyun compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 180*4882a593Smuzhiyun reg = <0x0260B200 0x200>; 181*4882a593Smuzhiyun interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 182*4882a593Smuzhiyun status = "disabled"; 183*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0008>; 184*4882a593Smuzhiyun clocks = <&k2g_clks 0x0008 1>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun dcan1: can@260b400 { 188*4882a593Smuzhiyun compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 189*4882a593Smuzhiyun reg = <0x0260B400 0x200>; 190*4882a593Smuzhiyun interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 191*4882a593Smuzhiyun status = "disabled"; 192*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0009>; 193*4882a593Smuzhiyun clocks = <&k2g_clks 0x0009 1>; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun i2c0: i2c@2530000 { 197*4882a593Smuzhiyun compatible = "ti,keystone-i2c"; 198*4882a593Smuzhiyun reg = <0x02530000 0x400>; 199*4882a593Smuzhiyun clocks = <&k2g_clks 0x003a 0>; 200*4882a593Smuzhiyun power-domains = <&k2g_pds 0x003a>; 201*4882a593Smuzhiyun interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 202*4882a593Smuzhiyun #address-cells = <1>; 203*4882a593Smuzhiyun #size-cells = <0>; 204*4882a593Smuzhiyun status = "disabled"; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun i2c1: i2c@2530400 { 208*4882a593Smuzhiyun compatible = "ti,keystone-i2c"; 209*4882a593Smuzhiyun reg = <0x02530400 0x400>; 210*4882a593Smuzhiyun clocks = <&k2g_clks 0x003b 0>; 211*4882a593Smuzhiyun power-domains = <&k2g_pds 0x003b>; 212*4882a593Smuzhiyun interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 213*4882a593Smuzhiyun #address-cells = <1>; 214*4882a593Smuzhiyun #size-cells = <0>; 215*4882a593Smuzhiyun status = "disabled"; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun i2c2: i2c@2530800 { 219*4882a593Smuzhiyun compatible = "ti,keystone-i2c"; 220*4882a593Smuzhiyun reg = <0x02530800 0x400>; 221*4882a593Smuzhiyun clocks = <&k2g_clks 0x003c 0>; 222*4882a593Smuzhiyun power-domains = <&k2g_pds 0x003c>; 223*4882a593Smuzhiyun interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 224*4882a593Smuzhiyun #address-cells = <1>; 225*4882a593Smuzhiyun #size-cells = <0>; 226*4882a593Smuzhiyun status = "disabled"; 227*4882a593Smuzhiyun }; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun dsp0: dsp@10800000 { 230*4882a593Smuzhiyun compatible = "ti,k2g-dsp"; 231*4882a593Smuzhiyun reg = <0x10800000 0x00100000>, 232*4882a593Smuzhiyun <0x10e00000 0x00008000>, 233*4882a593Smuzhiyun <0x10f00000 0x00008000>; 234*4882a593Smuzhiyun reg-names = "l2sram", "l1pram", "l1dram"; 235*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0046>; 236*4882a593Smuzhiyun ti,syscon-dev = <&devctrl 0x844>; 237*4882a593Smuzhiyun resets = <&k2g_reset 0x0046 0x1>; 238*4882a593Smuzhiyun interrupt-parent = <&kirq0>; 239*4882a593Smuzhiyun interrupts = <0 8>; 240*4882a593Smuzhiyun interrupt-names = "vring", "exception"; 241*4882a593Smuzhiyun kick-gpios = <&dspgpio0 27 0>; 242*4882a593Smuzhiyun status = "disabled"; 243*4882a593Smuzhiyun }; 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun msgmgr: msgmgr@2a00000 { 246*4882a593Smuzhiyun compatible = "ti,k2g-message-manager"; 247*4882a593Smuzhiyun #mbox-cells = <2>; 248*4882a593Smuzhiyun reg-names = "queue_proxy_region", 249*4882a593Smuzhiyun "queue_state_debug_region"; 250*4882a593Smuzhiyun reg = <0x02a00000 0x400000>, <0x028c3400 0x400>; 251*4882a593Smuzhiyun interrupt-names = "rx_005", 252*4882a593Smuzhiyun "rx_057"; 253*4882a593Smuzhiyun interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 254*4882a593Smuzhiyun <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun pmmc: pmmc@2921c00 { 258*4882a593Smuzhiyun compatible = "ti,k2g-sci"; 259*4882a593Smuzhiyun /* 260*4882a593Smuzhiyun * In case of rare platforms that does not use k2g as 261*4882a593Smuzhiyun * system master, use /delete-property/ 262*4882a593Smuzhiyun */ 263*4882a593Smuzhiyun ti,system-reboot-controller; 264*4882a593Smuzhiyun mbox-names = "rx", "tx"; 265*4882a593Smuzhiyun mboxes= <&msgmgr 5 2>, 266*4882a593Smuzhiyun <&msgmgr 0 0>; 267*4882a593Smuzhiyun reg-names = "debug_messages"; 268*4882a593Smuzhiyun reg = <0x02921c00 0x400>; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun k2g_pds: power-controller { 271*4882a593Smuzhiyun compatible = "ti,sci-pm-domain"; 272*4882a593Smuzhiyun #power-domain-cells = <1>; 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun k2g_clks: clocks { 276*4882a593Smuzhiyun compatible = "ti,k2g-sci-clk"; 277*4882a593Smuzhiyun #clock-cells = <2>; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun k2g_reset: reset-controller { 281*4882a593Smuzhiyun compatible = "ti,sci-reset"; 282*4882a593Smuzhiyun #reset-cells = <2>; 283*4882a593Smuzhiyun }; 284*4882a593Smuzhiyun }; 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun gpio0: gpio@2603000 { 287*4882a593Smuzhiyun compatible = "ti,k2g-gpio", "ti,keystone-gpio"; 288*4882a593Smuzhiyun reg = <0x02603000 0x100>; 289*4882a593Smuzhiyun gpio-controller; 290*4882a593Smuzhiyun #gpio-cells = <2>; 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>, 293*4882a593Smuzhiyun <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>, 294*4882a593Smuzhiyun <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>, 295*4882a593Smuzhiyun <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>, 296*4882a593Smuzhiyun <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>, 297*4882a593Smuzhiyun <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>, 298*4882a593Smuzhiyun <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>, 299*4882a593Smuzhiyun <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>, 300*4882a593Smuzhiyun <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>; 301*4882a593Smuzhiyun interrupt-controller; 302*4882a593Smuzhiyun #interrupt-cells = <2>; 303*4882a593Smuzhiyun ti,ngpio = <144>; 304*4882a593Smuzhiyun ti,davinci-gpio-unbanked = <0>; 305*4882a593Smuzhiyun clocks = <&k2g_clks 0x001b 0x0>; 306*4882a593Smuzhiyun clock-names = "gpio"; 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun gpio1: gpio@260a000 { 310*4882a593Smuzhiyun compatible = "ti,k2g-gpio", "ti,keystone-gpio"; 311*4882a593Smuzhiyun reg = <0x0260a000 0x100>; 312*4882a593Smuzhiyun gpio-controller; 313*4882a593Smuzhiyun #gpio-cells = <2>; 314*4882a593Smuzhiyun interrupts = <GIC_SPI 442 IRQ_TYPE_EDGE_RISING>, 315*4882a593Smuzhiyun <GIC_SPI 443 IRQ_TYPE_EDGE_RISING>, 316*4882a593Smuzhiyun <GIC_SPI 444 IRQ_TYPE_EDGE_RISING>, 317*4882a593Smuzhiyun <GIC_SPI 445 IRQ_TYPE_EDGE_RISING>, 318*4882a593Smuzhiyun <GIC_SPI 446 IRQ_TYPE_EDGE_RISING>; 319*4882a593Smuzhiyun interrupt-controller; 320*4882a593Smuzhiyun #interrupt-cells = <2>; 321*4882a593Smuzhiyun ti,ngpio = <68>; 322*4882a593Smuzhiyun ti,davinci-gpio-unbanked = <0>; 323*4882a593Smuzhiyun clocks = <&k2g_clks 0x001c 0x0>; 324*4882a593Smuzhiyun clock-names = "gpio"; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun dss: dss@02540000 { 328*4882a593Smuzhiyun compatible = "ti,k2g-dss"; 329*4882a593Smuzhiyun reg = <0x02540000 0x400>, 330*4882a593Smuzhiyun <0x02550000 0x1000>, 331*4882a593Smuzhiyun <0x02557000 0x1000>, 332*4882a593Smuzhiyun <0x0255a800 0x100>, 333*4882a593Smuzhiyun <0x0255ac00 0x100>; 334*4882a593Smuzhiyun reg-names = "cfg", "common", "vid1", "ovr1", "vp1"; 335*4882a593Smuzhiyun clocks = <&k2g_clks 0x2 0>, 336*4882a593Smuzhiyun <&k2g_clks 0x2 1>; 337*4882a593Smuzhiyun clock-names = "fck", "vp1"; 338*4882a593Smuzhiyun interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>; 339*4882a593Smuzhiyun 340*4882a593Smuzhiyun power-domains = <&k2g_pds 0x2>; 341*4882a593Smuzhiyun status = "disabled"; 342*4882a593Smuzhiyun #address-cells = <1>; 343*4882a593Smuzhiyun #size-cells = <1>; 344*4882a593Smuzhiyun ranges; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun max-memory-bandwidth = <230000000>; 347*4882a593Smuzhiyun }; 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun edma0: edma@2700000 { 350*4882a593Smuzhiyun compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; 351*4882a593Smuzhiyun reg = <0x02700000 0x8000>; 352*4882a593Smuzhiyun reg-names = "edma3_cc"; 353*4882a593Smuzhiyun interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, 354*4882a593Smuzhiyun <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>, 355*4882a593Smuzhiyun <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 356*4882a593Smuzhiyun interrupt-names = "edma3_ccint", "emda3_mperr", 357*4882a593Smuzhiyun "edma3_ccerrint"; 358*4882a593Smuzhiyun dma-requests = <64>; 359*4882a593Smuzhiyun #dma-cells = <2>; 360*4882a593Smuzhiyun 361*4882a593Smuzhiyun ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>; 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun ti,edma-memcpy-channels = <32 33 34 35>; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun power-domains = <&k2g_pds 0x3f>; 366*4882a593Smuzhiyun }; 367*4882a593Smuzhiyun 368*4882a593Smuzhiyun edma0_tptc0: tptc@2760000 { 369*4882a593Smuzhiyun compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; 370*4882a593Smuzhiyun reg = <0x02760000 0x400>; 371*4882a593Smuzhiyun power-domains = <&k2g_pds 0x3f>; 372*4882a593Smuzhiyun }; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun edma0_tptc1: tptc@2768000 { 375*4882a593Smuzhiyun compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; 376*4882a593Smuzhiyun reg = <0x02768000 0x400>; 377*4882a593Smuzhiyun power-domains = <&k2g_pds 0x3f>; 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun edma1: edma@2728000 { 381*4882a593Smuzhiyun compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc"; 382*4882a593Smuzhiyun reg = <0x02728000 0x8000>; 383*4882a593Smuzhiyun reg-names = "edma3_cc"; 384*4882a593Smuzhiyun interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 385*4882a593Smuzhiyun <GIC_SPI 219 IRQ_TYPE_EDGE_RISING>, 386*4882a593Smuzhiyun <GIC_SPI 220 IRQ_TYPE_EDGE_RISING>; 387*4882a593Smuzhiyun interrupt-names = "edma3_ccint", "emda3_mperr", 388*4882a593Smuzhiyun "edma3_ccerrint"; 389*4882a593Smuzhiyun dma-requests = <64>; 390*4882a593Smuzhiyun #dma-cells = <2>; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>; 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun /* 395*4882a593Smuzhiyun * memcpy is disabled, can be enabled with: 396*4882a593Smuzhiyun * ti,edma-memcpy-channels = <12 13 14 15>; 397*4882a593Smuzhiyun * for example. 398*4882a593Smuzhiyun */ 399*4882a593Smuzhiyun 400*4882a593Smuzhiyun power-domains = <&k2g_pds 0x4f>; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun edma1_tptc0: tptc@27b0000 { 404*4882a593Smuzhiyun compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; 405*4882a593Smuzhiyun reg = <0x027b0000 0x400>; 406*4882a593Smuzhiyun power-domains = <&k2g_pds 0x4f>; 407*4882a593Smuzhiyun }; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun edma1_tptc1: tptc@27b8000 { 410*4882a593Smuzhiyun compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc"; 411*4882a593Smuzhiyun reg = <0x027b8000 0x400>; 412*4882a593Smuzhiyun power-domains = <&k2g_pds 0x4f>; 413*4882a593Smuzhiyun }; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun mmc0: mmc@23000000 { 416*4882a593Smuzhiyun compatible = "ti,k2g-sdhci"; 417*4882a593Smuzhiyun reg = <0x23000000 0x400>; 418*4882a593Smuzhiyun interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>; 419*4882a593Smuzhiyun bus-width = <4>; 420*4882a593Smuzhiyun no-1-8-v; 421*4882a593Smuzhiyun max-frequency = <96000000>; 422*4882a593Smuzhiyun power-domains = <&k2g_pds 0xb>; 423*4882a593Smuzhiyun clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>; 424*4882a593Smuzhiyun clock-names = "fck", "mmchsdb_fck"; 425*4882a593Smuzhiyun status = "disabled"; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun mmc1: mmc@23100000 { 429*4882a593Smuzhiyun compatible = "ti,k2g-sdhci"; 430*4882a593Smuzhiyun reg = <0x23100000 0x400>; 431*4882a593Smuzhiyun interrupts = <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>; 432*4882a593Smuzhiyun bus-width = <8>; 433*4882a593Smuzhiyun no-1-8-v; 434*4882a593Smuzhiyun non-removable; 435*4882a593Smuzhiyun max-frequency = <96000000>; 436*4882a593Smuzhiyun power-domains = <&k2g_pds 0xc>; 437*4882a593Smuzhiyun clocks = <&k2g_clks 0xc 1>, <&k2g_clks 0xc 2>; 438*4882a593Smuzhiyun clock-names = "fck", "mmchsdb_fck"; 439*4882a593Smuzhiyun }; 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun qspi: spi@2940000 { 442*4882a593Smuzhiyun compatible = "ti,k2g-qspi", "cdns,qspi-nor"; 443*4882a593Smuzhiyun #address-cells = <1>; 444*4882a593Smuzhiyun #size-cells = <0>; 445*4882a593Smuzhiyun reg = <0x02940000 0x1000>, 446*4882a593Smuzhiyun <0x24000000 0x4000000>; 447*4882a593Smuzhiyun interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>; 448*4882a593Smuzhiyun cdns,fifo-depth = <256>; 449*4882a593Smuzhiyun cdns,fifo-width = <4>; 450*4882a593Smuzhiyun cdns,trigger-address = <0x24000000>; 451*4882a593Smuzhiyun clocks = <&k2g_clks 0x43 0x0>; 452*4882a593Smuzhiyun power-domains = <&k2g_pds 0x43>; 453*4882a593Smuzhiyun status = "disabled"; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun mcasp0: mcasp@2340000 { 457*4882a593Smuzhiyun compatible = "ti,am33xx-mcasp-audio"; 458*4882a593Smuzhiyun reg = <0x02340000 0x2000>, 459*4882a593Smuzhiyun <0x21804000 0x1000>; 460*4882a593Smuzhiyun reg-names = "mpu","dat"; 461*4882a593Smuzhiyun interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 462*4882a593Smuzhiyun <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 463*4882a593Smuzhiyun interrupt-names = "tx", "rx"; 464*4882a593Smuzhiyun dmas = <&edma0 24 1>, <&edma0 25 1>; 465*4882a593Smuzhiyun dma-names = "tx", "rx"; 466*4882a593Smuzhiyun power-domains = <&k2g_pds 0x4>; 467*4882a593Smuzhiyun clocks = <&k2g_clks 0x4 0>; 468*4882a593Smuzhiyun clock-names = "fck"; 469*4882a593Smuzhiyun status = "disabled"; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun 472*4882a593Smuzhiyun mcasp1: mcasp@2342000 { 473*4882a593Smuzhiyun compatible = "ti,am33xx-mcasp-audio"; 474*4882a593Smuzhiyun reg = <0x02342000 0x2000>, 475*4882a593Smuzhiyun <0x21804400 0x1000>; 476*4882a593Smuzhiyun reg-names = "mpu","dat"; 477*4882a593Smuzhiyun interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 478*4882a593Smuzhiyun <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 479*4882a593Smuzhiyun interrupt-names = "tx", "rx"; 480*4882a593Smuzhiyun dmas = <&edma1 48 1>, <&edma1 49 1>; 481*4882a593Smuzhiyun dma-names = "tx", "rx"; 482*4882a593Smuzhiyun power-domains = <&k2g_pds 0x5>; 483*4882a593Smuzhiyun clocks = <&k2g_clks 0x5 0>; 484*4882a593Smuzhiyun clock-names = "fck"; 485*4882a593Smuzhiyun status = "disabled"; 486*4882a593Smuzhiyun }; 487*4882a593Smuzhiyun 488*4882a593Smuzhiyun mcasp2: mcasp@2344000 { 489*4882a593Smuzhiyun compatible = "ti,am33xx-mcasp-audio"; 490*4882a593Smuzhiyun reg = <0x02344000 0x2000>, 491*4882a593Smuzhiyun <0x21804800 0x1000>; 492*4882a593Smuzhiyun reg-names = "mpu","dat"; 493*4882a593Smuzhiyun interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 494*4882a593Smuzhiyun <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 495*4882a593Smuzhiyun interrupt-names = "tx", "rx"; 496*4882a593Smuzhiyun dmas = <&edma1 50 1>, <&edma1 51 1>; 497*4882a593Smuzhiyun dma-names = "tx", "rx"; 498*4882a593Smuzhiyun power-domains = <&k2g_pds 0x6>; 499*4882a593Smuzhiyun clocks = <&k2g_clks 0x6 0>; 500*4882a593Smuzhiyun clock-names = "fck"; 501*4882a593Smuzhiyun status = "disabled"; 502*4882a593Smuzhiyun }; 503*4882a593Smuzhiyun 504*4882a593Smuzhiyun keystone_usb0: keystone-dwc3@2680000 { 505*4882a593Smuzhiyun compatible = "ti,keystone-dwc3"; 506*4882a593Smuzhiyun #address-cells = <1>; 507*4882a593Smuzhiyun #size-cells = <1>; 508*4882a593Smuzhiyun reg = <0x2680000 0x10000>; 509*4882a593Smuzhiyun interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>; 510*4882a593Smuzhiyun ranges; 511*4882a593Smuzhiyun dma-coherent; 512*4882a593Smuzhiyun dma-ranges; 513*4882a593Smuzhiyun status = "disabled"; 514*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0016>; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun usb0: usb@2690000 { 517*4882a593Smuzhiyun compatible = "snps,dwc3"; 518*4882a593Smuzhiyun reg = <0x2690000 0x10000>; 519*4882a593Smuzhiyun interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>; 520*4882a593Smuzhiyun maximum-speed = "high-speed"; 521*4882a593Smuzhiyun dr_mode = "otg"; 522*4882a593Smuzhiyun usb-phy = <&usb0_phy>; 523*4882a593Smuzhiyun status = "disabled"; 524*4882a593Smuzhiyun }; 525*4882a593Smuzhiyun }; 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun keystone_usb1: keystone-dwc3@2580000 { 528*4882a593Smuzhiyun compatible = "ti,keystone-dwc3"; 529*4882a593Smuzhiyun #address-cells = <1>; 530*4882a593Smuzhiyun #size-cells = <1>; 531*4882a593Smuzhiyun reg = <0x2580000 0x10000>; 532*4882a593Smuzhiyun interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 533*4882a593Smuzhiyun ranges; 534*4882a593Smuzhiyun dma-coherent; 535*4882a593Smuzhiyun dma-ranges; 536*4882a593Smuzhiyun status = "disabled"; 537*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0017>; 538*4882a593Smuzhiyun 539*4882a593Smuzhiyun usb1: usb@2590000 { 540*4882a593Smuzhiyun compatible = "snps,dwc3"; 541*4882a593Smuzhiyun reg = <0x2590000 0x10000>; 542*4882a593Smuzhiyun interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 543*4882a593Smuzhiyun maximum-speed = "high-speed"; 544*4882a593Smuzhiyun dr_mode = "otg"; 545*4882a593Smuzhiyun usb-phy = <&usb1_phy>; 546*4882a593Smuzhiyun status = "disabled"; 547*4882a593Smuzhiyun }; 548*4882a593Smuzhiyun }; 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun ecap0: pwm@21d1800 { 551*4882a593Smuzhiyun compatible = "ti,k2g-ecap", "ti,am3352-ecap"; 552*4882a593Smuzhiyun #pwm-cells = <3>; 553*4882a593Smuzhiyun reg = <0x021d1800 0x60>; 554*4882a593Smuzhiyun power-domains = <&k2g_pds 0x38>; 555*4882a593Smuzhiyun clocks = <&k2g_clks 0x38 0>; 556*4882a593Smuzhiyun clock-names = "fck"; 557*4882a593Smuzhiyun status = "disabled"; 558*4882a593Smuzhiyun }; 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun ecap1: pwm@21d1c00 { 561*4882a593Smuzhiyun compatible = "ti,k2g-ecap", "ti,am3352-ecap"; 562*4882a593Smuzhiyun #pwm-cells = <3>; 563*4882a593Smuzhiyun reg = <0x021d1c00 0x60>; 564*4882a593Smuzhiyun power-domains = <&k2g_pds 0x39>; 565*4882a593Smuzhiyun clocks = <&k2g_clks 0x39 0x0>; 566*4882a593Smuzhiyun clock-names = "fck"; 567*4882a593Smuzhiyun status = "disabled"; 568*4882a593Smuzhiyun }; 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun spi0: spi@21805400 { 571*4882a593Smuzhiyun compatible = "ti,keystone-spi"; 572*4882a593Smuzhiyun reg = <0x21805400 0x200>; 573*4882a593Smuzhiyun num-cs = <4>; 574*4882a593Smuzhiyun ti,davinci-spi-intr-line = <0>; 575*4882a593Smuzhiyun interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>; 576*4882a593Smuzhiyun #address-cells = <1>; 577*4882a593Smuzhiyun #size-cells = <0>; 578*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0010>; 579*4882a593Smuzhiyun clocks = <&k2g_clks 0x0010 0>; 580*4882a593Smuzhiyun }; 581*4882a593Smuzhiyun 582*4882a593Smuzhiyun spi1: spi@21805800 { 583*4882a593Smuzhiyun compatible = "ti,keystone-spi"; 584*4882a593Smuzhiyun reg = <0x21805800 0x200>; 585*4882a593Smuzhiyun num-cs = <4>; 586*4882a593Smuzhiyun ti,davinci-spi-intr-line = <0>; 587*4882a593Smuzhiyun interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>; 588*4882a593Smuzhiyun #address-cells = <1>; 589*4882a593Smuzhiyun #size-cells = <0>; 590*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0011>; 591*4882a593Smuzhiyun clocks = <&k2g_clks 0x0011 0>; 592*4882a593Smuzhiyun }; 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun spi2: spi@21805c00 { 595*4882a593Smuzhiyun compatible = "ti,keystone-spi"; 596*4882a593Smuzhiyun reg = <0x21805C00 0x200>; 597*4882a593Smuzhiyun num-cs = <4>; 598*4882a593Smuzhiyun ti,davinci-spi-intr-line = <0>; 599*4882a593Smuzhiyun interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 600*4882a593Smuzhiyun #address-cells = <1>; 601*4882a593Smuzhiyun #size-cells = <0>; 602*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0012>; 603*4882a593Smuzhiyun clocks = <&k2g_clks 0x0012 0>; 604*4882a593Smuzhiyun }; 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun spi3: spi@21806000 { 607*4882a593Smuzhiyun compatible = "ti,keystone-spi"; 608*4882a593Smuzhiyun reg = <0x21806000 0x200>; 609*4882a593Smuzhiyun num-cs = <4>; 610*4882a593Smuzhiyun ti,davinci-spi-intr-line = <0>; 611*4882a593Smuzhiyun interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 612*4882a593Smuzhiyun #address-cells = <1>; 613*4882a593Smuzhiyun #size-cells = <0>; 614*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0013>; 615*4882a593Smuzhiyun clocks = <&k2g_clks 0x0013 0>; 616*4882a593Smuzhiyun }; 617*4882a593Smuzhiyun 618*4882a593Smuzhiyun wdt: wdt@02250000 { 619*4882a593Smuzhiyun compatible = "ti,keystone-wdt", "ti,davinci-wdt"; 620*4882a593Smuzhiyun reg = <0x02250000 0x80>; 621*4882a593Smuzhiyun power-domains = <&k2g_pds 0x22>; 622*4882a593Smuzhiyun clocks = <&k2g_clks 0x22 0>; 623*4882a593Smuzhiyun }; 624*4882a593Smuzhiyun 625*4882a593Smuzhiyun emif: emif@21010000 { 626*4882a593Smuzhiyun compatible = "ti,emif-keystone"; 627*4882a593Smuzhiyun reg = <0x21010000 0x200>; 628*4882a593Smuzhiyun interrupts = <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>; 629*4882a593Smuzhiyun }; 630*4882a593Smuzhiyun 631*4882a593Smuzhiyun mdio: mdio@4200f00 { 632*4882a593Smuzhiyun compatible = "ti,keystone_mdio", "ti,davinci_mdio"; 633*4882a593Smuzhiyun reg = <0x04200f00 0x100>; 634*4882a593Smuzhiyun #address-cells = <1>; 635*4882a593Smuzhiyun #size-cells = <0>; 636*4882a593Smuzhiyun clocks = <&k2g_clks 0x0018 3>; 637*4882a593Smuzhiyun clock-names = "fck"; 638*4882a593Smuzhiyun power-domains = <&k2g_pds 0x0018>; 639*4882a593Smuzhiyun status = "disabled"; 640*4882a593Smuzhiyun bus_freq = <2500000>; 641*4882a593Smuzhiyun }; 642*4882a593Smuzhiyun #include "keystone-k2g-netcp.dtsi" 643*4882a593Smuzhiyun }; 644*4882a593Smuzhiyun}; 645