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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3588j.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 * The Max frequency is 1296MHz in default normal mode.
12 * The Max frequency is 1704MHz in overdrive mode,
17 /delete-node/ opp-j-m-1416000000;
18 /delete-node/ opp-j-m-1608000000;
19 /delete-node/ opp-j-m-1704000000;
24 * The Max frequency is 1608MHz in default normal mode.
25 * The Max frequency is 2016MHz in overdrive mode,
30 /delete-node/ opp-j-m-1800000000;
31 /delete-node/ opp-j-m-2016000000;
[all …]
/OK3568_Linux_fs/kernel/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
49 The top-level help describes arguments and features. Notice that there is a
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/OK3568_Linux_fs/kernel/Documentation/cpu-freq/
H A Dcpu-drivers.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - Dominik Brodowski <linux@brodo.de>
11 - Rafael J. Wysocki <rafael.j.wysocki@intel.com>
12 - Viresh Kumar <viresh.kumar@linaro.org>
18 1.2 Per-CPU Initialization
24 2. Frequency Table Helpers
31 So, you just got a brand-new CPU / chipset with datasheets and want to
37 ------------------
46 .name - The name of this driver.
48 .init - A pointer to the per-policy initialization function.
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/OK3568_Linux_fs/kernel/drivers/cpufreq/
H A Dfreq_table.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2002 - 2003 Dominik Brodowski
15 * FREQUENCY TABLE HELPERS *
20 struct cpufreq_frequency_table *pos, *table = policy->freq_table; in policy_has_boost_freq()
26 if (pos->flags & CPUFREQ_BOOST_FREQ) in policy_has_boost_freq()
42 freq = pos->frequency; in cpufreq_frequency_table_cpuinfo()
45 && (pos->flags & CPUFREQ_BOOST_FREQ)) in cpufreq_frequency_table_cpuinfo()
48 pr_debug("table entry %u: %u kHz\n", (int)(pos - table), freq); in cpufreq_frequency_table_cpuinfo()
56 policy->min = policy->cpuinfo.min_freq = min_freq; in cpufreq_frequency_table_cpuinfo()
57 policy->max = max_freq; in cpufreq_frequency_table_cpuinfo()
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dqcom-msm8960-cdp.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
4 #include "qcom-msm8960.dtsi"
8 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
15 stdout-path = "serial0:115200n8";
41 compatible = "qcom,rpm-pm8921-regulators";
42 vin_lvs1_3_6-supply = <&pm8921_s4>;
43 vin_lvs2-supply = <&pm8921_s4>;
44 vin_lvs4_5_7-supply = <&pm8921_s4>;
45 vdd_ncp-supply = <&pm8921_l6>;
[all …]
H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
27 compatible = "arm,cortex-a15";
30 clock-frequency = <1800000000>;
31 cci-control-port = <&cci_control1>;
32 operating-points-v2 = <&cluster_a15_opp_table>;
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H A Dbcm28155-ap.dts14 /dts-v1/;
16 #include <dt-bindings/gpio/gpio.h>
22 compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
35 clock-frequency = <400000>;
40 clock-frequency = <400000>;
45 clock-frequency = <400000>;
50 clock-frequency = <100000>;
58 non-removable;
59 max-frequency = <48000000>;
60 vmmc-supply = <&camldo1_reg>;
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H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
26 compatible = "arm,cortex-a7";
29 clock-frequency = <1000000000>;
30 cci-control-port = <&cci_control0>;
31 operating-points-v2 = <&cluster_a7_opp_table>;
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H A Dqcom-apq8064-sony-xperia-yuga.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 compatible = "sony,xperia-yuga", "qcom,apq8064";
17 stdout-path = "serial0:115200n8";
20 gpio-keys {
21 compatible = "gpio-keys";
[all …]
/OK3568_Linux_fs/kernel/include/linux/
H A Dcpufreq.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
24 * Frequency values here are CPU kHz
26 * Maximum transition latency is in nanoseconds - if it's unknown,
30 #define CPUFREQ_ETERNAL (-1)
47 /* in 10^(-9) s = nanoseconds */
65 unsigned int max; /* in kHz */ member
68 unsigned int restore_freq; /* = policy->cur before transition */
93 * - Any routine that wants to read from the policy structure will
95 * - Any routine that will write to the policy structure and/or may take away
[all …]
/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Dtegra30-apalis.dts1 /dts-v1/;
10 stdout-path = &uarta;
35 pcie-controller@00003000 {
37 avdd-pexa-supply = <&vdd2_reg>;
38 vdd-pexa-supply = <&vdd2_reg>;
39 avdd-pexb-supply = <&vdd2_reg>;
40 vdd-pexb-supply = <&vdd2_reg>;
41 avdd-pex-pll-supply = <&vdd2_reg>;
42 avdd-plle-supply = <&ldo6_reg>;
43 vddio-pex-ctl-supply = <&sys_3v3_reg>;
[all …]
H A Dtegra124-cei-tk1-som.dts1 /dts-v1/;
6 model = "Colorado Engineering TK1-SOM";
7 compatible = "nvidia,cei-tk1-som", "nvidia,tegra124";
10 stdout-path = &uartd;
32 pcie-controller@01003000 {
35 avddio-pex-supply = <&vdd_1v05_run>;
36 dvddio-pex-supply = <&vdd_1v05_run>;
37 avdd-pex-pll-supply = <&vdd_1v05_run>;
38 hvdd-pex-supply = <&vdd_3v3_lp0>;
39 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
[all …]
H A Dtegra124-jetson-tk1.dts1 /dts-v1/;
7 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
10 stdout-path = &uartd;
32 pcie-controller@01003000 {
35 avddio-pex-supply = <&vdd_1v05_run>;
36 dvddio-pex-supply = <&vdd_1v05_run>;
37 avdd-pex-pll-supply = <&vdd_1v05_run>;
38 hvdd-pex-supply = <&vdd_3v3_lp0>;
39 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
40 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
[all …]
H A Dtegra30-beaver.dts1 /dts-v1/;
10 stdout-path = &uarta;
31 pcie-controller@00003000 {
34 avdd-pexa-supply = <&ldo1_reg>;
35 vdd-pexa-supply = <&ldo1_reg>;
36 avdd-pexb-supply = <&ldo1_reg>;
37 vdd-pexb-supply = <&ldo1_reg>;
38 avdd-pex-pll-supply = <&ldo1_reg>;
39 avdd-plle-supply = <&ldo1_reg>;
40 vddio-pex-ctl-supply = <&sys_3v3_reg>;
[all …]
H A Dtegra210-p2571.dts1 /dts-v1/;
10 stdout-path = &uarta;
34 clock-frequency = <100000>;
39 clock-frequency = <100000>;
44 clock-frequency = <100000>;
49 clock-frequency = <100000>;
54 clock-frequency = <400000>;
59 clock-frequency = <400000>;
64 spi-max-frequency = <25000000>;
69 spi-max-frequency = <25000000>;
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-rockchip.txt5 and get frequency count from pvtm, then supplies the OPP framework
6 with 'prop' information which is used to determine opp-microvolt-<name>
8 on operating-points-v2, but the driver can also create the "cpufreq-dt"
9 platform_device to compatibility with operating-points.
14 In 'operating-points-v2' table:
15 - rockchip,leakage-voltage-sel: The property is an array of 3-tuples items, and
17 <min-leakage max-leakage volt-selector>.
18 min-leakage: minimum leakage in mA, ranges from 1 to 254.
19 max-leakage: maximum leakage in mA, ranges from 1 to 254.
20 voltage-selector: a sequence number which is used to math
[all …]
/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/spi/
H A Dspi-stm32-qspi.txt2 --------------------------------------------
5 - compatible : should be "st,stm32-qspi".
6 - reg : 1. Physical base address and size of SPI registers map.
8 - spi-max-frequency : Max supported spi frequency.
9 - status : enable in requried dts.
12 --------------------------
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
15 - spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
16 - memory-map : Address and size for memory-mapping the flash
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/resolver/
H A Dad2s90.txt1 Analog Devices AD2S90 Resolver-to-Digital Converter
6 - compatible: should be "adi,ad2s90"
7 - reg: SPI chip select number for the device
8 - spi-max-frequency: set maximum clock frequency, must be 830000
9 - spi-cpol and spi-cpha:
11 spi-cpha, spi-cpol.
14 Documentation/devicetree/bindings/spi/spi-bus.txt
16 Note about max frequency:
17 Chip's max frequency, as specified in its datasheet, is 2Mhz. But a 600ns
21 2 * 600ns, so the max frequency should be 1 / (2 * 6e-7), which gives
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/OK3568_Linux_fs/kernel/Documentation/admin-guide/media/
H A Dsi4713.rst1 .. SPDX-License-Identifier: GPL-2.0
14 ----------------------------
26 Users must comply with local regulations on radio frequency (RF) transmission.
29 -------------------------
34 The I2C device driver exports a v4l2-subdev interface to the kernel.
36 using the v4l2-subdev calls (g_ext_ctrls, s_ext_ctrls).
42 Applications can use v4l2 radio API to specify frequency of operation, mute state,
48 ----------------------
51 Here is an output from v4l2-ctl util:
53 .. code-block:: none
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
29 stdout-path = "serial0:115200n8";
37 sys_mclk: clock-mclk {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <25000000>;
43 reg_1p8v: regulator-1p8v {
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/spi/
H A Dqcom,spi-qup.txt4 and an input FIFO) for serial peripheral interface (SPI) mini-core.
10 - compatible: Should contain:
11 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
12 "qcom,spi-qup-v2.1.1" for 8974 and later
13 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
15 - reg: Should contain base register location and length
16 - interrupts: Interrupt number used by this controller
18 - clocks: Should contain the core clock and the AHB clock.
19 - clock-names: Should be "core" for the core clock and "iface" for the
22 - #address-cells: Number of cells required to define a chip select
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dselftest_rps.c1 // SPDX-License-Identifier: MIT
21 /* Try to isolate the impact of cstates from determing frequency response */
22 #define CPU_LATENCY 0 /* -1 to disable pm_qos, 0 to disable cstates */
33 return -1; in cmp_u64()
45 return -1; in cmp_u32()
64 #define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x) in create_spin_counter()
72 obj = i915_gem_object_create_internal(vm->i915, 64 << 10); in create_spin_counter()
76 end = obj->base.size / sizeof(u32) - 1; in create_spin_counter()
109 loop = cs - base; in create_spin_counter()
122 *cs++ = lower_32_bits(vma->node.start + end * sizeof(*cs)); in create_spin_counter()
[all …]
/OK3568_Linux_fs/kernel/arch/riscv/boot/dts/sifive/
H A Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
9 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
13 #address-cells = <2>;
14 #size-cells = <2>;
16 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
[all …]
/OK3568_Linux_fs/kernel/tools/power/cpupower/utils/
H A Dcpufreq-info.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2004-2009 Dominik Brodowski <linux@dominikbrodowski.de>
39 value[LINE_LEN - 1] = '\0'; in count_cpus()
40 if (strlen(value) < (LINE_LEN - 2)) in count_cpus()
62 unsigned long min, max; in proc_cpufreq_output() local
64 printf(_(" minimum CPU frequency - maximum CPU frequency - governor\n")); in proc_cpufreq_output()
72 if (cpufreq_get_hardware_limits(cpu, &min, &max)) { in proc_cpufreq_output()
73 max = 0; in proc_cpufreq_output()
75 min_pctg = (policy->min * 100) / max; in proc_cpufreq_output()
76 max_pctg = (policy->max * 100) / max; in proc_cpufreq_output()
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/OK3568_Linux_fs/kernel/drivers/memory/samsung/
H A Dexynos5422-dmc.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <linux/devfreq-event.h>
100 * struct dmc_opp_table - Operating level desciption
101 * @freq_hz: target frequency in Hz
104 * Covers frequency and voltage settings of the DMC operating mode.
112 * struct exynos5_dmc - main structure describing DMC device
119 * @lock: protects curr_rate and frequency/voltage setting section
120 * @curr_rate: current frequency
159 /* Protects curr_rate and frequency/voltage setting section */
195 __val = (t_val) << (timing)->bit_beg; \
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