1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*4882a593Smuzhiyun/* Copyright (c) 2018-2019 SiFive, Inc */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun#include "fu540-c000.dtsi" 5*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 6*4882a593Smuzhiyun#include <dt-bindings/leds/common.h> 7*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ 10*4882a593Smuzhiyun#define RTCCLK_FREQ 1000000 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun #address-cells = <2>; 14*4882a593Smuzhiyun #size-cells = <2>; 15*4882a593Smuzhiyun model = "SiFive HiFive Unleashed A00"; 16*4882a593Smuzhiyun compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun chosen { 19*4882a593Smuzhiyun stdout-path = "serial0"; 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun cpus { 23*4882a593Smuzhiyun timebase-frequency = <RTCCLK_FREQ>; 24*4882a593Smuzhiyun }; 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun memory@80000000 { 27*4882a593Smuzhiyun device_type = "memory"; 28*4882a593Smuzhiyun reg = <0x0 0x80000000 0x2 0x00000000>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun soc { 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun hfclk: hfclk { 35*4882a593Smuzhiyun #clock-cells = <0>; 36*4882a593Smuzhiyun compatible = "fixed-clock"; 37*4882a593Smuzhiyun clock-frequency = <33333333>; 38*4882a593Smuzhiyun clock-output-names = "hfclk"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun rtcclk: rtcclk { 42*4882a593Smuzhiyun #clock-cells = <0>; 43*4882a593Smuzhiyun compatible = "fixed-clock"; 44*4882a593Smuzhiyun clock-frequency = <RTCCLK_FREQ>; 45*4882a593Smuzhiyun clock-output-names = "rtcclk"; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun gpio-restart { 48*4882a593Smuzhiyun compatible = "gpio-restart"; 49*4882a593Smuzhiyun gpios = <&gpio 10 GPIO_ACTIVE_LOW>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun led-controller { 53*4882a593Smuzhiyun compatible = "pwm-leds"; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun led-d1 { 56*4882a593Smuzhiyun pwms = <&pwm0 0 7812500 PWM_POLARITY_INVERTED>; 57*4882a593Smuzhiyun active-low; 58*4882a593Smuzhiyun color = <LED_COLOR_ID_GREEN>; 59*4882a593Smuzhiyun max-brightness = <255>; 60*4882a593Smuzhiyun label = "d1"; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun led-d2 { 64*4882a593Smuzhiyun pwms = <&pwm0 1 7812500 PWM_POLARITY_INVERTED>; 65*4882a593Smuzhiyun active-low; 66*4882a593Smuzhiyun color = <LED_COLOR_ID_GREEN>; 67*4882a593Smuzhiyun max-brightness = <255>; 68*4882a593Smuzhiyun label = "d2"; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun led-d3 { 72*4882a593Smuzhiyun pwms = <&pwm0 2 7812500 PWM_POLARITY_INVERTED>; 73*4882a593Smuzhiyun active-low; 74*4882a593Smuzhiyun color = <LED_COLOR_ID_GREEN>; 75*4882a593Smuzhiyun max-brightness = <255>; 76*4882a593Smuzhiyun label = "d3"; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun led-d4 { 80*4882a593Smuzhiyun pwms = <&pwm0 3 7812500 PWM_POLARITY_INVERTED>; 81*4882a593Smuzhiyun active-low; 82*4882a593Smuzhiyun color = <LED_COLOR_ID_GREEN>; 83*4882a593Smuzhiyun max-brightness = <255>; 84*4882a593Smuzhiyun label = "d4"; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun&uart0 { 90*4882a593Smuzhiyun status = "okay"; 91*4882a593Smuzhiyun}; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun&uart1 { 94*4882a593Smuzhiyun status = "okay"; 95*4882a593Smuzhiyun}; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun&i2c0 { 98*4882a593Smuzhiyun status = "okay"; 99*4882a593Smuzhiyun}; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun&qspi0 { 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun flash@0 { 104*4882a593Smuzhiyun compatible = "issi,is25wp256", "jedec,spi-nor"; 105*4882a593Smuzhiyun reg = <0>; 106*4882a593Smuzhiyun spi-max-frequency = <50000000>; 107*4882a593Smuzhiyun m25p,fast-read; 108*4882a593Smuzhiyun spi-tx-bus-width = <4>; 109*4882a593Smuzhiyun spi-rx-bus-width = <4>; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun&qspi2 { 114*4882a593Smuzhiyun status = "okay"; 115*4882a593Smuzhiyun mmc@0 { 116*4882a593Smuzhiyun compatible = "mmc-spi-slot"; 117*4882a593Smuzhiyun reg = <0>; 118*4882a593Smuzhiyun spi-max-frequency = <20000000>; 119*4882a593Smuzhiyun voltage-ranges = <3300 3300>; 120*4882a593Smuzhiyun disable-wp; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun}; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyunð0 { 125*4882a593Smuzhiyun status = "okay"; 126*4882a593Smuzhiyun phy-mode = "gmii"; 127*4882a593Smuzhiyun phy-handle = <&phy0>; 128*4882a593Smuzhiyun phy0: ethernet-phy@0 { 129*4882a593Smuzhiyun compatible = "ethernet-phy-id0007.0771"; 130*4882a593Smuzhiyun reg = <0>; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun}; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun&pwm0 { 135*4882a593Smuzhiyun status = "okay"; 136*4882a593Smuzhiyun}; 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun&pwm1 { 139*4882a593Smuzhiyun status = "okay"; 140*4882a593Smuzhiyun}; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&gpio { 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun}; 145