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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/net/
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
26 qca,clk-out-strength:
31 qca,keep-pll-enabled:
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/OK3568_Linux_fs/kernel/drivers/clk/meson/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0
11 * In the most basic form, a Meson PLL is composed as follows:
13 * PLL
14 * +--------------------------------+
16 * | +--+ |
17 * in >>-----[ /N ]--->| | +-----+ |
18 * | | |------| DCO |---->> out
19 * | +--------->| | +--v--+ |
20 * | | +--+ | |
22 * | +--[ *(M + (F/Fmax) ]<--+ |
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/OK3568_Linux_fs/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
20 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
22 * completely would just make things worse. We try to keep them as separate
115 if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) in serdes_lane_enabled()
125 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); in serdes_lane_enabled()
128 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); in serdes_lane_enabled()
135 /* Is serdes enabled at all? */ in is_serdes_configured()
136 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) in is_serdes_configured()
154 return -ENODEV; in __serdes_get_first_lane()
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/OK3568_Linux_fs/kernel/drivers/net/phy/
H A Dat803x.c1 // SPDX-License-Identifier: GPL-2.0+
22 #include <dt-bindings/net/qca-ar803x.h>
86 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
99 /* AT803x supports either the XTAL input pad, an internal PLL or the
101 * is only used for 25 MHz output, all other frequencies need the PLL.
105 * By default the PLL is only enabled if there is a link. Otherwise
106 * the PHY will go into low power state and disabled the PLL. You can
107 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
108 * enabled.
122 * but doesn't support choosing between XTAL/PLL and DSP.
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28-var4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
12 /dts-v1/;
13 #include "fsl-ls1028a-kontron-sl28.dts"
14 #include <dt-bindings/net/qca-ar803x.h>
17 model = "Kontron SMARC-sAL28 (Dual PHY)";
18 compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
22 phy-handle = <&phy1>;
23 phy-connection-type = "rgmii-id";
27 #address-cells = <1>;
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/
H A Dtc358768.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com
26 /* Global (16-bit addressable) */
43 /* Debug (16-bit addressable) */
49 /* TX PHY (32-bit addressable) */
61 /* TX PPI (32-bit addressable) */
77 /* TX CTRL (32-bit addressable) */
98 /* DSITX CTRL (16-bit addressable) */
141 int enabled; member
151 /* Parameters for PLL programming */
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/OK3568_Linux_fs/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c2 * Copyright (C) 2015-2016 Marvell International Ltd.
4 * SPDX-License-Identifier: GPL-2.0+
36 /*-----------------------------------------------------------*/
114 for (; timeout > 0; timeout--) { in comphy_poll_reg()
133 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
142 * 1. Enable max PLL. in comphy_pcie_power_up()
182 * 8. Check crystal jumper setting and program the Power and PLL in comphy_pcie_power_up()
194 * 9. Override Speed_PLL value and use MAC PLL in comphy_pcie_power_up()
219 /* Wait for > 55 us to allow PCLK be enabled */ in comphy_pcie_power_up()
222 /* Assert PCLK enabled */ in comphy_pcie_power_up()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Dradeon_legacy_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
40 struct drm_device *dev = crtc->dev; in radeon_overscan_setup()
41 struct radeon_device *rdev = dev->dev_private; in radeon_overscan_setup()
44 WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
45 WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
46 WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0); in radeon_overscan_setup()
52 struct drm_device *dev = crtc->dev; in radeon_legacy_rmx_mode_set()
53 struct radeon_device *rdev = dev->dev_private; in radeon_legacy_rmx_mode_set()
55 int xres = mode->hdisplay; in radeon_legacy_rmx_mode_set()
56 int yres = mode->vdisplay; in radeon_legacy_rmx_mode_set()
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/OK3568_Linux_fs/u-boot/arch/arm/mach-mvebu/
H A Dcpu.c2 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
42 writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask); in reset_cpu()
43 writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst); in reset_cpu()
142 val = readl(CONFIG_SAR2_REG); /* SAR - Sample At Reset */ in get_sar_freq()
144 val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ in get_sar_freq()
178 *sar_freq = sar_freq_tab[i - 1]; in get_sar_freq()
191 puts("MV78230-"); in print_cpuinfo()
194 puts("MV78260-"); in print_cpuinfo()
197 puts("MV78460-"); in print_cpuinfo()
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/OK3568_Linux_fs/kernel/drivers/phy/broadcom/
H A Dphy-brcm-usb-init.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * phy-brcm-usb-init.c - Broadcom USB Phy chip specific init functions
5 * Copyright (C) 2014-2017 Broadcom
16 #include "phy-brcm-usb-init.h"
133 (params->usb_reg_bits_map[USB_CTRL_##reg##_##field##_SELECTOR])
403 mask = params->usb_reg_bits_map[field]; in usb_ctrl_unset_family()
404 brcm_usb_ctrl_unset(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_unset_family()
413 mask = params->usb_reg_bits_map[field]; in usb_ctrl_set_family()
414 brcm_usb_ctrl_set(params->regs[BRCM_REGS_CTRL] + reg_offset, mask); in usb_ctrl_set_family()
460 /* reset USB 2.0 PLL */ in brcmusb_usb_phy_ldo_fix()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
47 (clk_mgr->regs->reg)
51 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
68 /* ClocksStateInvalid - should not be used */
70 /* ClocksStateUltraLow - not expected to be used for DCE 8.0 */
88 * (did - DENTIST_BASE_DID_1); in dentist_get_divider_from_did()
91 * (did - DENTIST_BASE_DID_2); in dentist_get_divider_from_did()
94 * (did - DENTIST_BASE_DID_3); in dentist_get_divider_from_did()
97 * (did - DENTIST_BASE_DID_4); in dentist_get_divider_from_did()
104 -if SS enabled on DP Ref clock and HW de-spreading enabled with SW
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/OK3568_Linux_fs/kernel/drivers/net/wireless/rockchip_wlan/rkwifi/bcmdhd/include/
H A Dbcmdevs.h2 * Broadcom device-specific manifest constants.
21 * <<Broadcom-WL-IPTag/Dual:>>
45 /* BLAZAR_BRANCH_101_10_DHD_001/build/dhd/linux-fc19/brix-brcm */
270 BCM43012Variants,package,ballmap,floorplan-PackageOptions
288 #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
289 #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
292 #define BFL_LTECOEX 0x00000200 /* LTE Coex enabled */
310 /* BFL_FASTPWR and BFL_UCPWRCTL_MININDX are non-overlaping features and use the same bit */
324 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
330 #define BFL2_WLCX_ATLAS 0x00000040 /* Board flag to initialize ECI for WLCX on FL-ATLAS */
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/OK3568_Linux_fs/external/rkwifibt/drivers/bcmdhd/include/
H A Dbcmdevs.h2 * Broadcom device-specific manifest constants.
21 * <<Broadcom-WL-IPTag/Dual:>>
45 /* BLAZAR_BRANCH_101_10_DHD_001/build/dhd/linux-fc19/brix-brcm */
270 BCM43012Variants,package,ballmap,floorplan-PackageOptions
288 #define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
289 #define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
292 #define BFL_LTECOEX 0x00000200 /* LTE Coex enabled */
310 /* BFL_FASTPWR and BFL_UCPWRCTL_MININDX are non-overlaping features and use the same bit */
324 #define BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
330 #define BFL2_WLCX_ATLAS 0x00000040 /* Board flag to initialize ECI for WLCX on FL-ATLAS */
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/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43/
H A Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
212 #define B43_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
234 #define B43_SHM_AUTOINC_R 0x0200 /* Auto-increment address on read */
235 #define B43_SHM_AUTOINC_W 0x0100 /* Auto-increment address on write */
330 #define B43_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_display.c2 * Copyright © 2006-2007 Intel Corporation
29 #include <linux/intel-iommu.h>
32 #include <linux/dma-resv.h>
208 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
222 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
223 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
225 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
237 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
240 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
241 dev_priv->czclk_freq); in intel_update_czclk()
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/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-mlxbf.c1 // SPDX-License-Identifier: GPL-2.0
54 * Note that the following SMBus, CAUSE, GPIO and PLL register addresses
56 * memory-mapped region whose addresses are specified in either the DT or
66 /* Reference clock for Bluefield - 156 MHz. */
69 /* Constant used to determine the PLL frequency. */
74 /* PLL registers. */
87 * as interrupt enabled bits.
124 * as interrupt enabled bits.
152 * SMBUS GW0 -> bits[26:25]
153 * SMBUS GW1 -> bits[28:27]
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/OK3568_Linux_fs/kernel/include/linux/bcma/
H A Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
33 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
48 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
102 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
104 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
153 #define BCMA_CC_FLASHCTL_ST_DP 0x00b9 /* Deep Power-down */
155 #define BCMA_CC_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
156 #define BCMA_CC_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
234 #define BCMA_CC_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled…
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/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dmain.h48 * Usage example, e.g. a three-bit field (bits 4-6):
52 * regval = R_REG(osh, &regs->regfoo);
55 * W_REG(osh, &regs->regfoo, regval);
58 (((unsigned)1 << (width)) - 1)
67 /* max # supported core revisions (0 .. MAXCOREREV - 1) */
70 /* Double check that unsupported cores are not enabled */
76 #define BRCMS_SHORTSLOT_AUTO -1 /* Driver will manage Shortslot setting */
91 #define TXFID_QUEUE_MASK 0x0007 /* Bits 0-2 */
92 #define TXFID_SEQ_MASK 0x7FE0 /* Bits 5-15 */
132 /* PLL requests */
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/rcar-du/
H A Drcar_lvds.c1 // SPDX-License-Identifier: GPL-2.0
3 * rcar_lvds.c -- R-Car LVDS Encoder
5 * Copyright (C) 2013-2018 Renesas Electronics Corporation
34 /* Keep in sync with the LVDCR0.LVMD hardware register values. */
50 #define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
51 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
88 iowrite32(data, lvds->mmio + reg); in rcar_lvds_write()
91 /* -----------------------------------------------------------------------------
99 return drm_panel_get_modes(lvds->panel, connector); in rcar_lvds_connector_get_modes()
111 if (!conn_state->crtc) in rcar_lvds_connector_atomic_check()
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/OK3568_Linux_fs/kernel/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
25 /* helpers to keep the MCLK intermediates "somewhere" in our table */
88 * NFC IP block, output clocks, system PLL status query, different CPMF
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
296 /* get the SPMF and translate it into the "sys pll" multiplier */
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
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/OK3568_Linux_fs/kernel/include/linux/ssb/
H A Dssb_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
37 #define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
161 …e SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
163 …CLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable reque…
260 /** PMU PLL registers */
262 /* PMU rev 0 PLL registers */
276 /* PMU rev 1 PLL registers */
308 /* BCM4312 PLL resource numbers. */
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
13 stdout-path = "serial0:115200n8";
19 * missing a unit-address. However, the bootloader on these Chromebook
21 * Adding the unit-address causes the bootloader to create a /memory
33 /delete-node/ memory@80000000;
39 vdd-supply = <&vdd_3v3_hdmi>;
40 pll-supply = <&vdd_hdmi_pll>;
41 hdmi-supply = <&vdd_5v0_hdmi>;
43 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
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/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c4 * SPDX-License-Identifier: GPL-2.0
73 /* Poll - Wait for Refresh operation completion */ in wait_refresh_op_complete()
83 * Args: target_freq - target frequency
85 * Returns: freq_par - the ratio parameter
96 /* Find the ratio between PLL frequency and ddr-clk */ in ddr3_get_freq_parameter()
109 * Args: freq - target frequency
111 * Returns: MV_OK - success, MV_FAIL - fail
120 DEBUG_DFS_C("DDR3 - DFS - High To Low - Starting DFS procedure to Frequency - ", in ddr3_dfs_high_2_low()
123 /* target frequency - 100MHz */ in ddr3_dfs_high_2_low()
132 /* Configure - DRAM DLL final state after DFS is complete - Enable */ in ddr3_dfs_high_2_low()
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/OK3568_Linux_fs/kernel/sound/soc/codecs/
H A Dda7219-aad.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * da7219-aad.c - Dialog DA7219 ALSA SoC AAD Driver
24 #include "da7219-aad.h"
35 da7219->aad->jack = jack; in da7219_aad_jack_det()
36 da7219->aad->jack_inserted = false; in da7219_aad_jack_det()
56 struct snd_soc_component *component = da7219_aad->component; in da7219_aad_btn_det_work()
84 dev_warn(component->dev, "Mic bias status check timed out"); in da7219_aad_btn_det_work()
86 da7219->micbias_on_event = true; in da7219_aad_btn_det_work()
92 if (da7219_aad->micbias_pulse_lvl && da7219_aad->micbias_pulse_time) { in da7219_aad_btn_det_work()
97 da7219_aad->micbias_pulse_lvl); in da7219_aad_btn_det_work()
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/OK3568_Linux_fs/kernel/drivers/net/wireless/broadcom/b43legacy/
H A Db43legacy.h1 /* SPDX-License-Identifier: GPL-2.0 */
59 /* 32-bit DMA */
66 /* 64-bit DMA */
119 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
120 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
153 #define B43legacy_SHM_SH_SPUWKUP 0x0094 /* pre-wakeup for synth PU in us */
154 #define B43legacy_SHM_SH_PRETBTT 0x0096 /* pre-TBTT in us */
163 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
164 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
192 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
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