Home
last modified time | relevance | path

Searched full:hart (Results 1 – 25 of 55) sorted by relevance

123

/OK3568_Linux_fs/kernel/arch/riscv/kernel/
H A Dcpu.c12 * Returns the hart ID of the given device tree node, or -ENODEV if the node
13 * isn't an enabled and valid RISC-V hart node.
18 u32 hart; in riscv_of_processor_hartid() local
25 if (of_property_read_u32(node, "reg", &hart)) { in riscv_of_processor_hartid()
26 pr_warn("Found CPU without hart ID\n"); in riscv_of_processor_hartid()
31 pr_info("CPU with hartid=%d is not available\n", hart); in riscv_of_processor_hartid()
36 pr_warn("CPU with hartid=%d has no \"riscv,isa\" property\n", hart); in riscv_of_processor_hartid()
40 pr_warn("CPU with hartid=%d has an invalid ISA of \"%s\"\n", hart, isa); in riscv_of_processor_hartid()
44 return hart; in riscv_of_processor_hartid()
48 * Find hart ID of the CPU DT node under which given DT node falls.
[all …]
H A Dsmpboot.c70 int hart; in setup_smp() local
77 hart = riscv_of_processor_hartid(dn); in setup_smp()
78 if (hart < 0) in setup_smp()
81 if (hart == cpuid_to_hartid_map(0)) { in setup_smp()
88 cpuid, hart); in setup_smp()
92 cpuid_to_hartid_map(cpuid) = hart; in setup_smp()
H A Dhead.S180 /* We lack SMP support or have too many harts, so park this hart */
241 /* Pick one hart to run the main boot sequence */
257 /* Save hart ID and DTB physical address */
299 * This hart didn't win the lottery, so we wait for the winning hart to
H A Dsys_riscv.c49 * kernel might schedule a process on another hart. There is no way for
51 * thread->hart mappings), so we've defined a RISC-V specific system call to
H A Dcpufeature.c113 * All "okay" hart should have same isa. Set HWCAP based on in riscv_fill_hwcap()
114 * common capabilities of every "okay" hart, in case they don't in riscv_fill_hwcap()
/OK3568_Linux_fs/kernel/arch/riscv/mm/
H A Dcacheflush.c33 * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
36 * execution resumes on each hart.
45 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm()
48 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm()
62 * performed on this hart between setting a hart's cpumask bit in flush_icache_mm()
63 * and scheduling this MM context on that hart. Sending an SBI in flush_icache_mm()
65 * messages are sent we still need to order this hart's writes in flush_icache_mm()
H A Dcontext.c17 * behavior in a common case (a bunch of single-hart processes on a many-hart
20 * cache flush to be performed before execution resumes on each hart. This
22 * refers to the current hart.
33 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/interrupt-controller/
H A Driscv,cpu-intc.txt1 RISC-V Hart-Level Interrupt Controller (HLIC)
5 CPU core (HART in RISC-V terminology) and can be read or written by software.
7 Every interrupt is ultimately routed through a hart's HLIC before it
8 interrupts that hart.
40 definition of the hart whose CSRs control these local interrupts.
H A Dsifive,plic-1.0.0.yaml14 hart contexts in the system, via the external interrupt source in each hart.
16 A hart context is a privilege mode in a hardware execution thread. For example,
18 privilege modes per hart; machine mode and supervisor mode.
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/riscv/
H A Dcpus.yaml17 hart: A hardware execution context, which contains all the state
39 Identifies that the hart uses the RISC-V instruction set
40 and identifies the type of the hart.
45 hart. These values originate from the RISC-V Privileged
57 supported by the hart. These are documented in the RISC-V
145 // Example 2: Spike ISA Simulator with 1 Hart
/OK3568_Linux_fs/kernel/drivers/irqchip/
H A Dirq-riscv-intc.c48 * on the local hart, these functions can only be called on the hart that
102 pr_warn("unable to find hart id for %pOF\n", node); in riscv_intc_init()
107 * The DT will have one INTC DT node under each CPU (or HART) in riscv_intc_init()
110 * for the INTC DT node belonging to boot CPU (or boot HART). in riscv_intc_init()
H A Dirq-sifive-plic.c44 * Each hart context has a vector of interrupt enable bits associated with it.
51 * Each hart context has a set of control registers associated with it. Right
52 * now there's only two: a source priority threshold over which the hart will
334 pr_warn("failed to parse hart ID for context %d.\n", i); in plic_init()
H A DKconfig522 This enables support for the per-HART local interrupt controller
523 found in standard RISC-V systems. The per-HART local interrupt
525 hardware interrupts. Without a per-HART local interrupt controller,
/OK3568_Linux_fs/kernel/arch/csky/abiv2/
H A Dcacheflush.c40 * Ensure the remote hart's writes are visible to this hart. in flush_icache_deferred()
64 /* Mark every hart's icache as needing a flush for this MM. */ in flush_icache_mm_range()
68 /* Flush this hart's I$ now, and mark it as flushed. */ in flush_icache_mm_range()
/OK3568_Linux_fs/kernel/tools/testing/selftests/futex/
H A Drun.sh13 # Darren Hart <dvhart@linux.intel.com>
16 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
/OK3568_Linux_fs/kernel/arch/riscv/include/uapi/asm/
H A Dunistd.h31 * kernel might schedule a process on another hart. There is no way for
33 * thread->hart mappings), so we've defined a RISC-V specific system call to
/OK3568_Linux_fs/kernel/tools/arch/riscv/include/uapi/asm/
H A Dunistd.h29 * kernel might schedule a process on another hart. There is no way for
31 * thread->hart mappings), so we've defined a RISC-V specific system call to
/OK3568_Linux_fs/kernel/tools/testing/selftests/futex/functional/
H A Drun.sh12 # Darren Hart <dvhart@linux.intel.com>
15 # 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
H A Dfutex_wait_timeout.c10 * Darren Hart <dvhart@linux.intel.com>
13 * 2009-Nov-6: Initial version by Darren Hart <dvhart@linux.intel.com>
H A Dfutex_requeue_pi_mismatched_ops.c12 * Darren Hart <dvhart@linux.intel.com>
15 * 2009-Nov-9: Initial version by Darren Hart <dvhart@linux.intel.com>
H A Dfutex_requeue_pi_signal_restart.c12 * Darren Hart <dvhart@linux.intel.com>
15 * 2008-May-5: Initial version by Darren Hart <dvhart@linux.intel.com>
/OK3568_Linux_fs/kernel/arch/riscv/include/asm/
H A Dsmp.h54 /* Secondary hart entry */
58 * Obtains the hart ID of the currently executing task. This relies on
H A Dbarrier.h64 * task is marked as available for scheduling on a new hart. While I don't see
68 * the new hart.
/OK3568_Linux_fs/kernel/tools/testing/selftests/futex/include/
H A Datomic.h11 * Darren Hart <dvhart@linux.intel.com>
14 * 2009-Nov-17: Initial version by Darren Hart <dvhart@linux.intel.com>
H A Dlogging.h10 * Darren Hart <dvhart@linux.intel.com>
13 * 2009-Nov-6: Initial version by Darren Hart <dvhart@linux.intel.com>

123