1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 David Abdurachmanov <david.abdurachmanov@gmail.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 6*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 7*4882a593Smuzhiyun * published by the Free Software Foundation. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, 10*4882a593Smuzhiyun * but WITHOUT ANY WARRANTY; without even the implied warranty of 11*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12*4882a593Smuzhiyun * GNU General Public License for more details. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License 15*4882a593Smuzhiyun * along with this program. If not, see <https://www.gnu.org/licenses/>. 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifdef __LP64__ 19*4882a593Smuzhiyun #define __ARCH_WANT_NEW_STAT 20*4882a593Smuzhiyun #define __ARCH_WANT_SET_GET_RLIMIT 21*4882a593Smuzhiyun #endif /* __LP64__ */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define __ARCH_WANT_SYS_CLONE3 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #include <asm-generic/unistd.h> 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Allows the instruction cache to be flushed from userspace. Despite RISC-V 29*4882a593Smuzhiyun * having a direct 'fence.i' instruction available to userspace (which we 30*4882a593Smuzhiyun * can't trap!), that's not actually viable when running on Linux because the 31*4882a593Smuzhiyun * kernel might schedule a process on another hart. There is no way for 32*4882a593Smuzhiyun * userspace to handle this without invoking the kernel (as it doesn't know the 33*4882a593Smuzhiyun * thread->hart mappings), so we've defined a RISC-V specific system call to 34*4882a593Smuzhiyun * flush the instruction cache. 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * __NR_riscv_flush_icache is defined to flush the instruction cache over an 37*4882a593Smuzhiyun * address range, with the flush applying to either all threads or just the 38*4882a593Smuzhiyun * caller. We don't currently do anything with the address range, that's just 39*4882a593Smuzhiyun * in there for forwards compatibility. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #ifndef __NR_riscv_flush_icache 42*4882a593Smuzhiyun #define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15) 43*4882a593Smuzhiyun #endif 44*4882a593Smuzhiyun __SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache) 45