xref: /OK3568_Linux_fs/kernel/drivers/irqchip/Kconfig (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyunmenu "IRQ chip support"
3*4882a593Smuzhiyun
4*4882a593Smuzhiyunconfig IRQCHIP
5*4882a593Smuzhiyun	def_bool y
6*4882a593Smuzhiyun	depends on OF_IRQ
7*4882a593Smuzhiyun
8*4882a593Smuzhiyunconfig ARM_GIC
9*4882a593Smuzhiyun	bool
10*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
11*4882a593Smuzhiyun	select GENERIC_IRQ_MULTI_HANDLER
12*4882a593Smuzhiyun	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
13*4882a593Smuzhiyun
14*4882a593Smuzhiyunconfig ARM_GIC_PM
15*4882a593Smuzhiyun	bool
16*4882a593Smuzhiyun	depends on PM
17*4882a593Smuzhiyun	select ARM_GIC
18*4882a593Smuzhiyun
19*4882a593Smuzhiyunconfig ARM_GIC_MAX_NR
20*4882a593Smuzhiyun	int
21*4882a593Smuzhiyun	depends on ARM_GIC
22*4882a593Smuzhiyun	default 2 if ARCH_REALVIEW
23*4882a593Smuzhiyun	default 1
24*4882a593Smuzhiyun
25*4882a593Smuzhiyunconfig ARM_GIC_V2M
26*4882a593Smuzhiyun	bool
27*4882a593Smuzhiyun	depends on PCI
28*4882a593Smuzhiyun	select ARM_GIC
29*4882a593Smuzhiyun	select PCI_MSI
30*4882a593Smuzhiyun
31*4882a593Smuzhiyunconfig GIC_NON_BANKED
32*4882a593Smuzhiyun	bool
33*4882a593Smuzhiyun
34*4882a593Smuzhiyunconfig ARM_GIC_V3
35*4882a593Smuzhiyun	bool
36*4882a593Smuzhiyun	select GENERIC_IRQ_MULTI_HANDLER
37*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
38*4882a593Smuzhiyun	select PARTITION_PERCPU
39*4882a593Smuzhiyun	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
40*4882a593Smuzhiyun
41*4882a593Smuzhiyunconfig ARM_GIC_V3_ITS
42*4882a593Smuzhiyun	bool
43*4882a593Smuzhiyun	select GENERIC_MSI_IRQ_DOMAIN
44*4882a593Smuzhiyun	default ARM_GIC_V3
45*4882a593Smuzhiyun
46*4882a593Smuzhiyunconfig ARM_GIC_V3_ITS_PCI
47*4882a593Smuzhiyun	bool
48*4882a593Smuzhiyun	depends on ARM_GIC_V3_ITS
49*4882a593Smuzhiyun	depends on PCI
50*4882a593Smuzhiyun	depends on PCI_MSI
51*4882a593Smuzhiyun	default ARM_GIC_V3_ITS
52*4882a593Smuzhiyun
53*4882a593Smuzhiyunconfig ARM_GIC_V3_ITS_FSL_MC
54*4882a593Smuzhiyun	bool
55*4882a593Smuzhiyun	depends on ARM_GIC_V3_ITS
56*4882a593Smuzhiyun	depends on FSL_MC_BUS
57*4882a593Smuzhiyun	default ARM_GIC_V3_ITS
58*4882a593Smuzhiyun
59*4882a593Smuzhiyunconfig ARM_NVIC
60*4882a593Smuzhiyun	bool
61*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
62*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
63*4882a593Smuzhiyun
64*4882a593Smuzhiyunconfig ARM_VIC
65*4882a593Smuzhiyun	bool
66*4882a593Smuzhiyun	select IRQ_DOMAIN
67*4882a593Smuzhiyun	select GENERIC_IRQ_MULTI_HANDLER
68*4882a593Smuzhiyun
69*4882a593Smuzhiyunconfig ARM_VIC_NR
70*4882a593Smuzhiyun	int
71*4882a593Smuzhiyun	default 4 if ARCH_S5PV210
72*4882a593Smuzhiyun	default 2
73*4882a593Smuzhiyun	depends on ARM_VIC
74*4882a593Smuzhiyun	help
75*4882a593Smuzhiyun	  The maximum number of VICs available in the system, for
76*4882a593Smuzhiyun	  power management.
77*4882a593Smuzhiyun
78*4882a593Smuzhiyunconfig ARMADA_370_XP_IRQ
79*4882a593Smuzhiyun	bool
80*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
81*4882a593Smuzhiyun	select PCI_MSI if PCI
82*4882a593Smuzhiyun	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
83*4882a593Smuzhiyun
84*4882a593Smuzhiyunconfig ALPINE_MSI
85*4882a593Smuzhiyun	bool
86*4882a593Smuzhiyun	depends on PCI
87*4882a593Smuzhiyun	select PCI_MSI
88*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
89*4882a593Smuzhiyun
90*4882a593Smuzhiyunconfig AL_FIC
91*4882a593Smuzhiyun	bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
92*4882a593Smuzhiyun	depends on OF || COMPILE_TEST
93*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
94*4882a593Smuzhiyun	select IRQ_DOMAIN
95*4882a593Smuzhiyun	help
96*4882a593Smuzhiyun	  Support Amazon's Annapurna Labs Fabric Interrupt Controller.
97*4882a593Smuzhiyun
98*4882a593Smuzhiyunconfig ATMEL_AIC_IRQ
99*4882a593Smuzhiyun	bool
100*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
101*4882a593Smuzhiyun	select IRQ_DOMAIN
102*4882a593Smuzhiyun	select GENERIC_IRQ_MULTI_HANDLER
103*4882a593Smuzhiyun	select SPARSE_IRQ
104*4882a593Smuzhiyun
105*4882a593Smuzhiyunconfig ATMEL_AIC5_IRQ
106*4882a593Smuzhiyun	bool
107*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
108*4882a593Smuzhiyun	select IRQ_DOMAIN
109*4882a593Smuzhiyun	select GENERIC_IRQ_MULTI_HANDLER
110*4882a593Smuzhiyun	select SPARSE_IRQ
111*4882a593Smuzhiyun
112*4882a593Smuzhiyunconfig I8259
113*4882a593Smuzhiyun	bool
114*4882a593Smuzhiyun	select IRQ_DOMAIN
115*4882a593Smuzhiyun
116*4882a593Smuzhiyunconfig BCM6345_L1_IRQ
117*4882a593Smuzhiyun	bool
118*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
119*4882a593Smuzhiyun	select IRQ_DOMAIN
120*4882a593Smuzhiyun	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
121*4882a593Smuzhiyun
122*4882a593Smuzhiyunconfig BCM7038_L1_IRQ
123*4882a593Smuzhiyun	bool
124*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
125*4882a593Smuzhiyun	select IRQ_DOMAIN
126*4882a593Smuzhiyun	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
127*4882a593Smuzhiyun
128*4882a593Smuzhiyunconfig BCM7120_L2_IRQ
129*4882a593Smuzhiyun	bool
130*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
131*4882a593Smuzhiyun	select IRQ_DOMAIN
132*4882a593Smuzhiyun
133*4882a593Smuzhiyunconfig BRCMSTB_L2_IRQ
134*4882a593Smuzhiyun	bool
135*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
136*4882a593Smuzhiyun	select IRQ_DOMAIN
137*4882a593Smuzhiyun
138*4882a593Smuzhiyunconfig DAVINCI_AINTC
139*4882a593Smuzhiyun	bool
140*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
141*4882a593Smuzhiyun	select IRQ_DOMAIN
142*4882a593Smuzhiyun
143*4882a593Smuzhiyunconfig DAVINCI_CP_INTC
144*4882a593Smuzhiyun	bool
145*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
146*4882a593Smuzhiyun	select IRQ_DOMAIN
147*4882a593Smuzhiyun
148*4882a593Smuzhiyunconfig DW_APB_ICTL
149*4882a593Smuzhiyun	bool
150*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
151*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
152*4882a593Smuzhiyun
153*4882a593Smuzhiyunconfig FARADAY_FTINTC010
154*4882a593Smuzhiyun	bool
155*4882a593Smuzhiyun	select IRQ_DOMAIN
156*4882a593Smuzhiyun	select GENERIC_IRQ_MULTI_HANDLER
157*4882a593Smuzhiyun	select SPARSE_IRQ
158*4882a593Smuzhiyun
159*4882a593Smuzhiyunconfig HISILICON_IRQ_MBIGEN
160*4882a593Smuzhiyun	bool
161*4882a593Smuzhiyun	select ARM_GIC_V3
162*4882a593Smuzhiyun	select ARM_GIC_V3_ITS
163*4882a593Smuzhiyun
164*4882a593Smuzhiyunconfig IMGPDC_IRQ
165*4882a593Smuzhiyun	bool
166*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
167*4882a593Smuzhiyun	select IRQ_DOMAIN
168*4882a593Smuzhiyun
169*4882a593Smuzhiyunconfig IXP4XX_IRQ
170*4882a593Smuzhiyun	bool
171*4882a593Smuzhiyun	select IRQ_DOMAIN
172*4882a593Smuzhiyun	select GENERIC_IRQ_MULTI_HANDLER
173*4882a593Smuzhiyun	select SPARSE_IRQ
174*4882a593Smuzhiyun
175*4882a593Smuzhiyunconfig MADERA_IRQ
176*4882a593Smuzhiyun	tristate
177*4882a593Smuzhiyun
178*4882a593Smuzhiyunconfig IRQ_MIPS_CPU
179*4882a593Smuzhiyun	bool
180*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
181*4882a593Smuzhiyun	select GENERIC_IRQ_IPI if SMP && SYS_SUPPORTS_MULTITHREADING
182*4882a593Smuzhiyun	select IRQ_DOMAIN
183*4882a593Smuzhiyun	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
184*4882a593Smuzhiyun
185*4882a593Smuzhiyunconfig CLPS711X_IRQCHIP
186*4882a593Smuzhiyun	bool
187*4882a593Smuzhiyun	depends on ARCH_CLPS711X
188*4882a593Smuzhiyun	select IRQ_DOMAIN
189*4882a593Smuzhiyun	select GENERIC_IRQ_MULTI_HANDLER
190*4882a593Smuzhiyun	select SPARSE_IRQ
191*4882a593Smuzhiyun	default y
192*4882a593Smuzhiyun
193*4882a593Smuzhiyunconfig OMPIC
194*4882a593Smuzhiyun	bool
195*4882a593Smuzhiyun
196*4882a593Smuzhiyunconfig OR1K_PIC
197*4882a593Smuzhiyun	bool
198*4882a593Smuzhiyun	select IRQ_DOMAIN
199*4882a593Smuzhiyun
200*4882a593Smuzhiyunconfig OMAP_IRQCHIP
201*4882a593Smuzhiyun	bool
202*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
203*4882a593Smuzhiyun	select IRQ_DOMAIN
204*4882a593Smuzhiyun
205*4882a593Smuzhiyunconfig ORION_IRQCHIP
206*4882a593Smuzhiyun	bool
207*4882a593Smuzhiyun	select IRQ_DOMAIN
208*4882a593Smuzhiyun	select GENERIC_IRQ_MULTI_HANDLER
209*4882a593Smuzhiyun
210*4882a593Smuzhiyunconfig PIC32_EVIC
211*4882a593Smuzhiyun	bool
212*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
213*4882a593Smuzhiyun	select IRQ_DOMAIN
214*4882a593Smuzhiyun
215*4882a593Smuzhiyunconfig JCORE_AIC
216*4882a593Smuzhiyun	bool "J-Core integrated AIC" if COMPILE_TEST
217*4882a593Smuzhiyun	depends on OF
218*4882a593Smuzhiyun	select IRQ_DOMAIN
219*4882a593Smuzhiyun	help
220*4882a593Smuzhiyun	  Support for the J-Core integrated AIC.
221*4882a593Smuzhiyun
222*4882a593Smuzhiyunconfig RDA_INTC
223*4882a593Smuzhiyun	bool
224*4882a593Smuzhiyun	select IRQ_DOMAIN
225*4882a593Smuzhiyun
226*4882a593Smuzhiyunconfig RENESAS_INTC_IRQPIN
227*4882a593Smuzhiyun	bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
228*4882a593Smuzhiyun	select IRQ_DOMAIN
229*4882a593Smuzhiyun	help
230*4882a593Smuzhiyun	  Enable support for the Renesas Interrupt Controller for external
231*4882a593Smuzhiyun	  interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
232*4882a593Smuzhiyun
233*4882a593Smuzhiyunconfig RENESAS_IRQC
234*4882a593Smuzhiyun	bool "Renesas R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} IRQC support" if COMPILE_TEST
235*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
236*4882a593Smuzhiyun	select IRQ_DOMAIN
237*4882a593Smuzhiyun	help
238*4882a593Smuzhiyun	  Enable support for the Renesas Interrupt Controller for external
239*4882a593Smuzhiyun	  devices, as found on R-Mobile APE6, R-Car Gen{2,3} and RZ/G{1,2} SoCs.
240*4882a593Smuzhiyun
241*4882a593Smuzhiyunconfig RENESAS_RZA1_IRQC
242*4882a593Smuzhiyun	bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
243*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
244*4882a593Smuzhiyun	help
245*4882a593Smuzhiyun	  Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
246*4882a593Smuzhiyun	  to 8 external interrupts with configurable sense select.
247*4882a593Smuzhiyun
248*4882a593Smuzhiyunconfig SL28CPLD_INTC
249*4882a593Smuzhiyun	bool "Kontron sl28cpld IRQ controller"
250*4882a593Smuzhiyun	depends on MFD_SL28CPLD=y || COMPILE_TEST
251*4882a593Smuzhiyun	select REGMAP_IRQ
252*4882a593Smuzhiyun	help
253*4882a593Smuzhiyun	  Interrupt controller driver for the board management controller
254*4882a593Smuzhiyun	  found on the Kontron sl28 CPLD.
255*4882a593Smuzhiyun
256*4882a593Smuzhiyunconfig ST_IRQCHIP
257*4882a593Smuzhiyun	bool
258*4882a593Smuzhiyun	select REGMAP
259*4882a593Smuzhiyun	select MFD_SYSCON
260*4882a593Smuzhiyun	help
261*4882a593Smuzhiyun	  Enables SysCfg Controlled IRQs on STi based platforms.
262*4882a593Smuzhiyun
263*4882a593Smuzhiyunconfig TANGO_IRQ
264*4882a593Smuzhiyun	bool
265*4882a593Smuzhiyun	select IRQ_DOMAIN
266*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
267*4882a593Smuzhiyun
268*4882a593Smuzhiyunconfig TB10X_IRQC
269*4882a593Smuzhiyun	bool
270*4882a593Smuzhiyun	select IRQ_DOMAIN
271*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
272*4882a593Smuzhiyun
273*4882a593Smuzhiyunconfig TS4800_IRQ
274*4882a593Smuzhiyun	tristate "TS-4800 IRQ controller"
275*4882a593Smuzhiyun	select IRQ_DOMAIN
276*4882a593Smuzhiyun	depends on HAS_IOMEM
277*4882a593Smuzhiyun	depends on SOC_IMX51 || COMPILE_TEST
278*4882a593Smuzhiyun	help
279*4882a593Smuzhiyun	  Support for the TS-4800 FPGA IRQ controller
280*4882a593Smuzhiyun
281*4882a593Smuzhiyunconfig VERSATILE_FPGA_IRQ
282*4882a593Smuzhiyun	bool
283*4882a593Smuzhiyun	select IRQ_DOMAIN
284*4882a593Smuzhiyun
285*4882a593Smuzhiyunconfig VERSATILE_FPGA_IRQ_NR
286*4882a593Smuzhiyun       int
287*4882a593Smuzhiyun       default 4
288*4882a593Smuzhiyun       depends on VERSATILE_FPGA_IRQ
289*4882a593Smuzhiyun
290*4882a593Smuzhiyunconfig XTENSA_MX
291*4882a593Smuzhiyun	bool
292*4882a593Smuzhiyun	select IRQ_DOMAIN
293*4882a593Smuzhiyun	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
294*4882a593Smuzhiyun
295*4882a593Smuzhiyunconfig XILINX_INTC
296*4882a593Smuzhiyun	bool
297*4882a593Smuzhiyun	select IRQ_DOMAIN
298*4882a593Smuzhiyun
299*4882a593Smuzhiyunconfig IRQ_CROSSBAR
300*4882a593Smuzhiyun	bool
301*4882a593Smuzhiyun	help
302*4882a593Smuzhiyun	  Support for a CROSSBAR ip that precedes the main interrupt controller.
303*4882a593Smuzhiyun	  The primary irqchip invokes the crossbar's callback which inturn allocates
304*4882a593Smuzhiyun	  a free irq and configures the IP. Thus the peripheral interrupts are
305*4882a593Smuzhiyun	  routed to one of the free irqchip interrupt lines.
306*4882a593Smuzhiyun
307*4882a593Smuzhiyunconfig KEYSTONE_IRQ
308*4882a593Smuzhiyun	tristate "Keystone 2 IRQ controller IP"
309*4882a593Smuzhiyun	depends on ARCH_KEYSTONE
310*4882a593Smuzhiyun	help
311*4882a593Smuzhiyun		Support for Texas Instruments Keystone 2 IRQ controller IP which
312*4882a593Smuzhiyun		is part of the Keystone 2 IPC mechanism
313*4882a593Smuzhiyun
314*4882a593Smuzhiyunconfig MIPS_GIC
315*4882a593Smuzhiyun	bool
316*4882a593Smuzhiyun	select GENERIC_IRQ_IPI if SMP
317*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
318*4882a593Smuzhiyun	select MIPS_CM
319*4882a593Smuzhiyun
320*4882a593Smuzhiyunconfig INGENIC_IRQ
321*4882a593Smuzhiyun	bool
322*4882a593Smuzhiyun	depends on MACH_INGENIC
323*4882a593Smuzhiyun	default y
324*4882a593Smuzhiyun
325*4882a593Smuzhiyunconfig INGENIC_TCU_IRQ
326*4882a593Smuzhiyun	bool "Ingenic JZ47xx TCU interrupt controller"
327*4882a593Smuzhiyun	default MACH_INGENIC
328*4882a593Smuzhiyun	depends on MIPS || COMPILE_TEST
329*4882a593Smuzhiyun	select MFD_SYSCON
330*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
331*4882a593Smuzhiyun	help
332*4882a593Smuzhiyun	  Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
333*4882a593Smuzhiyun	  JZ47xx SoCs.
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun	  If unsure, say N.
336*4882a593Smuzhiyun
337*4882a593Smuzhiyunconfig RENESAS_H8300H_INTC
338*4882a593Smuzhiyun        bool
339*4882a593Smuzhiyun	select IRQ_DOMAIN
340*4882a593Smuzhiyun
341*4882a593Smuzhiyunconfig RENESAS_H8S_INTC
342*4882a593Smuzhiyun	bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
343*4882a593Smuzhiyun	select IRQ_DOMAIN
344*4882a593Smuzhiyun	help
345*4882a593Smuzhiyun	  Enable support for the Renesas H8/300 Interrupt Controller, as found
346*4882a593Smuzhiyun	  on Renesas H8S SoCs.
347*4882a593Smuzhiyun
348*4882a593Smuzhiyunconfig IMX_GPCV2
349*4882a593Smuzhiyun	bool
350*4882a593Smuzhiyun	select IRQ_DOMAIN
351*4882a593Smuzhiyun	help
352*4882a593Smuzhiyun	  Enables the wakeup IRQs for IMX platforms with GPCv2 block
353*4882a593Smuzhiyun
354*4882a593Smuzhiyunconfig IRQ_MXS
355*4882a593Smuzhiyun	def_bool y if MACH_ASM9260 || ARCH_MXS
356*4882a593Smuzhiyun	select IRQ_DOMAIN
357*4882a593Smuzhiyun	select STMP_DEVICE
358*4882a593Smuzhiyun
359*4882a593Smuzhiyunconfig MSCC_OCELOT_IRQ
360*4882a593Smuzhiyun	bool
361*4882a593Smuzhiyun	select IRQ_DOMAIN
362*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
363*4882a593Smuzhiyun
364*4882a593Smuzhiyunconfig MVEBU_GICP
365*4882a593Smuzhiyun	bool
366*4882a593Smuzhiyun
367*4882a593Smuzhiyunconfig MVEBU_ICU
368*4882a593Smuzhiyun	bool
369*4882a593Smuzhiyun
370*4882a593Smuzhiyunconfig MVEBU_ODMI
371*4882a593Smuzhiyun	bool
372*4882a593Smuzhiyun	select GENERIC_MSI_IRQ_DOMAIN
373*4882a593Smuzhiyun
374*4882a593Smuzhiyunconfig MVEBU_PIC
375*4882a593Smuzhiyun	bool
376*4882a593Smuzhiyun
377*4882a593Smuzhiyunconfig MVEBU_SEI
378*4882a593Smuzhiyun        bool
379*4882a593Smuzhiyun
380*4882a593Smuzhiyunconfig LS_EXTIRQ
381*4882a593Smuzhiyun	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
382*4882a593Smuzhiyun	select MFD_SYSCON
383*4882a593Smuzhiyun
384*4882a593Smuzhiyunconfig LS_SCFG_MSI
385*4882a593Smuzhiyun	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
386*4882a593Smuzhiyun	depends on PCI && PCI_MSI
387*4882a593Smuzhiyun
388*4882a593Smuzhiyunconfig PARTITION_PERCPU
389*4882a593Smuzhiyun	bool
390*4882a593Smuzhiyun
391*4882a593Smuzhiyunconfig EZNPS_GIC
392*4882a593Smuzhiyun	bool "NPS400 Global Interrupt Manager (GIM)"
393*4882a593Smuzhiyun	depends on ARC || (COMPILE_TEST && !64BIT)
394*4882a593Smuzhiyun	select IRQ_DOMAIN
395*4882a593Smuzhiyun	help
396*4882a593Smuzhiyun	  Support the EZchip NPS400 global interrupt controller
397*4882a593Smuzhiyun
398*4882a593Smuzhiyunconfig STM32_EXTI
399*4882a593Smuzhiyun	bool
400*4882a593Smuzhiyun	select IRQ_DOMAIN
401*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
402*4882a593Smuzhiyun
403*4882a593Smuzhiyunconfig QCOM_IRQ_COMBINER
404*4882a593Smuzhiyun	bool "QCOM IRQ combiner support"
405*4882a593Smuzhiyun	depends on ARCH_QCOM && ACPI
406*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
407*4882a593Smuzhiyun	help
408*4882a593Smuzhiyun	  Say yes here to add support for the IRQ combiner devices embedded
409*4882a593Smuzhiyun	  in Qualcomm Technologies chips.
410*4882a593Smuzhiyun
411*4882a593Smuzhiyunconfig IRQ_UNIPHIER_AIDET
412*4882a593Smuzhiyun	bool "UniPhier AIDET support" if COMPILE_TEST
413*4882a593Smuzhiyun	depends on ARCH_UNIPHIER || COMPILE_TEST
414*4882a593Smuzhiyun	default ARCH_UNIPHIER
415*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
416*4882a593Smuzhiyun	help
417*4882a593Smuzhiyun	  Support for the UniPhier AIDET (ARM Interrupt Detector).
418*4882a593Smuzhiyun
419*4882a593Smuzhiyunconfig MESON_IRQ_GPIO
420*4882a593Smuzhiyun       tristate "Meson GPIO Interrupt Multiplexer"
421*4882a593Smuzhiyun       depends on ARCH_MESON || COMPILE_TEST
422*4882a593Smuzhiyun       default ARCH_MESON
423*4882a593Smuzhiyun       select IRQ_DOMAIN_HIERARCHY
424*4882a593Smuzhiyun       help
425*4882a593Smuzhiyun         Support Meson SoC Family GPIO Interrupt Multiplexer
426*4882a593Smuzhiyun
427*4882a593Smuzhiyunconfig GOLDFISH_PIC
428*4882a593Smuzhiyun       bool "Goldfish programmable interrupt controller"
429*4882a593Smuzhiyun       depends on MIPS && (GOLDFISH || COMPILE_TEST)
430*4882a593Smuzhiyun       select GENERIC_IRQ_CHIP
431*4882a593Smuzhiyun       select IRQ_DOMAIN
432*4882a593Smuzhiyun       help
433*4882a593Smuzhiyun         Say yes here to enable Goldfish interrupt controller driver used
434*4882a593Smuzhiyun         for Goldfish based virtual platforms.
435*4882a593Smuzhiyun
436*4882a593Smuzhiyunconfig QCOM_PDC
437*4882a593Smuzhiyun	tristate "QCOM PDC"
438*4882a593Smuzhiyun	depends on ARCH_QCOM
439*4882a593Smuzhiyun	depends on QCOM_SCM || !QCOM_SCM
440*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
441*4882a593Smuzhiyun	help
442*4882a593Smuzhiyun	  Power Domain Controller driver to manage and configure wakeup
443*4882a593Smuzhiyun	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
444*4882a593Smuzhiyun
445*4882a593Smuzhiyunconfig CSKY_MPINTC
446*4882a593Smuzhiyun	bool "C-SKY Multi Processor Interrupt Controller"
447*4882a593Smuzhiyun	depends on CSKY
448*4882a593Smuzhiyun	help
449*4882a593Smuzhiyun	  Say yes here to enable C-SKY SMP interrupt controller driver used
450*4882a593Smuzhiyun	  for C-SKY SMP system.
451*4882a593Smuzhiyun	  In fact it's not mmio map in hardware and it uses ld/st to visit the
452*4882a593Smuzhiyun	  controller's register inside CPU.
453*4882a593Smuzhiyun
454*4882a593Smuzhiyunconfig CSKY_APB_INTC
455*4882a593Smuzhiyun	bool "C-SKY APB Interrupt Controller"
456*4882a593Smuzhiyun	depends on CSKY
457*4882a593Smuzhiyun	help
458*4882a593Smuzhiyun	  Say yes here to enable C-SKY APB interrupt controller driver used
459*4882a593Smuzhiyun	  by C-SKY single core SOC system. It uses mmio map apb-bus to visit
460*4882a593Smuzhiyun	  the controller's register.
461*4882a593Smuzhiyun
462*4882a593Smuzhiyunconfig IMX_IRQSTEER
463*4882a593Smuzhiyun	bool "i.MX IRQSTEER support"
464*4882a593Smuzhiyun	depends on ARCH_MXC || COMPILE_TEST
465*4882a593Smuzhiyun	default ARCH_MXC
466*4882a593Smuzhiyun	select IRQ_DOMAIN
467*4882a593Smuzhiyun	help
468*4882a593Smuzhiyun	  Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
469*4882a593Smuzhiyun
470*4882a593Smuzhiyunconfig IMX_INTMUX
471*4882a593Smuzhiyun	bool "i.MX INTMUX support" if COMPILE_TEST
472*4882a593Smuzhiyun	default y if ARCH_MXC
473*4882a593Smuzhiyun	select IRQ_DOMAIN
474*4882a593Smuzhiyun	help
475*4882a593Smuzhiyun	  Support for the i.MX INTMUX interrupt multiplexer.
476*4882a593Smuzhiyun
477*4882a593Smuzhiyunconfig LS1X_IRQ
478*4882a593Smuzhiyun	bool "Loongson-1 Interrupt Controller"
479*4882a593Smuzhiyun	depends on MACH_LOONGSON32
480*4882a593Smuzhiyun	default y
481*4882a593Smuzhiyun	select IRQ_DOMAIN
482*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
483*4882a593Smuzhiyun	help
484*4882a593Smuzhiyun	  Support for the Loongson-1 platform Interrupt Controller.
485*4882a593Smuzhiyun
486*4882a593Smuzhiyunconfig TI_SCI_INTR_IRQCHIP
487*4882a593Smuzhiyun	bool
488*4882a593Smuzhiyun	depends on TI_SCI_PROTOCOL
489*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
490*4882a593Smuzhiyun	help
491*4882a593Smuzhiyun	  This enables the irqchip driver support for K3 Interrupt router
492*4882a593Smuzhiyun	  over TI System Control Interface available on some new TI's SoCs.
493*4882a593Smuzhiyun	  If you wish to use interrupt router irq resources managed by the
494*4882a593Smuzhiyun	  TI System Controller, say Y here. Otherwise, say N.
495*4882a593Smuzhiyun
496*4882a593Smuzhiyunconfig TI_SCI_INTA_IRQCHIP
497*4882a593Smuzhiyun	bool
498*4882a593Smuzhiyun	depends on TI_SCI_PROTOCOL
499*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
500*4882a593Smuzhiyun	select TI_SCI_INTA_MSI_DOMAIN
501*4882a593Smuzhiyun	help
502*4882a593Smuzhiyun	  This enables the irqchip driver support for K3 Interrupt aggregator
503*4882a593Smuzhiyun	  over TI System Control Interface available on some new TI's SoCs.
504*4882a593Smuzhiyun	  If you wish to use interrupt aggregator irq resources managed by the
505*4882a593Smuzhiyun	  TI System Controller, say Y here. Otherwise, say N.
506*4882a593Smuzhiyun
507*4882a593Smuzhiyunconfig TI_PRUSS_INTC
508*4882a593Smuzhiyun	tristate "TI PRU-ICSS Interrupt Controller"
509*4882a593Smuzhiyun	depends on ARCH_DAVINCI || SOC_AM33XX || SOC_AM43XX || SOC_DRA7XX || ARCH_KEYSTONE || ARCH_K3
510*4882a593Smuzhiyun	select IRQ_DOMAIN
511*4882a593Smuzhiyun	help
512*4882a593Smuzhiyun	  This enables support for the PRU-ICSS Local Interrupt Controller
513*4882a593Smuzhiyun	  present within a PRU-ICSS subsystem present on various TI SoCs.
514*4882a593Smuzhiyun	  The PRUSS INTC enables various interrupts to be routed to multiple
515*4882a593Smuzhiyun	  different processors within the SoC.
516*4882a593Smuzhiyun
517*4882a593Smuzhiyunconfig RISCV_INTC
518*4882a593Smuzhiyun	bool "RISC-V Local Interrupt Controller"
519*4882a593Smuzhiyun	depends on RISCV
520*4882a593Smuzhiyun	default y
521*4882a593Smuzhiyun	help
522*4882a593Smuzhiyun	   This enables support for the per-HART local interrupt controller
523*4882a593Smuzhiyun	   found in standard RISC-V systems.  The per-HART local interrupt
524*4882a593Smuzhiyun	   controller handles timer interrupts, software interrupts, and
525*4882a593Smuzhiyun	   hardware interrupts. Without a per-HART local interrupt controller,
526*4882a593Smuzhiyun	   a RISC-V system will be unable to handle any interrupts.
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun	   If you don't know what to do here, say Y.
529*4882a593Smuzhiyun
530*4882a593Smuzhiyunconfig SIFIVE_PLIC
531*4882a593Smuzhiyun	bool "SiFive Platform-Level Interrupt Controller"
532*4882a593Smuzhiyun	depends on RISCV
533*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
534*4882a593Smuzhiyun	help
535*4882a593Smuzhiyun	   This enables support for the PLIC chip found in SiFive (and
536*4882a593Smuzhiyun	   potentially other) RISC-V systems.  The PLIC controls devices
537*4882a593Smuzhiyun	   interrupts and connects them to each core's local interrupt
538*4882a593Smuzhiyun	   controller.  Aside from timer and software interrupts, all other
539*4882a593Smuzhiyun	   interrupt sources are subordinate to the PLIC.
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun	   If you don't know what to do here, say Y.
542*4882a593Smuzhiyun
543*4882a593Smuzhiyunconfig EXYNOS_IRQ_COMBINER
544*4882a593Smuzhiyun	bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST
545*4882a593Smuzhiyun	depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST
546*4882a593Smuzhiyun	help
547*4882a593Smuzhiyun	  Say yes here to add support for the IRQ combiner devices embedded
548*4882a593Smuzhiyun	  in Samsung Exynos chips.
549*4882a593Smuzhiyun
550*4882a593Smuzhiyunconfig LOONGSON_LIOINTC
551*4882a593Smuzhiyun	bool "Loongson Local I/O Interrupt Controller"
552*4882a593Smuzhiyun	depends on MACH_LOONGSON64
553*4882a593Smuzhiyun	default y
554*4882a593Smuzhiyun	select IRQ_DOMAIN
555*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
556*4882a593Smuzhiyun	help
557*4882a593Smuzhiyun	  Support for the Loongson Local I/O Interrupt Controller.
558*4882a593Smuzhiyun
559*4882a593Smuzhiyunconfig LOONGSON_HTPIC
560*4882a593Smuzhiyun	bool "Loongson3 HyperTransport PIC Controller"
561*4882a593Smuzhiyun	depends on MACH_LOONGSON64
562*4882a593Smuzhiyun	default y
563*4882a593Smuzhiyun	select IRQ_DOMAIN
564*4882a593Smuzhiyun	select GENERIC_IRQ_CHIP
565*4882a593Smuzhiyun	help
566*4882a593Smuzhiyun	  Support for the Loongson-3 HyperTransport PIC Controller.
567*4882a593Smuzhiyun
568*4882a593Smuzhiyunconfig LOONGSON_HTVEC
569*4882a593Smuzhiyun	bool "Loongson3 HyperTransport Interrupt Vector Controller"
570*4882a593Smuzhiyun	depends on MACH_LOONGSON64
571*4882a593Smuzhiyun	default MACH_LOONGSON64
572*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
573*4882a593Smuzhiyun	help
574*4882a593Smuzhiyun	  Support for the Loongson3 HyperTransport Interrupt Vector Controller.
575*4882a593Smuzhiyun
576*4882a593Smuzhiyunconfig LOONGSON_PCH_PIC
577*4882a593Smuzhiyun	bool "Loongson PCH PIC Controller"
578*4882a593Smuzhiyun	depends on MACH_LOONGSON64 || COMPILE_TEST
579*4882a593Smuzhiyun	default MACH_LOONGSON64
580*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
581*4882a593Smuzhiyun	select IRQ_FASTEOI_HIERARCHY_HANDLERS
582*4882a593Smuzhiyun	help
583*4882a593Smuzhiyun	  Support for the Loongson PCH PIC Controller.
584*4882a593Smuzhiyun
585*4882a593Smuzhiyunconfig LOONGSON_PCH_MSI
586*4882a593Smuzhiyun	bool "Loongson PCH MSI Controller"
587*4882a593Smuzhiyun	depends on MACH_LOONGSON64 || COMPILE_TEST
588*4882a593Smuzhiyun	depends on PCI
589*4882a593Smuzhiyun	default MACH_LOONGSON64
590*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
591*4882a593Smuzhiyun	select PCI_MSI
592*4882a593Smuzhiyun	help
593*4882a593Smuzhiyun	  Support for the Loongson PCH MSI Controller.
594*4882a593Smuzhiyun
595*4882a593Smuzhiyunconfig MST_IRQ
596*4882a593Smuzhiyun	bool "MStar Interrupt Controller"
597*4882a593Smuzhiyun	depends on ARCH_MEDIATEK || ARCH_MSTARV7 || COMPILE_TEST
598*4882a593Smuzhiyun	default ARCH_MEDIATEK
599*4882a593Smuzhiyun	select IRQ_DOMAIN
600*4882a593Smuzhiyun	select IRQ_DOMAIN_HIERARCHY
601*4882a593Smuzhiyun	help
602*4882a593Smuzhiyun	  Support MStar Interrupt Controller.
603*4882a593Smuzhiyun
604*4882a593Smuzhiyunendmenu
605