1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2012 Regents of the University of California
4*4882a593Smuzhiyun * Copyright (C) 2017 SiFive
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <linux/mm.h>
8*4882a593Smuzhiyun #include <asm/tlbflush.h>
9*4882a593Smuzhiyun #include <asm/cacheflush.h>
10*4882a593Smuzhiyun #include <asm/mmu_context.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /*
13*4882a593Smuzhiyun * When necessary, performs a deferred icache flush for the given MM context,
14*4882a593Smuzhiyun * on the local CPU. RISC-V has no direct mechanism for instruction cache
15*4882a593Smuzhiyun * shoot downs, so instead we send an IPI that informs the remote harts they
16*4882a593Smuzhiyun * need to flush their local instruction caches. To avoid pathologically slow
17*4882a593Smuzhiyun * behavior in a common case (a bunch of single-hart processes on a many-hart
18*4882a593Smuzhiyun * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
19*4882a593Smuzhiyun * executing a MM context and instead schedule a deferred local instruction
20*4882a593Smuzhiyun * cache flush to be performed before execution resumes on each hart. This
21*4882a593Smuzhiyun * actually performs that local instruction cache flush, which implicitly only
22*4882a593Smuzhiyun * refers to the current hart.
23*4882a593Smuzhiyun */
flush_icache_deferred(struct mm_struct * mm)24*4882a593Smuzhiyun static inline void flush_icache_deferred(struct mm_struct *mm)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun #ifdef CONFIG_SMP
27*4882a593Smuzhiyun unsigned int cpu = smp_processor_id();
28*4882a593Smuzhiyun cpumask_t *mask = &mm->context.icache_stale_mask;
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun if (cpumask_test_cpu(cpu, mask)) {
31*4882a593Smuzhiyun cpumask_clear_cpu(cpu, mask);
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun * Ensure the remote hart's writes are visible to this hart.
34*4882a593Smuzhiyun * This pairs with a barrier in flush_icache_mm.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun smp_mb();
37*4882a593Smuzhiyun local_flush_icache_all();
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #endif
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
switch_mm(struct mm_struct * prev,struct mm_struct * next,struct task_struct * task)43*4882a593Smuzhiyun void switch_mm(struct mm_struct *prev, struct mm_struct *next,
44*4882a593Smuzhiyun struct task_struct *task)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun unsigned int cpu;
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun if (unlikely(prev == next))
49*4882a593Smuzhiyun return;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * Mark the current MM context as inactive, and the next as
53*4882a593Smuzhiyun * active. This is at least used by the icache flushing
54*4882a593Smuzhiyun * routines in order to determine who should be flushed.
55*4882a593Smuzhiyun */
56*4882a593Smuzhiyun cpu = smp_processor_id();
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun cpumask_clear_cpu(cpu, mm_cpumask(prev));
59*4882a593Smuzhiyun cpumask_set_cpu(cpu, mm_cpumask(next));
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #ifdef CONFIG_MMU
62*4882a593Smuzhiyun csr_write(CSR_SATP, virt_to_pfn(next->pgd) | SATP_MODE);
63*4882a593Smuzhiyun local_flush_tlb_all();
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun flush_icache_deferred(next);
67*4882a593Smuzhiyun }
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