1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2017 SiFive
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <asm/cacheflush.h>
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifdef CONFIG_SMP
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <asm/sbi.h>
11*4882a593Smuzhiyun
ipi_remote_fence_i(void * info)12*4882a593Smuzhiyun static void ipi_remote_fence_i(void *info)
13*4882a593Smuzhiyun {
14*4882a593Smuzhiyun return local_flush_icache_all();
15*4882a593Smuzhiyun }
16*4882a593Smuzhiyun
flush_icache_all(void)17*4882a593Smuzhiyun void flush_icache_all(void)
18*4882a593Smuzhiyun {
19*4882a593Smuzhiyun local_flush_icache_all();
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_RISCV_SBI))
22*4882a593Smuzhiyun sbi_remote_fence_i(NULL);
23*4882a593Smuzhiyun else
24*4882a593Smuzhiyun on_each_cpu(ipi_remote_fence_i, NULL, 1);
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun EXPORT_SYMBOL(flush_icache_all);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /*
29*4882a593Smuzhiyun * Performs an icache flush for the given MM context. RISC-V has no direct
30*4882a593Smuzhiyun * mechanism for instruction cache shoot downs, so instead we send an IPI that
31*4882a593Smuzhiyun * informs the remote harts they need to flush their local instruction caches.
32*4882a593Smuzhiyun * To avoid pathologically slow behavior in a common case (a bunch of
33*4882a593Smuzhiyun * single-hart processes on a many-hart machine, ie 'make -j') we avoid the
34*4882a593Smuzhiyun * IPIs for harts that are not currently executing a MM context and instead
35*4882a593Smuzhiyun * schedule a deferred local instruction cache flush to be performed before
36*4882a593Smuzhiyun * execution resumes on each hart.
37*4882a593Smuzhiyun */
flush_icache_mm(struct mm_struct * mm,bool local)38*4882a593Smuzhiyun void flush_icache_mm(struct mm_struct *mm, bool local)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun unsigned int cpu;
41*4882a593Smuzhiyun cpumask_t others, *mask;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun preempt_disable();
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Mark every hart's icache as needing a flush for this MM. */
46*4882a593Smuzhiyun mask = &mm->context.icache_stale_mask;
47*4882a593Smuzhiyun cpumask_setall(mask);
48*4882a593Smuzhiyun /* Flush this hart's I$ now, and mark it as flushed. */
49*4882a593Smuzhiyun cpu = smp_processor_id();
50*4882a593Smuzhiyun cpumask_clear_cpu(cpu, mask);
51*4882a593Smuzhiyun local_flush_icache_all();
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * Flush the I$ of other harts concurrently executing, and mark them as
55*4882a593Smuzhiyun * flushed.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
58*4882a593Smuzhiyun local |= cpumask_empty(&others);
59*4882a593Smuzhiyun if (mm == current->active_mm && local) {
60*4882a593Smuzhiyun /*
61*4882a593Smuzhiyun * It's assumed that at least one strongly ordered operation is
62*4882a593Smuzhiyun * performed on this hart between setting a hart's cpumask bit
63*4882a593Smuzhiyun * and scheduling this MM context on that hart. Sending an SBI
64*4882a593Smuzhiyun * remote message will do this, but in the case where no
65*4882a593Smuzhiyun * messages are sent we still need to order this hart's writes
66*4882a593Smuzhiyun * with flush_icache_deferred().
67*4882a593Smuzhiyun */
68*4882a593Smuzhiyun smp_mb();
69*4882a593Smuzhiyun } else if (IS_ENABLED(CONFIG_RISCV_SBI)) {
70*4882a593Smuzhiyun cpumask_t hartid_mask;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun riscv_cpuid_to_hartid_mask(&others, &hartid_mask);
73*4882a593Smuzhiyun sbi_remote_fence_i(cpumask_bits(&hartid_mask));
74*4882a593Smuzhiyun } else {
75*4882a593Smuzhiyun on_each_cpu_mask(&others, ipi_remote_fence_i, NULL, 1);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun preempt_enable();
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #endif /* CONFIG_SMP */
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #ifdef CONFIG_MMU
flush_icache_pte(pte_t pte)84*4882a593Smuzhiyun void flush_icache_pte(pte_t pte)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun struct page *page = pte_page(pte);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (!test_and_set_bit(PG_dcache_clean, &page->flags))
89*4882a593Smuzhiyun flush_icache_all();
90*4882a593Smuzhiyun }
91*4882a593Smuzhiyun #endif /* CONFIG_MMU */
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