1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/cache.h>
5*4882a593Smuzhiyun #include <linux/highmem.h>
6*4882a593Smuzhiyun #include <linux/mm.h>
7*4882a593Smuzhiyun #include <asm/cache.h>
8*4882a593Smuzhiyun
update_mmu_cache(struct vm_area_struct * vma,unsigned long address,pte_t * pte)9*4882a593Smuzhiyun void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
10*4882a593Smuzhiyun pte_t *pte)
11*4882a593Smuzhiyun {
12*4882a593Smuzhiyun unsigned long addr;
13*4882a593Smuzhiyun struct page *page;
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun page = pfn_to_page(pte_pfn(*pte));
16*4882a593Smuzhiyun if (page == ZERO_PAGE(0))
17*4882a593Smuzhiyun return;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun if (test_and_set_bit(PG_dcache_clean, &page->flags))
20*4882a593Smuzhiyun return;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun addr = (unsigned long) kmap_atomic(page);
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun dcache_wb_range(addr, addr + PAGE_SIZE);
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun if (vma->vm_flags & VM_EXEC)
27*4882a593Smuzhiyun icache_inv_range(addr, addr + PAGE_SIZE);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun kunmap_atomic((void *) addr);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
flush_icache_deferred(struct mm_struct * mm)32*4882a593Smuzhiyun void flush_icache_deferred(struct mm_struct *mm)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun unsigned int cpu = smp_processor_id();
35*4882a593Smuzhiyun cpumask_t *mask = &mm->context.icache_stale_mask;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun if (cpumask_test_cpu(cpu, mask)) {
38*4882a593Smuzhiyun cpumask_clear_cpu(cpu, mask);
39*4882a593Smuzhiyun /*
40*4882a593Smuzhiyun * Ensure the remote hart's writes are visible to this hart.
41*4882a593Smuzhiyun * This pairs with a barrier in flush_icache_mm.
42*4882a593Smuzhiyun */
43*4882a593Smuzhiyun smp_mb();
44*4882a593Smuzhiyun local_icache_inv_all(NULL);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
flush_icache_mm_range(struct mm_struct * mm,unsigned long start,unsigned long end)48*4882a593Smuzhiyun void flush_icache_mm_range(struct mm_struct *mm,
49*4882a593Smuzhiyun unsigned long start, unsigned long end)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun unsigned int cpu;
52*4882a593Smuzhiyun cpumask_t others, *mask;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun preempt_disable();
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #ifdef CONFIG_CPU_HAS_ICACHE_INS
57*4882a593Smuzhiyun if (mm == current->mm) {
58*4882a593Smuzhiyun icache_inv_range(start, end);
59*4882a593Smuzhiyun preempt_enable();
60*4882a593Smuzhiyun return;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Mark every hart's icache as needing a flush for this MM. */
65*4882a593Smuzhiyun mask = &mm->context.icache_stale_mask;
66*4882a593Smuzhiyun cpumask_setall(mask);
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Flush this hart's I$ now, and mark it as flushed. */
69*4882a593Smuzhiyun cpu = smp_processor_id();
70*4882a593Smuzhiyun cpumask_clear_cpu(cpu, mask);
71*4882a593Smuzhiyun local_icache_inv_all(NULL);
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun * Flush the I$ of other harts concurrently executing, and mark them as
75*4882a593Smuzhiyun * flushed.
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun if (mm != current->active_mm || !cpumask_empty(&others)) {
80*4882a593Smuzhiyun on_each_cpu_mask(&others, local_icache_inv_all, NULL, 1);
81*4882a593Smuzhiyun cpumask_clear(mask);
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun preempt_enable();
85*4882a593Smuzhiyun }
86