| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/ |
| H A D | samsung-pinctrl.txt | 6 on-chip controllers onto these pads.
9 - compatible: should be one of the following.
10 - "samsung,s3c2412-pinctrl": for S3C2412-compatible pin-controller,
11 - "samsung,s3c2416-pinctrl": for S3C2416-compatible pin-controller,
12 - "samsung,s3c2440-pinctrl": for S3C2440-compatible pin-controller,
13 - "samsung,s3c2450-pinctrl": for S3C2450-compatible pin-controller,
14 - "samsung,s3c64xx-pinctrl": for S3C64xx-compatible pin-controller,
15 - "samsung,s5pv210-pinctrl": for S5PV210-compatible pin-controller,
16 - "samsung,exynos3250-pinctrl": for Exynos3250 compatible pin-controller.
17 - "samsung,exynos4210-pinctrl": for Exynos4210 compatible pin-controller.
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| H A D | aspeed,ast2500-pinctrl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/aspeed,ast2500-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Jeffery <andrew@aj.id.au>
16 - compatible: Should be one of the following:
17 "aspeed,ast2500-scu", "syscon", "simple-mfd"
18 "aspeed,g5-scu", "syscon", "simple-mfd"
25 const: aspeed,ast2500-pinctrl
28 A hint for the memory regions associated with the pin-controller
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/powerpc/fsl/ |
| H A D | mpc5200.txt | 2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/clock/ |
| H A D | clock-bindings.txt | 1 This binding is a work-in-progress, and are based on some experimental
5 tree. Those nodes are designated as clock providers. Clock consumer
6 nodes use a phandle and clock specifier pair to connect clock provider
10 value of a #clock-cells property in the clock provider node.
17 #clock-cells: Number of cells in a clock specifier; Typically 0 for nodes
18 with a single clock output and 1 for nodes with multiple
22 clock-output-names: Recommended to be a list of strings of clock output signal
24 However, the meaning of clock-output-names is domain
32 Clock consumer nodes must never directly reference
33 the provider's clock-output-names property.
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| H A D | amlogic,gxbb-aoclkc.txt | 4 controllers within the Always-On part of the SoC.
8 - compatible: value should be different for each SoC family as :
9 - GXBB (S905) : "amlogic,meson-gxbb-aoclkc"
10 - GXL (S905X, S905D) : "amlogic,meson-gxl-aoclkc"
11 - GXM (S912) : "amlogic,meson-gxm-aoclkc"
12 - AXG (A113D, A113X) : "amlogic,meson-axg-aoclkc"
13 - G12A (S905X2, S905D2, S905Y2) : "amlogic,meson-g12a-aoclkc"
14 followed by the common "amlogic,meson-gx-aoclkc"
15 - clocks: list of clock phandle, one for each entry clock-names.
16 - clock-names: should contain the following:
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| H A D | st,stm32-rcc.txt | 6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
23 - clocks: External oscillator clock phandle
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| H A D | renesas,rcar-usb2-clock-sel.txt | 1 * Renesas R-Car USB 2.0 clock selector
3 This file provides information on what the device node for the R-Car USB 2.0
6 If you connect an external clock to the USB_EXTAL pin only, you should set
10 clock rates to both "usb_extal" and "usb_xtal" nodes.
12 Case 1: An external clock connects to R-Car SoC
13 +----------+ +--- R-Car ---------------------+
14 |External |---|USB_EXTAL ---> all usb channels|
16 +----------+ +-------------------------------+
19 Case 2: An oscillator connects to R-Car SoC
20 +----------+ +--- R-Car ---------------------+
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| H A D | rockchip,rk3368-cru.txt | 9 - compatible: should be "rockchip,rk3368-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
22 preprocessor macros in the dt-bindings/clock/rk3368-cru.h headers and can be
26 External clocks:
30 clock-output-names:
31 - "xin24m" - crystal input - required,
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| H A D | rockchip,rv1108-cru.txt | 9 - compatible: should be "rockchip,rv1108-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
22 preprocessor macros in the dt-bindings/clock/rv1108-cru.h headers and can be
26 External clocks:
30 clock-output-names:
31 - "xin24m" - crystal input - required,
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| H A D | rockchip,rk3288-cru.txt | 8 different so another dt-compatible is available. Noticed that it is only
14 - compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
16 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
19 - #reset-cells: should be 1.
23 - rockchip,grf: phandle to the syscon managing the "general register files"
26 Each clock is assigned an identifier and client nodes can use this identifier
28 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
32 External clocks:
36 clock-output-names:
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| H A D | rockchip,rv1126-cru.txt | 9 - compatible: PMU for CRU should be "rockchip,rv1126-pmucru"
10 - compatible: CRU should be "rockchip,rv1126-cru"
11 - reg: physical base address of the controller and length of memory mapped
13 - #clock-cells: should be 1.
14 - #reset-cells: should be 1.
18 - rockchip,grf: phandle to the syscon managing the "general register files"
21 Each clock is assigned an identifier and client nodes can use this identifier
23 preprocessor macros in the dt-bindings/clock/rv1126-cru.h headers and can be
27 External clocks:
31 clock-output-names:
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| H A D | renesas,r9a06g032-sysctrl.txt | 5 - compatible: Must be:
6 - "renesas,r9a06g032-sysctrl"
7 - reg: Base address and length of the SYSCTRL IO block.
8 - #clock-cells: Must be 1
9 - clocks: References to the parent clocks:
10 - external 40mhz crystal.
11 - external (optional) 32.768khz
12 - external (optional) jtag input
13 - external (optional) RGMII_REFCLK
14 - clock-names: Must be:
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| /OK3568_Linux_fs/u-boot/doc/uImage.FIT/ |
| H A D | source_file_format.txt | 1 U-Boot new uImage source file format (bindings definition)
5 External data additions, 25/1/16 Simon Glass <sjg@chromium.org>
8 ---------------
15 replace direct passing of 'struct bd_info' which was used to boot pre-FDT
18 However, U-Boot needs to support both techniques to provide backward
21 blob. Kernel image, FDT blob and possibly ramdisk image - all must be placed
24 Additionally, old uImage format has been extended to support multi sub-images
34 --------------------------------
40 (3) increases code reuse as it is already part of the U-Boot source tree.
45 uImage internals. Bindings are defined from U-Boot perspective, i.e. describe
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/ |
| H A D | as3722.txt | 4 -------------------
5 - compatible: Must be "ams,as3722".
6 - reg: I2C device address.
7 - interrupt-controller: AS3722 has internal interrupt controller which takes the
8 interrupt request from internal sub-blocks like RTC, regulators, GPIOs as well
9 as external input.
10 - #interrupt-cells: Should be set to 2 for IRQ number and flags.
12 of AS3722 are defined at dt-bindings/mfd/as3722.h
14 interrupts.txt, using dt-bindings/irq.
17 --------------------
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/regulator/ |
| H A D | lp872x.txt | 4 - compatible: "ti,lp8720" or "ti,lp8725"
5 - reg: I2C slave address. 0x7d = LP8720, 0x7a = LP8725
8 - ti,general-config: the value of LP872X_GENERAL_CFG register (u8)
10 bit[2]: BUCK output voltage control by external DVS pin or register
11 1 = external pin, 0 = bit7 of register 08h
12 bit[1]: sleep control by external DVS pin or register
13 1 = external pin, 0 = bit6 of register 08h
20 bit[2]: BUCK1 output voltage control by external DVS pin or register
27 - ti,update-config: define it when LP872X_GENERAL_CFG register should be set
28 - ti,dvs-gpio: GPIO specifier for external DVS pin control of LP872x devices.
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| H A D | as3722-regulator.txt | 5 --------------------
7 regulator node. The AS3722 is having 7 DCDC step-down regulators as
8 sd[0-6], 10 LDOs as ldo[0-7], ldo[9-11]. The input supply of these
10 vsup-sd2-supply: Input supply for SD2.
11 vsup-sd3-supply: Input supply for SD3.
12 vsup-sd4-supply: Input supply for SD4.
13 vsup-sd5-supply: Input supply for SD5.
14 vin-ldo0-supply: Input supply for LDO0.
15 vin-ldo1-6-supply: Input supply for LDO1 and LDO6.
16 vin-ldo2-5-7-supply: Input supply for LDO2, LDO5 and LDO7.
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| /OK3568_Linux_fs/kernel/fs/hpfs/ |
| H A D | anode.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Mikulas Patocka (mikulas@artax.karlin.mff.cuni.cz), 1998-1999
18 anode_secno a = -1; in hpfs_bplus_lookup()
23 if (hpfs_sb(s)->sb_chk) if (hpfs_stop_cycles(s, a, &c1, &c2, "hpfs_bplus_lookup")) return -1; in hpfs_bplus_lookup()
25 for (i = 0; i < btree->n_used_nodes; i++) in hpfs_bplus_lookup()
26 if (le32_to_cpu(btree->u.internal[i].file_secno) > sec) { in hpfs_bplus_lookup()
27 a = le32_to_cpu(btree->u.internal[i].down); in hpfs_bplus_lookup()
29 if (!(anode = hpfs_map_anode(s, a, &bh))) return -1; in hpfs_bplus_lookup()
30 btree = &anode->btree; in hpfs_bplus_lookup()
35 return -1; in hpfs_bplus_lookup()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/media/ |
| H A D | samsung-fimc.txt | 2 ----------------------------------------------
4 The S5P/Exynos SoC Camera subsystem comprises of multiple sub-devices
5 represented by separate device tree nodes. Currently this includes: FIMC (in
6 the S5P SoCs series known as CAMIF), MIPI CSIS, FIMC-LITE and FIMC-IS (ISP).
8 The sub-subdevices are defined as child nodes of the common 'camera' node which
10 any single sub-device, like common camera port pins or the CAMCLK clock outputs
11 for external image sensors attached to an SoC.
14 --------------------
18 - compatible: must be "samsung,fimc", "simple-bus"
19 - clocks: list of clock specifiers, corresponding to entries in
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| H A D | video-interfaces.txt | 4 ---------------
6 Video data pipelines usually consist of external devices, e.g. camera sensors,
10 SoC internal blocks are described by DT nodes, placed similarly to other SoC
11 blocks. External devices are represented as child nodes of their respective
12 bus controller nodes, e.g. I2C.
14 Data interfaces on all video devices are described by their child 'port' nodes.
21 #address-cells = <1>;
22 #size-cells = <0>;
37 a common scheme using '#address-cells', '#size-cells' and 'reg' properties is
40 All 'port' nodes can be grouped under optional 'ports' node, which allows to
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| H A D | cdns,csi2rx.txt | 1 Cadence MIPI-CSI2 RX controller
4 The Cadence MIPI-CSI2 RX controller is a CSI-2 bridge supporting up to 4 CSI
8 - compatible: must be set to "cdns,csi2rx" and an SoC-specific compatible
9 - reg: base address and size of the memory mapped region
10 - clocks: phandles to the clocks driving the controller
11 - clock-names: must contain:
14 * pixel_if[0-3]_clk: pixel stream output clock, one for each stream
18 - phys: phandle to the external D-PHY, phy-names must be provided
19 - phy-names: must contain "dphy", if the implementation uses an
20 external D-PHY
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| /OK3568_Linux_fs/u-boot/doc/device-tree-bindings/clock/ |
| H A D | rockchip,rk3288-cru.txt | 9 - compatible: should be "rockchip,rk3288-cru"
10 - reg: physical base address of the controller and length of memory mapped
12 - #clock-cells: should be 1.
13 - #reset-cells: should be 1.
17 - rockchip,grf: phandle to the syscon managing the "general register files"
20 Each clock is assigned an identifier and client nodes can use this identifier
22 preprocessor macros in the dt-bindings/clock/rk3288-cru.h headers and can be
26 External clocks:
30 clock-output-names:
31 - "xin24m" - crystal input - required,
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/bus/ |
| H A D | nvidia,tegra20-gmi.txt | 4 external memory. Can be used to attach various high speed devices such as
7 The actual devices are instantiated from the child nodes of a GMI node.
10 - compatible : Should contain one of the following:
11 For Tegra20 must contain "nvidia,tegra20-gmi".
12 For Tegra30 must contain "nvidia,tegra30-gmi".
13 - reg: Should contain GMI controller registers location and length.
14 - clocks: Must contain an entry for each entry in clock-names.
15 - clock-names: Must include the following entries: "gmi"
16 - resets : Must contain an entry for each entry in reset-names.
17 - reset-names : Must include the following entries: "gmi"
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| /OK3568_Linux_fs/kernel/Documentation/admin-guide/media/ |
| H A D | davinci-vpbe.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 -----------------------
13 Implements creation of video2 and video3 device nodes and
18 Loads up VENC, OSD and external encoders such as ths8200. It provides
20 in the VENC or external sub devices. It also provides
22 using sub device ops. The connection of external encoders to VENC LCD
27 When connected to an external encoder, vpbe controller is also responsible
28 for setting up the interface between VENC and external encoders based on
29 board specific settings (specified in board-xxx-evm.c). This allows
30 interfacing external encoders such as ths8200. The setup_if_config()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/iio/adc/ |
| H A D | at91_adc.txt | 4 - compatible: Should be "atmel,<chip>-adc"
6 - reg: Should contain ADC registers location and length
7 - interrupts: Should contain the IRQ line for the ADC
8 - clock-names: tuple listing input clock names.
10 - clocks: phandles to input clocks.
11 - atmel,adc-channels-used: Bitmask of the channels muxed and enabled for this
13 - atmel,adc-startup-time: Startup Time of the ADC in microseconds as
15 - atmel,adc-vref: Reference voltage in millivolts for the conversions
16 - atmel,adc-res: List of resolutions in bits supported by the ADC. List size
18 - atmel,adc-res-names: Contains one identifier string for each resolution
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| H A D | xilinx-xadc.txt | 13 - compatible: Should be one of
14 * "xlnx,zynq-xadc-1.00.a": When using the ZYNQ device
16 * "xlnx,axi-xadc-1.00.a": When using the axi-xadc pcore to
18 - reg: Address and length of the register set for the device
19 - interrupts: Interrupt for the XADC control interface.
20 - clocks: When using the ZYNQ this must be the ZYNQ PCAP clock,
21 when using the AXI-XADC pcore this must be the clock that provides the
25 - xlnx,external-mux:
26 * "none": No external multiplexer is used, this is the default
28 * "single": External multiplexer mode is used with one
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