1* Rockchip RV1126 Clock and Reset Unit 2 3The RV1126 clock controller generates and supplies clock to various 4controllers within the SoC and also implements a reset controller for SoC 5peripherals. 6 7Required Properties: 8 9- compatible: PMU for CRU should be "rockchip,rv1126-pmucru" 10- compatible: CRU should be "rockchip,rv1126-cru" 11- reg: physical base address of the controller and length of memory mapped 12 region. 13- #clock-cells: should be 1. 14- #reset-cells: should be 1. 15 16Optional Properties: 17 18- rockchip,grf: phandle to the syscon managing the "general register files" 19 If missing, pll rates are not changeable, due to the missing pll lock status. 20 21Each clock is assigned an identifier and client nodes can use this identifier 22to specify the clock which they consume. All available clocks are defined as 23preprocessor macros in the dt-bindings/clock/rv1126-cru.h headers and can be 24used in device tree sources. Similar macros exist for the reset sources in 25these files. 26 27External clocks: 28 29There are several clocks that are generated outside the SoC. It is expected 30that they are defined using standard clock bindings with following 31clock-output-names: 32 - "xin24m" - crystal input - required, 33 - "xin32k" - rtc clock - optional, 34 - "i2s8ch_mclkin" - external I2S clock - optional, 35 - "i2s2ch0_mclkin" - external I2S clock - optional, 36 - "i2s2ch1_mclkin" - external I2S clock - optional, 37 - "clk_gmac_rgmii_clkin_m0" - external GMAC clock - optional 38 - "clk_gmac_rgmii_clkin_m1" - external GMAC clock - optional 39 40Example: Clock controller node: 41 42 pmucru: clock-controller@ff480000 { 43 compatible = "rockchip,rv1126-pmucru"; 44 reg = <0x0 0xff480000 0x0 0x1000>; 45 #clock-cells = <1>; 46 #reset-cells = <1>; 47 }; 48 49 cru: clock-controller@ff490000 { 50 compatible = "rockchip,rv1126-cru"; 51 reg = <0x0 0xff490000 0x0 0x1000>; 52 rockchip,grf = <&grf>; 53 #clock-cells = <1>; 54 #reset-cells = <1>; 55 }; 56 57Example: UART controller node that consumes the clock generated by the clock 58 controller: 59 60 uart0: serial@ff560000 { 61 compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; 62 reg = <0xff560000 0x100>; 63 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 64 reg-shift = <2>; 65 reg-io-width = <4>; 66 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 67 clock-names = "baudclk", "apb_pclk"; 68 }; 69