1*4882a593Smuzhiyun.. SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe VPBE V4L2 driver design 4*4882a593Smuzhiyun=========================== 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunFunctional partitioning 7*4882a593Smuzhiyun----------------------- 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunConsists of the following: 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun 1. V4L2 display driver 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun Implements creation of video2 and video3 device nodes and 14*4882a593Smuzhiyun provides v4l2 device interface to manage VID0 and VID1 layers. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun 2. Display controller 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun Loads up VENC, OSD and external encoders such as ths8200. It provides 19*4882a593Smuzhiyun a set of API calls to V4L2 drivers to set the output/standards 20*4882a593Smuzhiyun in the VENC or external sub devices. It also provides 21*4882a593Smuzhiyun a device object to access the services from OSD subdevice 22*4882a593Smuzhiyun using sub device ops. The connection of external encoders to VENC LCD 23*4882a593Smuzhiyun controller port is done at init time based on default output and standard 24*4882a593Smuzhiyun selection or at run time when application change the output through 25*4882a593Smuzhiyun V4L2 IOCTLs. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun When connected to an external encoder, vpbe controller is also responsible 28*4882a593Smuzhiyun for setting up the interface between VENC and external encoders based on 29*4882a593Smuzhiyun board specific settings (specified in board-xxx-evm.c). This allows 30*4882a593Smuzhiyun interfacing external encoders such as ths8200. The setup_if_config() 31*4882a593Smuzhiyun is implemented for this as well as configure_venc() (part of the next patch) 32*4882a593Smuzhiyun API to set timings in VENC for a specific display resolution. As of this 33*4882a593Smuzhiyun patch series, the interconnection and enabling and setting of the external 34*4882a593Smuzhiyun encoders is not present, and would be a part of the next patch series. 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun 3. VENC subdevice module 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun Responsible for setting outputs provided through internal DACs and also 39*4882a593Smuzhiyun setting timings at LCD controller port when external encoders are connected 40*4882a593Smuzhiyun at the port or LCD panel timings required. When external encoder/LCD panel 41*4882a593Smuzhiyun is connected, the timings for a specific standard/preset is retrieved from 42*4882a593Smuzhiyun the board specific table and the values are used to set the timings in 43*4882a593Smuzhiyun venc using non-standard timing mode. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun Support LCD Panel displays using the VENC. For example to support a Logic 46*4882a593Smuzhiyun PD display, it requires setting up the LCD controller port with a set of 47*4882a593Smuzhiyun timings for the resolution supported and setting the dot clock. So we could 48*4882a593Smuzhiyun add the available outputs as a board specific entry (i.e add the "LogicPD" 49*4882a593Smuzhiyun output name to board-xxx-evm.c). A table of timings for various LCDs 50*4882a593Smuzhiyun supported can be maintained in the board specific setup file to support 51*4882a593Smuzhiyun various LCD displays.As of this patch a basic driver is present, and this 52*4882a593Smuzhiyun support for external encoders and displays forms a part of the next 53*4882a593Smuzhiyun patch series. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun 4. OSD module 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun OSD module implements all OSD layer management and hardware specific 58*4882a593Smuzhiyun features. The VPBE module interacts with the OSD for enabling and 59*4882a593Smuzhiyun disabling appropriate features of the OSD. 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunCurrent status 62*4882a593Smuzhiyun-------------- 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunA fully functional working version of the V4L2 driver is available. This 65*4882a593Smuzhiyundriver has been tested with NTSC and PAL standards and buffer streaming. 66