Searched +full:emc +full:- +full:timings +full:- +full:1 (Results 1 – 25 of 27) sorted by relevance
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1 // SPDX-License-Identifier: GPL-2.077 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)86 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)151 struct emc_timing *timings; member163 struct tegra_emc *emc = data; in tegra_emc_isr() local167 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()173 dev_err_ratelimited(emc->dev, in tegra_emc_isr()177 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()182 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument188 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()[all …]
1 // SPDX-License-Identifier: GPL-2.0+5 * Based on downstream driver from NVIDIA and tegra124-emc.c6 * Copyright (C) 2011-2014 NVIDIA Corporation9 * Copyright (C) 2019 GRATE-DRIVER project151 ((num) > 1 ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)161 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)192 (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)193 #define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)199 #define EMC_CLKCHANGE_PD_ENABLE BIT(1)222 [1] = EMC_RFC,[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.21 #include "tegra210-emc.h"22 #include "tegra210-mc.h"44 #define PLLM_VCOB 162 next->trim_regs[EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## \69 next->trim_perch_regs[EMC ## chan ## \80 ((new[n + 1] << EMC_PMACRO_OB_DDLL_LONG_DQ_RANK ## rank ## _ ##\522 { .bank = 1, .offset = EMC_MRW10, },524 { .bank = 1, .offset = EMC_MRW11, },[all …]
1 // SPDX-License-Identifier: GPL-2.0-only9 #include <linux/clk-provider.h>21 #include <soc/tegra/emc.h>264 #define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)274 #define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)275 #define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)282 DRAM_TYPE_DDR1 = 1,476 struct emc_timing *timings; member488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()[all …]
1 /* SPDX-License-Identifier: GPL-2.0 */3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.24 #define EMC_DBG_WRITE_MUX_ACTIVE BIT(1)33 #define EMC_PIN_PIN_CKEB BIT(1)143 #define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK BIT(1)175 #define EMC_ZQ_CAL_ZQ_LATCH_CMD BIT(1)197 #define EMC_CCFIFO_ADDR_STALL_BY_1 (1 << 31)243 #define EMC_FBIO_CFG7_CH0_ENABLE BIT(1)653 #define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC BIT(1)661 #define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC BIT(1)[all …]
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Thierry Reding <thierry.reding@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>14 The EMC interfaces with the off-chip SDRAM to service the request stream19 const: nvidia,tegra124-emc22 maxItems: 126 - description: external memory clock[all …]
1 # SPDX-License-Identifier: (GPL-2.0)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>15 The EMC interfaces with the off-chip SDRAM to service the request stream16 sent from Memory Controller. The EMC also has various performance-affecting18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,[all …]
1 # SPDX-License-Identifier: (GPL-2.0)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Jon Hunter <jonathanh@nvidia.com>11 - Thierry Reding <thierry.reding@gmail.com>14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.22 const: nvidia,tegra124-mc25 maxItems: 128 maxItems: 1[all …]
1 # SPDX-License-Identifier: (GPL-2.0)3 ---4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Dmitry Osipenko <digetx@gmail.com>11 - Jon Hunter <jonathanh@nvidia.com>12 - Thierry Reding <thierry.reding@gmail.com>39 const: nvidia,tegra30-mc42 maxItems: 145 maxItems: 1[all …]
1 // SPDX-License-Identifier: GPL-2.0-only3 * drivers/clk/tegra/clk-emc.c11 #include <linux/clk-provider.h>24 #include <soc/tegra/emc.h>46 * List of clock sources for various parents the EMC clock can have.53 #define EMC_SRC_PLL_C 178 struct tegra_emc *emc; member81 struct emc_timing *timings; member101 val = readl(tegra->clk_regs + CLK_SOURCE_EMC); in emc_recalc_rate()109 * safer since things have EMC rate floors. Also don't touch parent_rate[all …]
1 // SPDX-License-Identifier: GPL-2.03 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.8 #include <linux/clk-provider.h>23 #define CLK_SRC_PLLC 153 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()[all …]
4 Documentation/devicetree/bindings/clock/clock-bindings.txt10 - compatible : Should be "nvidia,tegra124-car" or "nvidia,tegra132-car"11 - reg : Should contain CAR registers location and length12 - clocks : Should contain phandle and clock specifiers for two clocks:13 the 32 KHz "32k_in", and the board-specific oscillator "osc".14 - #clock-cells : Should be 1.17 <dt-bindings/clock/tegra124-car-common.h> (which covers IDs common18 to Tegra124 and Tegra132) and <dt-bindings/clock/tegra124-car.h>19 (for Tegra124-specific clocks).20 - #reset-cells : Should be 1.[all …]
1 // SPDX-License-Identifier: GPL-2.03 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"7 * Tilapia's memory timings are pretty much the same as the Grouper's9 * these differentiating timings are overridden here for Tilapia.12 memory-controller@7000f400 {13 emc-timings-0 {14 timing-667000000 {15 clock-frequency = <667000000>;17 nvidia,emc-auto-cal-interval = <0x001fffff>;18 nvidia,emc-mode-1 = <0x80100002>;[all …]
1 // SPDX-License-Identifier: GPL-2.04 emc-timings-1 {5 nvidia,ram-code = <1>;7 timing-12750000 {8 clock-frequency = <12750000>;9 nvidia,parent-clock-frequency = <408000000>;11 clock-names = "emc-parent";13 timing-20400000 {14 clock-frequency = <20400000>;15 nvidia,parent-clock-frequency = <408000000>;[all …]
1 // SPDX-License-Identifier: GPL-2.0 OR X113 * Copyright 2016-2019 Toradex AG9 emc-timings-1 {10 nvidia,ram-code = <1>;12 timing-12750000 {13 clock-frequency = <12750000>;14 nvidia,parent-clock-frequency = <408000000>;16 clock-names = "emc-parent";18 timing-20400000 {19 clock-frequency = <20400000>;[all …]
1 // SPDX-License-Identifier: GPL-2.04 emc-timings-3 {5 nvidia,ram-code = <3>;7 timing-12750000 {8 clock-frequency = <12750000>;9 nvidia,parent-clock-frequency = <408000000>;11 clock-names = "emc-parent";13 timing-20400000 {14 clock-frequency = <20400000>;15 nvidia,parent-clock-frequency = <408000000>;[all …]
1 // SPDX-License-Identifier: GPL-2.04 memory-controller@7000f000 {5 emc-timings-0 {6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */8 timing-25500000 {9 clock-frequency = <25500000>;11 nvidia,emem-configuration = <33 timing-51000000 {34 clock-frequency = <51000000>;36 nvidia,emem-configuration = <[all …]
1 // SPDX-License-Identifier: GPL-2.04 nvidia,long-ram-code;8 emc-timings-1 {9 nvidia,ram-code = <1>;11 timing-12750000 {12 clock-frequency = <12750000>;13 nvidia,parent-clock-frequency = <408000000>;15 clock-names = "emc-parent";17 timing-20400000 {18 clock-frequency = <20400000>;[all …]
4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>6 * SPDX-License-Identifier: GPL-2.0+13 #include <asm/arch/emc.h>19 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; variable26 setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); in reset_periph()27 writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); in reset_periph()30 writel(0, &wdt->mctrl); in reset_periph()31 clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); in reset_periph()40 lpc32xx_i2c_init(1); in board_early_init_f()57 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; in board_init()[all …]
5 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>14 * SPDX-License-Identifier: GPL-2.0+22 #include <asm/arch/emc.h>26 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; variable32 /* Enable EMC interface and choose little endian mode */ in ddr_init()33 writel(1, &emc->ctrl); in ddr_init()34 writel(0, &emc->config); in ddr_init()35 /* Select maximum EMC Dynamic Memory Refresh Time */ in ddr_init()36 writel(0x7FF, &emc->refresh); in ddr_init()40 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init()[all …]
4 * SPDX-License-Identifier: GPL-2.0+10 #include <asm/arch-tegra/ap.h>11 #include <asm/arch-tegra/apb_misc.h>13 #include <asm/arch/emc.h>17 * The EMC registers have shadow registers. When the EMC clock is updated21 * and relies on the clock lock on the emc clock to avoid races between95 ERR_NO_EMC_NODE = -10,105 * Find EMC tables for the given ram code.107 * The tegra EMC binding has two options, one using the ram code and one not.108 * We detect which is in use by looking for the nvidia,use-ram-code property.[all …]
1 /dts-v1/;3 #include <dt-bindings/input/input.h>31 stdout-path = &uartd;47 display-timings {50 clock-frequency = <70600000>;53 hback-porch = <58>;54 hfront-porch = <58>;55 hsync-len = <58>;56 vback-porch = <4>;57 vfront-porch = <4>;[all …]
3 * SPDX-License-Identifier: GPL-2.0+29 * good reason why driver-model conversion is infeasible. Examples include35 COMPAT(NVIDIA_TEGRA20_EMC, "nvidia,tegra20-emc"),36 COMPAT(NVIDIA_TEGRA20_EMC_TABLE, "nvidia,tegra20-emc-table"),37 COMPAT(NVIDIA_TEGRA20_NAND, "nvidia,tegra20-nand"),38 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),39 COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),41 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),42 COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),43 COMPAT(SAMSUNG_EXYNOS5_SOUND, "samsung,exynos-sound"),[all …]
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