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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Dtegra124-nyan-blaze-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-1 {
5 nvidia,ram-code = <1>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
H A Dtegra124-apalis-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR X11
3 * Copyright 2016-2019 Toradex AG
9 emc-timings-1 {
10 nvidia,ram-code = <1>;
12 timing-12750000 {
13 clock-frequency = <12750000>;
14 nvidia,parent-clock-frequency = <408000000>;
16 clock-names = "emc-parent";
18 timing-20400000 {
19 clock-frequency = <20400000>;
[all …]
H A Dtegra124-jetson-tk1-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 emc-timings-3 {
5 nvidia,ram-code = <3>;
7 timing-12750000 {
8 clock-frequency = <12750000>;
9 nvidia,parent-clock-frequency = <408000000>;
11 clock-names = "emc-parent";
13 timing-20400000 {
14 clock-frequency = <20400000>;
15 nvidia,parent-clock-frequency = <408000000>;
[all …]
H A Dtegra30-asus-nexus7-grouper-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 memory-controller@7000f000 {
5 emc-timings-0 {
6 nvidia,ram-code = <0>; /* Elpida EDJ2108EDBG-DJL-F */
8 timing-25500000 {
9 clock-frequency = <25500000>;
11 nvidia,emem-configuration = <
33 timing-51000000 {
34 clock-frequency = <51000000>;
36 nvidia,emem-configuration = <
[all …]
H A Dtegra124-nyan-big-emc.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 nvidia,long-ram-code;
8 emc-timings-1 {
9 nvidia,ram-code = <1>;
11 timing-12750000 {
12 clock-frequency = <12750000>;
13 nvidia,parent-clock-frequency = <408000000>;
15 clock-names = "emc-parent";
17 timing-20400000 {
18 clock-frequency = <20400000>;
[all …]
H A Dtegra30-asus-nexus7-tilapia-memory-timings.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
12 memory-controller@7000f400 {
13 emc-timings-0 {
14 timing-667000000 {
15 clock-frequency = <667000000>;
17 nvidia,emc-auto-cal-interval = <0x001fffff>;
18 nvidia,emc-mode-1 = <0x80100002>;
19 nvidia,emc-mode-2 = <0x80200018>;
20 nvidia,emc-mode-reset = <0x80000b71>;
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra20-emc.txt4 - name : Should be emc
5 - #address-cells : Should be 1
6 - #size-cells : Should be 0
7 - compatible : Should contain "nvidia,tegra20-emc".
8 - reg : Offset and length of the register set for the device
9 - nvidia,use-ram-code : If present, the sub-nodes will be addressed
12 irrespective of ram-code configuration.
13 - interrupts : Should contain EMC General interrupt.
14 - clocks : Should contain EMC clock.
20 memory-controller@7000f400 {
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H A Dnvidia,tegra30-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
17 settings beyond the obvious SDRAM configuration parameters and initialization
[all …]
H A Dnvidia,tegra124-emc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
26 - description: external memory clock
28 clock-names:
[all …]
H A Dnvidia,tegra124-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller.
22 const: nvidia,tegra124-mc
30 clock-names:
32 - const: mc
[all …]
H A Dnvidia,tegra30-mc.yaml1 # SPDX-License-Identifier: (GPL-2.0)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
30 Global Resources, which include things like configuration registers which
39 const: nvidia,tegra30-mc
47 clock-names:
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/OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-lpc32xx/
H A Demc.h4 * SPDX-License-Identifier: GPL-2.0+
12 /* EMC Registers */
14 u32 ctrl; /* Controls operation of the EMC */
15 u32 status; /* Provides EMC status information */
16 u32 config; /* Configures operation of the EMC */
24 u32 t_srex; /* Self-refresh exit time */
28 u32 t_rfc; /* Auto-refresh period */
29 u32 t_xsr; /* Exit self-refresh to active command time */
36 u32 config0; /* Configuration information for the SDRAM */
39 u32 config1; /* Configuration information for the SDRAM */
[all …]
H A Dcpu.h4 * SPDX-License-Identifier: GPL-2.0+
21 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
/OK3568_Linux_fs/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/
H A Ddram.c5 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
12 * by the board configuration file.
14 * SPDX-License-Identifier: GPL-2.0+
22 #include <asm/arch/emc.h>
26 static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; variable
32 /* Enable EMC interface and choose little endian mode */ in ddr_init()
33 writel(1, &emc->ctrl); in ddr_init()
34 writel(0, &emc->config); in ddr_init()
35 /* Select maximum EMC Dynamic Memory Refresh Time */ in ddr_init()
36 writel(0x7FF, &emc->refresh); in ddr_init()
[all …]
/OK3568_Linux_fs/kernel/drivers/clk/tegra/
H A Dclk-tegra210-emc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved.
8 #include <linux/clk-provider.h>
53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
71 * ->set_rate(), so the parent rate passed in here was cached from the in tegra210_clk_emc_recalc_rate()
72 * parent before the ->set_rate() call. in tegra210_clk_emc_recalc_rate()
74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()
75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate()
[all …]
/OK3568_Linux_fs/kernel/drivers/memory/tegra/
H A Dtegra30-emc.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
357 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
362 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
364 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
368 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
377 struct tegra_emc *emc = data; in tegra_emc_isr() local
381 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
[all …]
H A Dtegra124-emc.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
21 #include <soc/tegra/emc.h>
488 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
491 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
495 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
500 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
503 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
509 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
[all …]
H A Dtegra210-emc-cc-r21021.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
14 #include "tegra210-emc.h"
15 #include "tegra210-mc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
53 * PTFV defines - basically just indexes into the per table PTFV array.
78 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] = \
79 next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] / \
80 next->ptfv_list[PTFV_DVFS_SAMPLES_INDEX]; })
86 ({ next->ptfv_list[PTFV_DQSOSC_MOVAVG_ ## dev ## _INDEX] += \
[all …]
/OK3568_Linux_fs/kernel/Documentation/ABI/testing/
H A Dsysfs-firmware-efi24 Contact: linux-efi@vger.kernel.org
25 Description: Displays the physical addresses of all EFI Configuration
34 Contact: Narendra K <Narendra.K@dell.com>, linux-bugs@dell.com
35 Description: Displays the content of the Runtime Configuration Interface
36 Table version 2 on Dell EMC PowerEdge systems in binary format
37 Users: It is used by Dell EMC OpenManage Server Administrator tool to
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include <dt-bindings/power/tegra194-powergate.h>
8 #include <dt-bindings/reset/tegra194-reset.h>
9 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
10 #include <dt-bindings/memory/tegra194-mc.h>
[all …]
H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
[all …]
/OK3568_Linux_fs/kernel/drivers/firmware/efi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
45 Export efi runtime memory maps to /sys/firmware/efi/runtime-map.
49 See also Documentation/ABI/testing/sysfs-firmware-efi-runtime-map.
70 Ranges can be set up to this value using comma-separated list.
86 resource, and set aside for direct-access (device-dax) by
89 device-dax kmem facility. Say N to have the kernel treat this
142 defined in its configuration, the bootloader will boot once
159 bool "Add support for Quark capsules with non-standard headers"
193 Thunderbolt Device ROM and GPU configuration data.
211 bool "EFI Runtime Configuration Interface Table Version 2 Support"
[all …]
/OK3568_Linux_fs/kernel/drivers/scsi/device_handler/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # SCSI Device Handler configuration
30 tristate "EMC CLARiiON Device Handler"
33 If you have a EMC CLARiiON select y. Otherwise, say N.
36 tristate "SPC-3 ALUA Device Handler"
39 SCSI Device handler for generic SPC-3 Asymmetric Logical Unit
/OK3568_Linux_fs/u-boot/board/timll/devkit3250/
H A Ddevkit3250_spl.c2 * Timll DevKit3250 board support, SPL board configuration
6 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/emc.h>
14 #include <asm/arch-lpc32xx/gpio.h>
20 * SDRAM K4S561632N-LC60 settings are selected in assumption that
51 writel((1 << 20), &gpio->p3_outp_clr); in spl_board_init()
/OK3568_Linux_fs/kernel/drivers/ntb/test/
H A Dntb_pingpong.c7 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
8 * Copyright (C) 2017 T-Platforms. All Rights Reserved.
21 * Copyright (C) 2015 EMC Corporation. All Rights Reserved.
22 * Copyright (C) 2017 T-Platforms. All Rights Reserved.
60 *-----------------------------------------------------------------------------
64 *-----------------------------------------------------------------------------
65 * Eg: get number of ping-pong cycles performed
88 MODULE_AUTHOR("Allen Hubbe <Allen.Hubbe@emc.com>");
121 link = ntb_link_is_up(pp->ntb, NULL, NULL); in pp_find_next_peer()
124 if (link & pp->nmask) in pp_find_next_peer()
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