1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _LPC32XX_EMC_H 8*4882a593Smuzhiyun #define _LPC32XX_EMC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <asm/types.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* EMC Registers */ 13*4882a593Smuzhiyun struct emc_regs { 14*4882a593Smuzhiyun u32 ctrl; /* Controls operation of the EMC */ 15*4882a593Smuzhiyun u32 status; /* Provides EMC status information */ 16*4882a593Smuzhiyun u32 config; /* Configures operation of the EMC */ 17*4882a593Smuzhiyun u32 reserved0[5]; 18*4882a593Smuzhiyun u32 control; /* Controls dyn memory operation */ 19*4882a593Smuzhiyun u32 refresh; /* Configures dyn memory refresh operation */ 20*4882a593Smuzhiyun u32 read_config; /* Configures the dyn memory read strategy */ 21*4882a593Smuzhiyun u32 reserved1; 22*4882a593Smuzhiyun u32 t_rp; /* Precharge command period */ 23*4882a593Smuzhiyun u32 t_ras; /* Active to precharge command period */ 24*4882a593Smuzhiyun u32 t_srex; /* Self-refresh exit time */ 25*4882a593Smuzhiyun u32 reserved2[2]; 26*4882a593Smuzhiyun u32 t_wr; /* Write recovery time */ 27*4882a593Smuzhiyun u32 t_rc; /* Active to active command period */ 28*4882a593Smuzhiyun u32 t_rfc; /* Auto-refresh period */ 29*4882a593Smuzhiyun u32 t_xsr; /* Exit self-refresh to active command time */ 30*4882a593Smuzhiyun u32 t_rrd; /* Active bank A to active bank B latency */ 31*4882a593Smuzhiyun u32 t_mrd; /* Load mode register to active command time */ 32*4882a593Smuzhiyun u32 t_cdlr; /* Last data in to read command time */ 33*4882a593Smuzhiyun u32 reserved3[8]; 34*4882a593Smuzhiyun u32 extended_wait; /* time for static memory rd/wr transfers */ 35*4882a593Smuzhiyun u32 reserved4[31]; 36*4882a593Smuzhiyun u32 config0; /* Configuration information for the SDRAM */ 37*4882a593Smuzhiyun u32 rascas0; /* RAS and CAS latencies for the SDRAM */ 38*4882a593Smuzhiyun u32 reserved5[6]; 39*4882a593Smuzhiyun u32 config1; /* Configuration information for the SDRAM */ 40*4882a593Smuzhiyun u32 rascas1; /* RAS and CAS latencies for the SDRAM */ 41*4882a593Smuzhiyun u32 reserved6[54]; 42*4882a593Smuzhiyun struct emc_stat_t { 43*4882a593Smuzhiyun u32 config; /* Static memory configuration */ 44*4882a593Smuzhiyun u32 waitwen; /* Delay from chip select to write enable */ 45*4882a593Smuzhiyun u32 waitoen; /* Delay to output enable */ 46*4882a593Smuzhiyun u32 waitrd; /* Delay to a read access */ 47*4882a593Smuzhiyun u32 waitpage; /* Delay for async page mode read */ 48*4882a593Smuzhiyun u32 waitwr; /* Delay to a write access */ 49*4882a593Smuzhiyun u32 waitturn; /* Number of bus turnaround cycles */ 50*4882a593Smuzhiyun u32 reserved; 51*4882a593Smuzhiyun } stat[4]; 52*4882a593Smuzhiyun u32 reserved7[96]; 53*4882a593Smuzhiyun struct emc_ahb_t { 54*4882a593Smuzhiyun u32 control; /* Control register for AHB */ 55*4882a593Smuzhiyun u32 status; /* Status register for AHB */ 56*4882a593Smuzhiyun u32 timeout; /* Timeout register for AHB */ 57*4882a593Smuzhiyun u32 reserved[5]; 58*4882a593Smuzhiyun } ahb[5]; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Static Memory Configuration Register bits */ 62*4882a593Smuzhiyun #define EMC_STAT_CONFIG_WP (1 << 20) 63*4882a593Smuzhiyun #define EMC_STAT_CONFIG_EW (1 << 8) 64*4882a593Smuzhiyun #define EMC_STAT_CONFIG_PB (1 << 7) 65*4882a593Smuzhiyun #define EMC_STAT_CONFIG_PC (1 << 6) 66*4882a593Smuzhiyun #define EMC_STAT_CONFIG_PM (1 << 3) 67*4882a593Smuzhiyun #define EMC_STAT_CONFIG_32BIT (2 << 0) 68*4882a593Smuzhiyun #define EMC_STAT_CONFIG_16BIT (1 << 0) 69*4882a593Smuzhiyun #define EMC_STAT_CONFIG_8BIT (0 << 0) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Static Memory Delay Registers */ 72*4882a593Smuzhiyun #define EMC_STAT_WAITWEN(n) (((n) - 1) & 0x0F) 73*4882a593Smuzhiyun #define EMC_STAT_WAITOEN(n) ((n) & 0x0F) 74*4882a593Smuzhiyun #define EMC_STAT_WAITRD(n) (((n) - 1) & 0x1F) 75*4882a593Smuzhiyun #define EMC_STAT_WAITPAGE(n) (((n) - 1) & 0x1F) 76*4882a593Smuzhiyun #define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) 77*4882a593Smuzhiyun #define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* EMC settings for DRAM */ 80*4882a593Smuzhiyun struct emc_dram_settings { 81*4882a593Smuzhiyun u32 cmddelay; 82*4882a593Smuzhiyun u32 config0; 83*4882a593Smuzhiyun u32 rascas0; 84*4882a593Smuzhiyun u32 rdconfig; 85*4882a593Smuzhiyun u32 trp; 86*4882a593Smuzhiyun u32 tras; 87*4882a593Smuzhiyun u32 tsrex; 88*4882a593Smuzhiyun u32 twr; 89*4882a593Smuzhiyun u32 trc; 90*4882a593Smuzhiyun u32 trfc; 91*4882a593Smuzhiyun u32 txsr; 92*4882a593Smuzhiyun u32 trrd; 93*4882a593Smuzhiyun u32 tmrd; 94*4882a593Smuzhiyun u32 tcdlr; 95*4882a593Smuzhiyun u32 refresh; 96*4882a593Smuzhiyun u32 mode; 97*4882a593Smuzhiyun u32 emode; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun #endif /* _LPC32XX_EMC_H */ 101