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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/mfd/
H A Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
12 - Guenter Roeck <groeck@chromium.org>
15 Google's ChromeOS EC is a microcontroller which talks to the AP and
17 The EC can be connected through various interfaces (I2C, SPI, and others)
23 - description:
[all …]
/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/i2c/
H A Dgoogle,cros-ec-i2c-tunnel.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $id: http://devicetree.org/schemas/i2c/google,cros-ec-i2c-tunnel.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: I2C bus that tunnels through the ChromeOS EC (cros-ec)
11 - Doug Anderson <dianders@chromium.org>
12 - Benson Leung <bleung@chromium.org>
13 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
16 On some ChromeOS board designs we've got a connection to the EC
18 other side of the EC (like a battery and PMIC). To get access to
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/OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/extcon/
H A Dextcon-usbc-cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/extcon/extcon-usbc-cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ChromeOS EC USB Type-C cable and accessories detection
10 - Benson Leung <bleung@chromium.org>
11 - Enric Balletbo i Serra <enric.balletbo@collabora.com>
17 The node for this device must be under a cros-ec node like google,cros-ec-spi
18 or google,cros-ec-i2c.
22 const: google,extcon-usbc-cros-ec
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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/misc/
H A Dcros-ec.txt8 - compatible = "google,cros-ec"
11 - spi-max-frequency : Sets the maximum frequency (in Hz) for SPI bus
13 - i2c-max-frequency : Sets the maximum frequency (in Hz) for I2C bus
15 - ec-interrupt : Selects the EC interrupt, defined as a GPIO according
17 - optimise-flash-write : Boolean property - if present then flash blocks
18 containing all 0xff will not be written, since we assume that the EC
22 to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
30 cros-ec@0 {
32 compatible = "google,cros-ec";
33 spi-max-frequency = <5000000>;
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/OK3568_Linux_fs/kernel/drivers/i2c/busses/
H A Di2c-cros-ec-tunnel.c1 // SPDX-License-Identifier: GPL-2.0+
2 // Expose an I2C passthrough to the ChromeOS EC.
8 #include <linux/i2c.h>
17 * struct ec_i2c_device - Driver data for I2C tunnel
20 * @adap: I2C adapter
21 * @ec: Pointer to EC device
22 * @remote_bus: The EC bus number we tunnel to on the other side.
30 struct cros_ec_device *ec; member
39 * ec_i2c_count_message - Count bytes needed for ec_i2c_construct_message
41 * @i2c_msgs: The i2c messages to read
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/OK3568_Linux_fs/u-boot/arch/arm/dts/
H A Drk3288-veyron-chromebook.dtsi6 * SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/rockchip,rk808.h>
10 #include <dt-bindings/input/input.h>
11 #include "rk3288-veyron.dtsi"
20 gpio_keys: gpio-keys {
21 pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;
26 linux,input-type = <5>; /* EV_SW */
27 debounce-interval = <1>;
28 gpio-key,wakeup;
32 gpio-charger {
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H A Dexynos5800-peach-pi.dts2 * SAMSUNG/GOOGLE Peach-Pit board device tree source
7 * SPDX-License-Identifier: GPL-2.0+
10 /dts-v1/;
15 cpu-model = "Exynos5800";
17 compatible = "google,pit-rev#", "google,pit",
21 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
22 hwid = "PIT TEST A-A 7848";
23 lazy-init = <1>;
29 pmic = "/i2c@12CA0000";
34 compatible = "pwm-backlight";
[all …]
H A Dexynos5420-peach-pit.dts2 * SAMSUNG/GOOGLE Peach-Pit board device tree source
7 * SPDX-License-Identifier: GPL-2.0+
10 /dts-v1/;
12 #include <dt-bindings/clock/maxim,max77802.h>
13 #include <dt-bindings/regulator/maxim,max77802.h>
18 compatible = "google,pit-rev#", "google,pit",
22 google,bad-wake-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
23 hwid = "PIT TEST A-A 7848";
24 lazy-init = <1>;
30 pmic = "/i2c@12CA0000";
[all …]
H A Dexynos5250-snow.dts12 /dts-v1/;
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/input/input.h>
23 i2c0 = "/i2c@12C60000";
24 i2c1 = "/i2c@12C70000";
25 i2c2 = "/i2c@12C80000";
26 i2c3 = "/i2c@12C90000";
27 i2c4 = "/i2c@12CA0000";
29 i2c5 = "/i2c@12CB0000";
[all …]
H A Dtegra124-nyan.dtsi1 #include <dt-bindings/input/input.h>
6 rtc0 = "/i2c@7000d000/pmic@40";
19 vdd-supply = <&vdd_3v3_hdmi>;
20 pll-supply = <&vdd_hdmi_pll>;
21 hdmi-supply = <&vdd_5v0_hdmi>;
23 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
24 nvidia,hpd-gpio =
36 vdd-supply = <&vdd_3v3_panel>;
50 i2c@7000c000 {
52 clock-frequency = <100000>;
[all …]
H A Dexynos5250-spring.dts7 * SPDX-License-Identifier: GPL-2.0
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/input/input.h>
21 i2c0 = "/i2c@12C60000";
22 i2c1 = "/i2c@12C70000";
23 i2c2 = "/i2c@12C80000";
24 i2c3 = "/i2c@12C90000";
25 i2c4 = "/i2c@12CA0000";
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/OK3568_Linux_fs/kernel/arch/arm/boot/dts/
H A Drk3288-veyron-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/clock/rockchip,rk808.h>
10 #include <dt-bindings/input/input.h>
11 #include "rk3288-veyron.dtsi"
12 #include "rk3288-veyron-analog-audio.dtsi"
13 #include "rk3288-veyron-edp.dtsi"
14 #include "rk3288-veyron-sdmmc.dtsi"
22 gpio-charger {
23 compatible = "gpio-charger";
24 charger-type = "mains";
[all …]
H A Dtegra124-nyan.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
7 rtc0 = "/i2c@7000d000/pmic@40";
13 stdout-path = "serial0:115200n8";
19 * missing a unit-address. However, the bootloader on these Chromebook
21 * Adding the unit-address causes the bootloader to create a /memory
33 /delete-node/ memory@80000000;
39 vdd-supply = <&vdd_3v3_hdmi>;
40 pll-supply = <&vdd_hdmi_pll>;
41 hdmi-supply = <&vdd_5v0_hdmi>;
[all …]
/OK3568_Linux_fs/u-boot/include/
H A Dcros_ec.h6 * SPDX-License-Identifier: GPL-2.0+
21 struct gpio_desc ec_int; /* GPIO used as EC interrupt line */
26 * These two buffers will always be dword-aligned and include enough
27 * space for up to 7 word-alignment bytes also, so we can ensure that
28 * the body of the message is always dword-aligned (64-bit).
41 * Hard-code the number of columns we happen to know we have right now. It
52 /* Holds information about the Chrome EC */
54 struct fmap_entry flash; /* Address and size of EC flash */
56 * Byte value of erased flash, or -1 if not known. It is normally
64 * Read the ID of the CROS-EC device
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/OK3568_Linux_fs/u-boot/doc/device-tree-bindings/i2c/
H A Di2c.txt1 U-Boot I2C
2 ----------
4 U-Boot's I2C model has the concept of an offset within a chip (I2C target
9 Apart from the controller-specific I2C bindings, U-Boot supports a special
13 - u-boot,i2c-offset-len - length of chip offset in bytes. If omitted the
18 -------
20 i2c4: i2c@12ca0000 {
21 cros-ec@1e {
23 compatible = "google,cros-ec";
24 i2c-max-frequency = <100000>;
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/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright 2016-2017 Google, Inc
8 #include <dt-bindings/input/input.h>
10 #include "rk3399-op1-opp.dtsi"
14 stdout-path = "serial2:115200n8";
23 * - Rails that only connect to the EC (or devices that the EC talks to)
25 * - Rails _are_ included if the rails go to the AP even if the AP
34 * - The EC controls the enable and the EC always enables a rail as
36 * - The rails are actually connected to each other by a jumper and
41 ppvar_sys: ppvar-sys {
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H A Drk3399-gru-chromebook.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Google Gru-Chromebook shared properties
8 #include "rk3399-gru.dtsi"
11 pp900_ap: pp900-ap {
12 compatible = "regulator-fixed";
13 regulator-name = "pp900_ap";
15 /* EC turns on w/ pp900_ap_en; always on for AP */
16 regulator-always-on;
17 regulator-boot-on;
18 regulator-min-microvolt = <900000>;
[all …]
/OK3568_Linux_fs/kernel/drivers/platform/chrome/
H A Dcros_ec_i2c.c1 // SPDX-License-Identifier: GPL-2.0
2 // I2C interface for ChromeOS Embedded Controller
10 #include <linux/i2c.h>
22 * byte 1-8 struct ec_host_request
23 * byte 10- response data
36 * byte 2-9 struct ec_host_response
37 * byte 10- response data
55 struct i2c_client *client = ec_dev->priv; in cros_ec_pkt_xfer_i2c()
56 int ret = -ENOMEM; in cros_ec_pkt_xfer_i2c()
69 i2c_msg[0].addr = client->addr; in cros_ec_pkt_xfer_i2c()
[all …]
H A Dcros_ec_spi.c1 // SPDX-License-Identifier: GPL-2.0
23 * Number of EC preamble bytes we read at a time. Since it takes
24 * about 400-500us for the EC to respond there is not a lot of
25 * point in tuning this. If the EC could respond faster then
34 * Allow for a long time for the EC to respond. We support i2c
43 * not directly passing i2c through, but it's too late for that for
50 * for this, clocking in at 2-3ms.
57 * If we go too fast, the EC will miss the transaction. We know that we
58 * need at least 70 us with the 16 MHz STM32 EC, so go with 200 us to be
64 * struct cros_ec_spi - information about a SPI-connected EC
[all …]
/OK3568_Linux_fs/u-boot/arch/sandbox/dts/
H A Dsandbox.dts1 /dts-v1/;
6 #address-cells = <1>;
7 #size-cells = <1>;
18 stdout-path = "/serial";
21 cros_ec: cros-ec@0 {
23 compatible = "google,cros-ec-sandbox";
26 * This describes the flash memory within the EC. Note
29 #address-cells = <1>;
30 #size-cells = <1>;
33 erase-value = <0>;
[all …]
/OK3568_Linux_fs/u-boot/drivers/misc/
H A Dcros_ec.c6 * SPDX-License-Identifier: GPL-2.0+
10 * This is the interface to the Chrome OS EC. It provides keyboard functions,
12 * provided to enable the EC software to be updated, talk to the EC's I2C bus
13 * and store a small amount of data in a memory which persists while the EC
20 #include <i2c.h>
27 #include <asm-generic/gpio.h>
28 #include <dm/device-internal.h>
30 #include <dm/uclass-internal.h>
53 if (cmd != -1) in cros_ec_dump_data()
62 * Calculate a simple 8-bit checksum of a data block
[all …]
/OK3568_Linux_fs/kernel/include/linux/platform_data/
H A Dcros_ec_proto.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * The EC is unresponsive for a time after a reboot command. Add a
31 * Max bus-specific overhead incurred by request/responses.
32 * I2C requires 1 additional byte for requests.
33 * I2C requires 2 additional bytes for responses.
41 * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
58 * struct cros_ec_command - Information about a ChromeOS EC command.
62 * @insize: Max number of bytes to accept from the EC.
63 * @result: EC's response to the command (separate from communication failure).
64 * @data: Where to put the incoming data from EC and outgoing data to EC.
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/mediatek/
H A Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
19 stdout-path = "serial0:115200n8";
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
31 clock-output-names = "clk32k";
35 compatible = "regulator-fixed";
36 regulator-name = "it6505_pp18";
[all …]
/OK3568_Linux_fs/kernel/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
23 /delete-node/ &hyp_mem;
24 /delete-node/ &xbl_mem;
25 /delete-node/ &aop_mem;
26 /delete-node/ &sec_apps_mem;
27 /delete-node/ &tz_mem;
35 reserved-memory {
[all …]
H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
26 stdout-path = "serial0:115200n8";
30 compatible = "pwm-backlight";
32 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
33 power-supply = <&ppvar_sys>;
34 pinctrl-names = "default";
35 pinctrl-0 = <&ap_edp_bklten>;
[all …]

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